mux.c 6.2 KB

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  1. /*
  2. * mux.c
  3. *
  4. * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem
  5. * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation version 2.
  10. *
  11. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12. * kind, whether express or implied; without even the implied warranty
  13. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. */
  16. #include <common.h>
  17. #include <asm/arch/sys_proto.h>
  18. #include <asm/arch/hardware.h>
  19. #include <asm/arch/mux.h>
  20. #include <asm/io.h>
  21. #include <i2c.h>
  22. #include "board.h"
  23. static struct module_pin_mux uart0_pin_mux[] = {
  24. {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
  25. {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
  26. {-1},
  27. };
  28. static struct module_pin_mux uart1_pin_mux[] = {
  29. {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
  30. {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
  31. {-1},
  32. };
  33. static struct module_pin_mux uart2_pin_mux[] = {
  34. {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
  35. {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
  36. {-1},
  37. };
  38. static struct module_pin_mux uart3_pin_mux[] = {
  39. {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
  40. {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
  41. {-1},
  42. };
  43. static struct module_pin_mux uart4_pin_mux[] = {
  44. {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
  45. {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
  46. {-1},
  47. };
  48. static struct module_pin_mux uart5_pin_mux[] = {
  49. {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
  50. {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
  51. {-1},
  52. };
  53. static struct module_pin_mux mmc0_pin_mux[] = {
  54. {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
  55. {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
  56. {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
  57. {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
  58. {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
  59. {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
  60. {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
  61. {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
  62. {-1},
  63. };
  64. static struct module_pin_mux mmc1_pin_mux[] = {
  65. {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
  66. {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
  67. {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
  68. {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
  69. {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
  70. {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
  71. {OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
  72. {OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
  73. {-1},
  74. };
  75. static struct module_pin_mux i2c0_pin_mux[] = {
  76. {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
  77. PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
  78. {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
  79. PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
  80. {-1},
  81. };
  82. static struct module_pin_mux i2c1_pin_mux[] = {
  83. {OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
  84. PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
  85. {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
  86. PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
  87. {-1},
  88. };
  89. static struct module_pin_mux rgmii1_pin_mux[] = {
  90. {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
  91. {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
  92. {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
  93. {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
  94. {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
  95. {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
  96. {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
  97. {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
  98. {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
  99. {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
  100. {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
  101. {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
  102. {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
  103. {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
  104. {-1},
  105. };
  106. static struct module_pin_mux mii1_pin_mux[] = {
  107. {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
  108. {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
  109. {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
  110. {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
  111. {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
  112. {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
  113. {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
  114. {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
  115. {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
  116. {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
  117. {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
  118. {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
  119. {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
  120. {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
  121. {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
  122. {-1},
  123. };
  124. void enable_uart0_pin_mux(void)
  125. {
  126. configure_module_pin_mux(uart0_pin_mux);
  127. }
  128. void enable_uart1_pin_mux(void)
  129. {
  130. configure_module_pin_mux(uart1_pin_mux);
  131. }
  132. void enable_uart2_pin_mux(void)
  133. {
  134. configure_module_pin_mux(uart2_pin_mux);
  135. }
  136. void enable_uart3_pin_mux(void)
  137. {
  138. configure_module_pin_mux(uart3_pin_mux);
  139. }
  140. void enable_uart4_pin_mux(void)
  141. {
  142. configure_module_pin_mux(uart4_pin_mux);
  143. }
  144. void enable_uart5_pin_mux(void)
  145. {
  146. configure_module_pin_mux(uart5_pin_mux);
  147. }
  148. void enable_i2c0_pin_mux(void)
  149. {
  150. configure_module_pin_mux(i2c0_pin_mux);
  151. }
  152. /* CPLD registers */
  153. #define I2C_CPLD_ADDR 0x35
  154. #define CFG_REG 0x10
  155. void enable_board_pin_mux(enum board_type board)
  156. {
  157. configure_module_pin_mux(i2c1_pin_mux);
  158. if (board == BAV335A)
  159. configure_module_pin_mux(mii1_pin_mux); /* MII Mode: 10/100MB */
  160. else
  161. configure_module_pin_mux(rgmii1_pin_mux); /* RGMII Mode: GB */
  162. configure_module_pin_mux(mmc0_pin_mux);
  163. configure_module_pin_mux(mmc1_pin_mux);
  164. }