ls2080aqds.h 12 KB

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  1. /*
  2. * Copyright 2015 Freescale Semiconductor
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #ifndef __LS2_QDS_H
  7. #define __LS2_QDS_H
  8. #include "ls2080a_common.h"
  9. #define CONFIG_DISPLAY_BOARDINFO
  10. #ifndef __ASSEMBLY__
  11. unsigned long get_board_sys_clk(void);
  12. unsigned long get_board_ddr_clk(void);
  13. #endif
  14. #define CONFIG_SYS_FSL_CLK
  15. #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
  16. #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
  17. #define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
  18. #define CONFIG_DDR_SPD
  19. #define CONFIG_DDR_ECC
  20. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  21. #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  22. #define SPD_EEPROM_ADDRESS1 0x51
  23. #define SPD_EEPROM_ADDRESS2 0x52
  24. #define SPD_EEPROM_ADDRESS3 0x53
  25. #define SPD_EEPROM_ADDRESS4 0x54
  26. #define SPD_EEPROM_ADDRESS5 0x55
  27. #define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
  28. #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
  29. #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
  30. #define CONFIG_DIMM_SLOTS_PER_CTLR 2
  31. #define CONFIG_CHIP_SELECTS_PER_CTRL 4
  32. #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  33. #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1
  34. #endif
  35. #define CONFIG_FSL_DDR_BIST /* enable built-in memory test */
  36. /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
  37. #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
  38. #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
  39. #define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
  40. #define CONFIG_SYS_NOR0_CSPR \
  41. (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
  42. CSPR_PORT_SIZE_16 | \
  43. CSPR_MSEL_NOR | \
  44. CSPR_V)
  45. #define CONFIG_SYS_NOR0_CSPR_EARLY \
  46. (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
  47. CSPR_PORT_SIZE_16 | \
  48. CSPR_MSEL_NOR | \
  49. CSPR_V)
  50. #define CONFIG_SYS_NOR1_CSPR \
  51. (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
  52. CSPR_PORT_SIZE_16 | \
  53. CSPR_MSEL_NOR | \
  54. CSPR_V)
  55. #define CONFIG_SYS_NOR1_CSPR_EARLY \
  56. (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
  57. CSPR_PORT_SIZE_16 | \
  58. CSPR_MSEL_NOR | \
  59. CSPR_V)
  60. #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
  61. #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
  62. FTIM0_NOR_TEADC(0x5) | \
  63. FTIM0_NOR_TEAHC(0x5))
  64. #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
  65. FTIM1_NOR_TRAD_NOR(0x1a) |\
  66. FTIM1_NOR_TSEQRAD_NOR(0x13))
  67. #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
  68. FTIM2_NOR_TCH(0x4) | \
  69. FTIM2_NOR_TWPH(0x0E) | \
  70. FTIM2_NOR_TWP(0x1c))
  71. #define CONFIG_SYS_NOR_FTIM3 0x04000000
  72. #define CONFIG_SYS_IFC_CCR 0x01000000
  73. #ifndef CONFIG_SYS_NO_FLASH
  74. #define CONFIG_FLASH_CFI_DRIVER
  75. #define CONFIG_SYS_FLASH_CFI
  76. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  77. #define CONFIG_SYS_FLASH_QUIET_TEST
  78. #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  79. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  80. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  81. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  82. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  83. #define CONFIG_SYS_FLASH_EMPTY_INFO
  84. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
  85. CONFIG_SYS_FLASH_BASE + 0x40000000}
  86. #endif
  87. #define CONFIG_NAND_FSL_IFC
  88. #define CONFIG_SYS_NAND_MAX_ECCPOS 256
  89. #define CONFIG_SYS_NAND_MAX_OOBFREE 2
  90. #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
  91. #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  92. | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  93. | CSPR_MSEL_NAND /* MSEL = NAND */ \
  94. | CSPR_V)
  95. #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
  96. #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
  97. | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
  98. | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
  99. | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
  100. | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
  101. | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
  102. | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
  103. #define CONFIG_SYS_NAND_ONFI_DETECTION
  104. /* ONFI NAND Flash mode0 Timing Params */
  105. #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
  106. FTIM0_NAND_TWP(0x18) | \
  107. FTIM0_NAND_TWCHT(0x07) | \
  108. FTIM0_NAND_TWH(0x0a))
  109. #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
  110. FTIM1_NAND_TWBE(0x39) | \
  111. FTIM1_NAND_TRR(0x0e) | \
  112. FTIM1_NAND_TRP(0x18))
  113. #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
  114. FTIM2_NAND_TREH(0x0a) | \
  115. FTIM2_NAND_TWHRE(0x1e))
  116. #define CONFIG_SYS_NAND_FTIM3 0x0
  117. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  118. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  119. #define CONFIG_MTD_NAND_VERIFY_WRITE
  120. #define CONFIG_CMD_NAND
  121. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
  122. #define CONFIG_FSL_QIXIS /* use common QIXIS code */
  123. #define QIXIS_LBMAP_SWITCH 0x06
  124. #define QIXIS_LBMAP_MASK 0x0f
  125. #define QIXIS_LBMAP_SHIFT 0
  126. #define QIXIS_LBMAP_DFLTBANK 0x00
  127. #define QIXIS_LBMAP_ALTBANK 0x04
  128. #define QIXIS_LBMAP_NAND 0x09
  129. #define QIXIS_RST_CTL_RESET 0x31
  130. #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
  131. #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
  132. #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
  133. #define QIXIS_RCW_SRC_NAND 0x107
  134. #define QIXIS_RST_FORCE_MEM 0x01
  135. #define CONFIG_SYS_CSPR3_EXT (0x0)
  136. #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
  137. | CSPR_PORT_SIZE_8 \
  138. | CSPR_MSEL_GPCM \
  139. | CSPR_V)
  140. #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
  141. | CSPR_PORT_SIZE_8 \
  142. | CSPR_MSEL_GPCM \
  143. | CSPR_V)
  144. #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
  145. #define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
  146. /* QIXIS Timing parameters for IFC CS3 */
  147. #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
  148. FTIM0_GPCM_TEADC(0x0e) | \
  149. FTIM0_GPCM_TEAHC(0x0e))
  150. #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
  151. FTIM1_GPCM_TRAD(0x3f))
  152. #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
  153. FTIM2_GPCM_TCH(0xf) | \
  154. FTIM2_GPCM_TWP(0x3E))
  155. #define CONFIG_SYS_CS3_FTIM3 0x0
  156. #if defined(CONFIG_SPL) && defined(CONFIG_NAND)
  157. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  158. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY
  159. #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR
  160. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
  161. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  162. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  163. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  164. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  165. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  166. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
  167. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY
  168. #define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR
  169. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY
  170. #define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK
  171. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
  172. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
  173. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
  174. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
  175. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
  176. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
  177. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
  178. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
  179. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
  180. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
  181. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
  182. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
  183. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
  184. #define CONFIG_ENV_IS_IN_NAND
  185. #define CONFIG_ENV_OFFSET (896 * 1024)
  186. #define CONFIG_ENV_SECT_SIZE 0x20000
  187. #define CONFIG_ENV_SIZE 0x2000
  188. #define CONFIG_SPL_PAD_TO 0x20000
  189. #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024)
  190. #define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024)
  191. #else
  192. #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
  193. #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
  194. #define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
  195. #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
  196. #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
  197. #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
  198. #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
  199. #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
  200. #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
  201. #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
  202. #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
  203. #define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
  204. #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
  205. #define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
  206. #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
  207. #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
  208. #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
  209. #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
  210. #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
  211. #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
  212. #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
  213. #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
  214. #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
  215. #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
  216. #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
  217. #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
  218. #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
  219. #define CONFIG_ENV_IS_IN_FLASH
  220. #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
  221. #define CONFIG_ENV_SECT_SIZE 0x20000
  222. #define CONFIG_ENV_SIZE 0x2000
  223. #endif
  224. /* Debug Server firmware */
  225. #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
  226. #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
  227. #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
  228. /*
  229. * I2C
  230. */
  231. #define I2C_MUX_PCA_ADDR 0x77
  232. #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
  233. /* I2C bus multiplexer */
  234. #define I2C_MUX_CH_DEFAULT 0x8
  235. /* SPI */
  236. #ifdef CONFIG_FSL_DSPI
  237. #define CONFIG_CMD_SF
  238. #define CONFIG_SPI_FLASH
  239. #endif
  240. /*
  241. * MMC
  242. */
  243. #ifdef CONFIG_MMC
  244. #define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
  245. QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
  246. #endif
  247. /*
  248. * RTC configuration
  249. */
  250. #define RTC
  251. #define CONFIG_RTC_DS3231 1
  252. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  253. #define CONFIG_CMD_DATE
  254. /* EEPROM */
  255. #define CONFIG_ID_EEPROM
  256. #define CONFIG_CMD_EEPROM
  257. #define CONFIG_SYS_I2C_EEPROM_NXID
  258. #define CONFIG_SYS_EEPROM_BUS_NUM 0
  259. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  260. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  261. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  262. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
  263. #define CONFIG_FSL_MEMAC
  264. #define CONFIG_PCI /* Enable PCIE */
  265. #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
  266. #ifdef CONFIG_PCI
  267. #define CONFIG_PCI_PNP
  268. #define CONFIG_PCI_SCAN_SHOW
  269. #define CONFIG_CMD_PCI
  270. #endif
  271. /* MMC */
  272. #define CONFIG_MMC
  273. #ifdef CONFIG_MMC
  274. #define CONFIG_CMD_MMC
  275. #define CONFIG_FSL_ESDHC
  276. #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  277. #define CONFIG_GENERIC_MMC
  278. #define CONFIG_CMD_FAT
  279. #define CONFIG_DOS_PARTITION
  280. #endif
  281. /* Initial environment variables */
  282. #undef CONFIG_EXTRA_ENV_SETTINGS
  283. #define CONFIG_EXTRA_ENV_SETTINGS \
  284. "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  285. "loadaddr=0x80100000\0" \
  286. "kernel_addr=0x100000\0" \
  287. "ramdisk_addr=0x800000\0" \
  288. "ramdisk_size=0x2000000\0" \
  289. "fdt_high=0xa0000000\0" \
  290. "initrd_high=0xffffffffffffffff\0" \
  291. "kernel_start=0x581100000\0" \
  292. "kernel_load=0xa0000000\0" \
  293. "kernel_size=0x28000000\0"
  294. #ifdef CONFIG_FSL_MC_ENET
  295. #define CONFIG_FSL_MEMAC
  296. #define CONFIG_PHYLIB
  297. #define CONFIG_PHYLIB_10G
  298. #define CONFIG_CMD_MII
  299. #define CONFIG_PHY_VITESSE
  300. #define CONFIG_PHY_REALTEK
  301. #define CONFIG_PHY_TERANETICS
  302. #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  303. #define SGMII_CARD_PORT2_PHY_ADDR 0x1d
  304. #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  305. #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  306. #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
  307. #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
  308. #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
  309. #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
  310. #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
  311. #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
  312. #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
  313. #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
  314. #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
  315. #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
  316. #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
  317. #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
  318. #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
  319. #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
  320. #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
  321. #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
  322. #define CONFIG_MII /* MII PHY management */
  323. #define CONFIG_ETHPRIME "DPNI1"
  324. #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
  325. #endif
  326. /*
  327. * USB
  328. */
  329. #define CONFIG_HAS_FSL_XHCI_USB
  330. #define CONFIG_USB_XHCI
  331. #define CONFIG_USB_XHCI_FSL
  332. #define CONFIG_USB_XHCI_DWC3
  333. #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  334. #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
  335. #define CONFIG_CMD_USB
  336. #define CONFIG_USB_STORAGE
  337. #define CONFIG_CMD_EXT2
  338. #endif /* __LS2_QDS_H */