pcie_layerscape.c 19 KB

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  1. /*
  2. * Copyright 2014-2015 Freescale Semiconductor, Inc.
  3. * Layerscape PCIe driver
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <asm/arch/fsl_serdes.h>
  9. #include <pci.h>
  10. #include <asm/io.h>
  11. #include <errno.h>
  12. #include <malloc.h>
  13. #ifdef CONFIG_FSL_LAYERSCAPE
  14. #include <asm/arch/fdt.h>
  15. #endif
  16. #ifndef CONFIG_SYS_PCI_MEMORY_BUS
  17. #define CONFIG_SYS_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
  18. #endif
  19. #ifndef CONFIG_SYS_PCI_MEMORY_PHYS
  20. #define CONFIG_SYS_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE
  21. #endif
  22. #ifndef CONFIG_SYS_PCI_MEMORY_SIZE
  23. #define CONFIG_SYS_PCI_MEMORY_SIZE (2 * 1024 * 1024 * 1024UL) /* 2G */
  24. #endif
  25. #ifndef CONFIG_SYS_PCI_EP_MEMORY_BASE
  26. #define CONFIG_SYS_PCI_EP_MEMORY_BASE CONFIG_SYS_LOAD_ADDR
  27. #endif
  28. /* iATU registers */
  29. #define PCIE_ATU_VIEWPORT 0x900
  30. #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
  31. #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
  32. #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
  33. #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
  34. #define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
  35. #define PCIE_ATU_REGION_INDEX3 (0x3 << 0)
  36. #define PCIE_ATU_CR1 0x904
  37. #define PCIE_ATU_TYPE_MEM (0x0 << 0)
  38. #define PCIE_ATU_TYPE_IO (0x2 << 0)
  39. #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
  40. #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
  41. #define PCIE_ATU_CR2 0x908
  42. #define PCIE_ATU_ENABLE (0x1 << 31)
  43. #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
  44. #define PCIE_ATU_BAR_NUM(bar) ((bar) << 8)
  45. #define PCIE_ATU_LOWER_BASE 0x90C
  46. #define PCIE_ATU_UPPER_BASE 0x910
  47. #define PCIE_ATU_LIMIT 0x914
  48. #define PCIE_ATU_LOWER_TARGET 0x918
  49. #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
  50. #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
  51. #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
  52. #define PCIE_ATU_UPPER_TARGET 0x91C
  53. /* LUT registers */
  54. #define PCIE_LUT_BASE 0x80000
  55. #define PCIE_LUT_LCTRL0 0x7F8
  56. #define PCIE_LUT_DBG 0x7FC
  57. #define PCIE_DBI_RO_WR_EN 0x8bc
  58. #define PCIE_LINK_CAP 0x7c
  59. #define PCIE_LINK_SPEED_MASK 0xf
  60. #define PCIE_LINK_STA 0x82
  61. #define LTSSM_STATE_MASK 0x3f
  62. #define LTSSM_PCIE_L0 0x11 /* L0 state */
  63. #define PCIE_DBI_SIZE 0x100000 /* 1M */
  64. #define PCIE_LCTRL0_CFG2_ENABLE (1 << 31)
  65. #define PCIE_LCTRL0_VF(vf) ((vf) << 22)
  66. #define PCIE_LCTRL0_PF(pf) ((pf) << 16)
  67. #define PCIE_LCTRL0_VF_ACTIVE (1 << 21)
  68. #define PCIE_LCTRL0_VAL(pf, vf) (PCIE_LCTRL0_PF(pf) | \
  69. PCIE_LCTRL0_VF(vf) | \
  70. ((vf) == 0 ? 0 : PCIE_LCTRL0_VF_ACTIVE) | \
  71. PCIE_LCTRL0_CFG2_ENABLE)
  72. #define PCIE_NO_SRIOV_BAR_BASE 0x1000
  73. #define PCIE_PF_NUM 2
  74. #define PCIE_VF_NUM 64
  75. #define PCIE_BAR0_SIZE (4 * 1024) /* 4K */
  76. #define PCIE_BAR1_SIZE (8 * 1024) /* 8K for MSIX */
  77. #define PCIE_BAR2_SIZE (4 * 1024) /* 4K */
  78. #define PCIE_BAR4_SIZE (1 * 1024 * 1024) /* 1M */
  79. struct ls_pcie {
  80. int idx;
  81. void __iomem *dbi;
  82. void __iomem *va_cfg0;
  83. void __iomem *va_cfg1;
  84. struct pci_controller hose;
  85. };
  86. struct ls_pcie_info {
  87. unsigned long regs;
  88. int pci_num;
  89. u64 phys_base;
  90. u64 cfg0_phys;
  91. u64 cfg0_size;
  92. u64 cfg1_phys;
  93. u64 cfg1_size;
  94. u64 mem_bus;
  95. u64 mem_phys;
  96. u64 mem_size;
  97. u64 io_bus;
  98. u64 io_phys;
  99. u64 io_size;
  100. };
  101. #define SET_LS_PCIE_INFO(x, num) \
  102. { \
  103. x.regs = CONFIG_SYS_PCIE##num##_ADDR; \
  104. x.phys_base = CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
  105. x.cfg0_phys = CONFIG_SYS_PCIE_CFG0_PHYS_OFF + \
  106. CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
  107. x.cfg0_size = CONFIG_SYS_PCIE_CFG0_SIZE; \
  108. x.cfg1_phys = CONFIG_SYS_PCIE_CFG1_PHYS_OFF + \
  109. CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
  110. x.cfg1_size = CONFIG_SYS_PCIE_CFG1_SIZE; \
  111. x.mem_bus = CONFIG_SYS_PCIE_MEM_BUS; \
  112. x.mem_phys = CONFIG_SYS_PCIE_MEM_PHYS_OFF + \
  113. CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
  114. x.mem_size = CONFIG_SYS_PCIE_MEM_SIZE; \
  115. x.io_bus = CONFIG_SYS_PCIE_IO_BUS; \
  116. x.io_phys = CONFIG_SYS_PCIE_IO_PHYS_OFF + \
  117. CONFIG_SYS_PCIE##num##_PHYS_ADDR; \
  118. x.io_size = CONFIG_SYS_PCIE_IO_SIZE; \
  119. x.pci_num = num; \
  120. }
  121. #ifdef CONFIG_LS102XA
  122. #include <asm/arch/immap_ls102xa.h>
  123. /* PEX1/2 Misc Ports Status Register */
  124. #define LTSSM_STATE_SHIFT 20
  125. static int ls_pcie_link_state(struct ls_pcie *pcie)
  126. {
  127. u32 state;
  128. struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  129. state = in_be32(&scfg->pexmscportsr[pcie->idx]);
  130. state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
  131. if (state < LTSSM_PCIE_L0) {
  132. debug("....PCIe link error. LTSSM=0x%02x.\n", state);
  133. return 0;
  134. }
  135. return 1;
  136. }
  137. #else
  138. static int ls_pcie_link_state(struct ls_pcie *pcie)
  139. {
  140. u32 state;
  141. state = readl(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) &
  142. LTSSM_STATE_MASK;
  143. if (state < LTSSM_PCIE_L0) {
  144. debug("....PCIe link error. LTSSM=0x%02x.\n", state);
  145. return 0;
  146. }
  147. return 1;
  148. }
  149. #endif
  150. static int ls_pcie_link_up(struct ls_pcie *pcie)
  151. {
  152. int state;
  153. u32 cap;
  154. state = ls_pcie_link_state(pcie);
  155. if (state)
  156. return state;
  157. /* Try to download speed to gen1 */
  158. cap = readl(pcie->dbi + PCIE_LINK_CAP);
  159. writel((cap & (~PCIE_LINK_SPEED_MASK)) | 1, pcie->dbi + PCIE_LINK_CAP);
  160. /*
  161. * Notice: the following delay has critical impact on link training
  162. * if too short (<30ms) the link doesn't get up.
  163. */
  164. mdelay(100);
  165. state = ls_pcie_link_state(pcie);
  166. if (state)
  167. return state;
  168. writel(cap, pcie->dbi + PCIE_LINK_CAP);
  169. return 0;
  170. }
  171. static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev)
  172. {
  173. writel(PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
  174. pcie->dbi + PCIE_ATU_VIEWPORT);
  175. writel(busdev, pcie->dbi + PCIE_ATU_LOWER_TARGET);
  176. }
  177. static void ls_pcie_cfg1_set_busdev(struct ls_pcie *pcie, u32 busdev)
  178. {
  179. writel(PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
  180. pcie->dbi + PCIE_ATU_VIEWPORT);
  181. writel(busdev, pcie->dbi + PCIE_ATU_LOWER_TARGET);
  182. }
  183. static void ls_pcie_iatu_outbound_set(struct ls_pcie *pcie, int idx, int type,
  184. u64 phys, u64 bus_addr, pci_size_t size)
  185. {
  186. writel(PCIE_ATU_REGION_OUTBOUND | idx, pcie->dbi + PCIE_ATU_VIEWPORT);
  187. writel((u32)phys, pcie->dbi + PCIE_ATU_LOWER_BASE);
  188. writel(phys >> 32, pcie->dbi + PCIE_ATU_UPPER_BASE);
  189. writel(phys + size - 1, pcie->dbi + PCIE_ATU_LIMIT);
  190. writel((u32)bus_addr, pcie->dbi + PCIE_ATU_LOWER_TARGET);
  191. writel(bus_addr >> 32, pcie->dbi + PCIE_ATU_UPPER_TARGET);
  192. writel(type, pcie->dbi + PCIE_ATU_CR1);
  193. writel(PCIE_ATU_ENABLE, pcie->dbi + PCIE_ATU_CR2);
  194. }
  195. /* Use bar match mode and MEM type as default */
  196. static void ls_pcie_iatu_inbound_set(struct ls_pcie *pcie, int idx,
  197. int bar, u64 phys)
  198. {
  199. writel(PCIE_ATU_REGION_INBOUND | idx, pcie->dbi + PCIE_ATU_VIEWPORT);
  200. writel((u32)phys, pcie->dbi + PCIE_ATU_LOWER_TARGET);
  201. writel(phys >> 32, pcie->dbi + PCIE_ATU_UPPER_TARGET);
  202. writel(PCIE_ATU_TYPE_MEM, pcie->dbi + PCIE_ATU_CR1);
  203. writel(PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE |
  204. PCIE_ATU_BAR_NUM(bar), pcie->dbi + PCIE_ATU_CR2);
  205. }
  206. static void ls_pcie_setup_atu(struct ls_pcie *pcie, struct ls_pcie_info *info)
  207. {
  208. #ifdef DEBUG
  209. int i;
  210. #endif
  211. /* ATU 0 : OUTBOUND : CFG0 */
  212. ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
  213. PCIE_ATU_TYPE_CFG0,
  214. info->cfg0_phys,
  215. 0,
  216. info->cfg0_size);
  217. /* ATU 1 : OUTBOUND : CFG1 */
  218. ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1,
  219. PCIE_ATU_TYPE_CFG1,
  220. info->cfg1_phys,
  221. 0,
  222. info->cfg1_size);
  223. /* ATU 2 : OUTBOUND : MEM */
  224. ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX2,
  225. PCIE_ATU_TYPE_MEM,
  226. info->mem_phys,
  227. info->mem_bus,
  228. info->mem_size);
  229. /* ATU 3 : OUTBOUND : IO */
  230. ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX3,
  231. PCIE_ATU_TYPE_IO,
  232. info->io_phys,
  233. info->io_bus,
  234. info->io_size);
  235. #ifdef DEBUG
  236. for (i = 0; i <= PCIE_ATU_REGION_INDEX3; i++) {
  237. writel(PCIE_ATU_REGION_OUTBOUND | i,
  238. pcie->dbi + PCIE_ATU_VIEWPORT);
  239. debug("iATU%d:\n", i);
  240. debug("\tLOWER PHYS 0x%08x\n",
  241. readl(pcie->dbi + PCIE_ATU_LOWER_BASE));
  242. debug("\tUPPER PHYS 0x%08x\n",
  243. readl(pcie->dbi + PCIE_ATU_UPPER_BASE));
  244. debug("\tLOWER BUS 0x%08x\n",
  245. readl(pcie->dbi + PCIE_ATU_LOWER_TARGET));
  246. debug("\tUPPER BUS 0x%08x\n",
  247. readl(pcie->dbi + PCIE_ATU_UPPER_TARGET));
  248. debug("\tLIMIT 0x%08x\n",
  249. readl(pcie->dbi + PCIE_ATU_LIMIT));
  250. debug("\tCR1 0x%08x\n",
  251. readl(pcie->dbi + PCIE_ATU_CR1));
  252. debug("\tCR2 0x%08x\n",
  253. readl(pcie->dbi + PCIE_ATU_CR2));
  254. }
  255. #endif
  256. }
  257. int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
  258. {
  259. /* Do not skip controller */
  260. return 0;
  261. }
  262. static int ls_pcie_addr_valid(struct pci_controller *hose, pci_dev_t d)
  263. {
  264. if (PCI_DEV(d) > 0)
  265. return -EINVAL;
  266. /* Controller does not support multi-function in RC mode */
  267. if ((PCI_BUS(d) == hose->first_busno) && (PCI_FUNC(d) > 0))
  268. return -EINVAL;
  269. return 0;
  270. }
  271. static int ls_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
  272. int where, u32 *val)
  273. {
  274. struct ls_pcie *pcie = hose->priv_data;
  275. u32 busdev, *addr;
  276. if (ls_pcie_addr_valid(hose, d)) {
  277. *val = 0xffffffff;
  278. return -EINVAL;
  279. }
  280. if (PCI_BUS(d) == hose->first_busno) {
  281. addr = pcie->dbi + (where & ~0x3);
  282. } else {
  283. busdev = PCIE_ATU_BUS(PCI_BUS(d)) |
  284. PCIE_ATU_DEV(PCI_DEV(d)) |
  285. PCIE_ATU_FUNC(PCI_FUNC(d));
  286. if (PCI_BUS(d) == hose->first_busno + 1) {
  287. ls_pcie_cfg0_set_busdev(pcie, busdev);
  288. addr = pcie->va_cfg0 + (where & ~0x3);
  289. } else {
  290. ls_pcie_cfg1_set_busdev(pcie, busdev);
  291. addr = pcie->va_cfg1 + (where & ~0x3);
  292. }
  293. }
  294. *val = readl(addr);
  295. return 0;
  296. }
  297. static int ls_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
  298. int where, u32 val)
  299. {
  300. struct ls_pcie *pcie = hose->priv_data;
  301. u32 busdev, *addr;
  302. if (ls_pcie_addr_valid(hose, d))
  303. return -EINVAL;
  304. if (PCI_BUS(d) == hose->first_busno) {
  305. addr = pcie->dbi + (where & ~0x3);
  306. } else {
  307. busdev = PCIE_ATU_BUS(PCI_BUS(d)) |
  308. PCIE_ATU_DEV(PCI_DEV(d)) |
  309. PCIE_ATU_FUNC(PCI_FUNC(d));
  310. if (PCI_BUS(d) == hose->first_busno + 1) {
  311. ls_pcie_cfg0_set_busdev(pcie, busdev);
  312. addr = pcie->va_cfg0 + (where & ~0x3);
  313. } else {
  314. ls_pcie_cfg1_set_busdev(pcie, busdev);
  315. addr = pcie->va_cfg1 + (where & ~0x3);
  316. }
  317. }
  318. writel(val, addr);
  319. return 0;
  320. }
  321. static void ls_pcie_setup_ctrl(struct ls_pcie *pcie,
  322. struct ls_pcie_info *info)
  323. {
  324. struct pci_controller *hose = &pcie->hose;
  325. pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
  326. ls_pcie_setup_atu(pcie, info);
  327. pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0);
  328. /* program correct class for RC */
  329. writel(1, pcie->dbi + PCIE_DBI_RO_WR_EN);
  330. pci_hose_write_config_word(hose, dev, PCI_CLASS_DEVICE,
  331. PCI_CLASS_BRIDGE_PCI);
  332. #ifndef CONFIG_LS102XA
  333. writel(0, pcie->dbi + PCIE_DBI_RO_WR_EN);
  334. #endif
  335. }
  336. static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie,
  337. struct ls_pcie_info *info)
  338. {
  339. u64 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE;
  340. /* ATU 0 : INBOUND : map BAR0 */
  341. ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX0, 0, phys);
  342. /* ATU 1 : INBOUND : map BAR1 */
  343. phys += PCIE_BAR1_SIZE;
  344. ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX1, 1, phys);
  345. /* ATU 2 : INBOUND : map BAR2 */
  346. phys += PCIE_BAR2_SIZE;
  347. ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX2, 2, phys);
  348. /* ATU 3 : INBOUND : map BAR4 */
  349. phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR4_SIZE;
  350. ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX3, 4, phys);
  351. /* ATU 0 : OUTBOUND : map 4G MEM */
  352. ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
  353. PCIE_ATU_TYPE_MEM,
  354. info->phys_base,
  355. 0,
  356. 4 * 1024 * 1024 * 1024ULL);
  357. }
  358. /* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */
  359. static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size)
  360. {
  361. if (size < 4 * 1024)
  362. return;
  363. switch (bar) {
  364. case 0:
  365. writel(size - 1, bar_base + PCI_BASE_ADDRESS_0);
  366. break;
  367. case 1:
  368. writel(size - 1, bar_base + PCI_BASE_ADDRESS_1);
  369. break;
  370. case 2:
  371. writel(size - 1, bar_base + PCI_BASE_ADDRESS_2);
  372. writel(0, bar_base + PCI_BASE_ADDRESS_3);
  373. break;
  374. case 4:
  375. writel(size - 1, bar_base + PCI_BASE_ADDRESS_4);
  376. writel(0, bar_base + PCI_BASE_ADDRESS_5);
  377. break;
  378. default:
  379. break;
  380. }
  381. }
  382. static void ls_pcie_ep_setup_bars(void *bar_base)
  383. {
  384. /* BAR0 - 32bit - 4K configuration */
  385. ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE);
  386. /* BAR1 - 32bit - 8K MSIX*/
  387. ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE);
  388. /* BAR2 - 64bit - 4K MEM desciptor */
  389. ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE);
  390. /* BAR4 - 64bit - 1M MEM*/
  391. ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
  392. }
  393. static void ls_pcie_setup_ep(struct ls_pcie *pcie, struct ls_pcie_info *info)
  394. {
  395. struct pci_controller *hose = &pcie->hose;
  396. pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
  397. int sriov;
  398. sriov = pci_hose_find_ext_capability(hose, dev, PCI_EXT_CAP_ID_SRIOV);
  399. if (sriov) {
  400. int pf, vf;
  401. for (pf = 0; pf < PCIE_PF_NUM; pf++) {
  402. for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
  403. writel(PCIE_LCTRL0_VAL(pf, vf),
  404. pcie->dbi + PCIE_LUT_BASE +
  405. PCIE_LUT_LCTRL0);
  406. ls_pcie_ep_setup_bars(pcie->dbi);
  407. ls_pcie_ep_setup_atu(pcie, info);
  408. }
  409. }
  410. /* Disable CFG2 */
  411. writel(0, pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_LCTRL0);
  412. } else {
  413. ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
  414. ls_pcie_ep_setup_atu(pcie, info);
  415. }
  416. }
  417. int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info *info)
  418. {
  419. struct ls_pcie *pcie;
  420. struct pci_controller *hose;
  421. int num = dev - PCIE1;
  422. pci_dev_t pdev = PCI_BDF(busno, 0, 0);
  423. int i, linkup, ep_mode;
  424. u8 header_type;
  425. u16 temp16;
  426. if (!is_serdes_configured(dev)) {
  427. printf("PCIe%d: disabled\n", num + 1);
  428. return busno;
  429. }
  430. pcie = malloc(sizeof(*pcie));
  431. if (!pcie)
  432. return busno;
  433. memset(pcie, 0, sizeof(*pcie));
  434. hose = &pcie->hose;
  435. hose->priv_data = pcie;
  436. hose->first_busno = busno;
  437. pcie->idx = num;
  438. pcie->dbi = map_physmem(info->regs, PCIE_DBI_SIZE, MAP_NOCACHE);
  439. pcie->va_cfg0 = map_physmem(info->cfg0_phys,
  440. info->cfg0_size,
  441. MAP_NOCACHE);
  442. pcie->va_cfg1 = map_physmem(info->cfg1_phys,
  443. info->cfg1_size,
  444. MAP_NOCACHE);
  445. /* outbound memory */
  446. pci_set_region(&hose->regions[0],
  447. (pci_size_t)info->mem_bus,
  448. (phys_size_t)info->mem_phys,
  449. (pci_size_t)info->mem_size,
  450. PCI_REGION_MEM);
  451. /* outbound io */
  452. pci_set_region(&hose->regions[1],
  453. (pci_size_t)info->io_bus,
  454. (phys_size_t)info->io_phys,
  455. (pci_size_t)info->io_size,
  456. PCI_REGION_IO);
  457. /* System memory space */
  458. pci_set_region(&hose->regions[2],
  459. CONFIG_SYS_PCI_MEMORY_BUS,
  460. CONFIG_SYS_PCI_MEMORY_PHYS,
  461. CONFIG_SYS_PCI_MEMORY_SIZE,
  462. PCI_REGION_SYS_MEMORY);
  463. hose->region_count = 3;
  464. for (i = 0; i < hose->region_count; i++)
  465. debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n",
  466. i,
  467. (u64)hose->regions[i].phys_start,
  468. (u64)hose->regions[i].bus_start,
  469. (u64)hose->regions[i].size,
  470. hose->regions[i].flags);
  471. pci_set_ops(hose,
  472. pci_hose_read_config_byte_via_dword,
  473. pci_hose_read_config_word_via_dword,
  474. ls_pcie_read_config,
  475. pci_hose_write_config_byte_via_dword,
  476. pci_hose_write_config_word_via_dword,
  477. ls_pcie_write_config);
  478. pci_hose_read_config_byte(hose, pdev, PCI_HEADER_TYPE, &header_type);
  479. ep_mode = (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
  480. printf("PCIe%u: %s ", info->pci_num,
  481. ep_mode ? "Endpoint" : "Root Complex");
  482. if (ep_mode)
  483. ls_pcie_setup_ep(pcie, info);
  484. else
  485. ls_pcie_setup_ctrl(pcie, info);
  486. linkup = ls_pcie_link_up(pcie);
  487. if (!linkup) {
  488. /* Let the user know there's no PCIe link */
  489. printf("no link, regs @ 0x%lx\n", info->regs);
  490. hose->last_busno = hose->first_busno;
  491. return busno;
  492. }
  493. /* Print the negotiated PCIe link width */
  494. pci_hose_read_config_word(hose, pdev, PCIE_LINK_STA, &temp16);
  495. printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4,
  496. (temp16 & 0xf), info->regs);
  497. if (ep_mode)
  498. return busno;
  499. pci_register_hose(hose);
  500. hose->last_busno = pci_hose_scan(hose);
  501. printf("PCIe%x: Bus %02x - %02x\n",
  502. info->pci_num, hose->first_busno, hose->last_busno);
  503. return hose->last_busno + 1;
  504. }
  505. int ls_pcie_init_board(int busno)
  506. {
  507. struct ls_pcie_info info;
  508. #ifdef CONFIG_PCIE1
  509. SET_LS_PCIE_INFO(info, 1);
  510. busno = ls_pcie_init_ctrl(busno, PCIE1, &info);
  511. #endif
  512. #ifdef CONFIG_PCIE2
  513. SET_LS_PCIE_INFO(info, 2);
  514. busno = ls_pcie_init_ctrl(busno, PCIE2, &info);
  515. #endif
  516. #ifdef CONFIG_PCIE3
  517. SET_LS_PCIE_INFO(info, 3);
  518. busno = ls_pcie_init_ctrl(busno, PCIE3, &info);
  519. #endif
  520. #ifdef CONFIG_PCIE4
  521. SET_LS_PCIE_INFO(info, 4);
  522. busno = ls_pcie_init_ctrl(busno, PCIE4, &info);
  523. #endif
  524. return busno;
  525. }
  526. void pci_init_board(void)
  527. {
  528. ls_pcie_init_board(0);
  529. }
  530. #ifdef CONFIG_OF_BOARD_SETUP
  531. #include <libfdt.h>
  532. #include <fdt_support.h>
  533. static void ft_pcie_ls_setup(void *blob, const char *pci_compat,
  534. unsigned long ctrl_addr, enum srds_prtcl dev)
  535. {
  536. int off;
  537. off = fdt_node_offset_by_compat_reg(blob, pci_compat,
  538. (phys_addr_t)ctrl_addr);
  539. if (off < 0)
  540. return;
  541. if (!is_serdes_configured(dev))
  542. fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
  543. }
  544. void ft_pci_setup(void *blob, bd_t *bd)
  545. {
  546. #ifdef CONFIG_PCIE1
  547. ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE1_ADDR, PCIE1);
  548. #endif
  549. #ifdef CONFIG_PCIE2
  550. ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE2_ADDR, PCIE2);
  551. #endif
  552. #ifdef CONFIG_PCIE3
  553. ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE3_ADDR, PCIE3);
  554. #endif
  555. #ifdef CONFIG_PCIE4
  556. ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE4_ADDR, PCIE4);
  557. #endif
  558. }
  559. #else
  560. void ft_pci_setup(void *blob, bd_t *bd)
  561. {
  562. }
  563. #endif
  564. #ifdef CONFIG_LS2080A
  565. void pcie_set_available_streamids(void *blob, const char *pcie_path,
  566. u32 *stream_ids, int count)
  567. {
  568. int nodeoffset;
  569. int i;
  570. nodeoffset = fdt_path_offset(blob, pcie_path);
  571. if (nodeoffset < 0) {
  572. printf("\n%s: ERROR: unable to update PCIe node\n", __func__);
  573. return;
  574. }
  575. /* for each stream ID, append to mmu-masters */
  576. for (i = 0; i < count; i++) {
  577. fdt_appendprop_u32(blob, nodeoffset, "available-stream-ids",
  578. stream_ids[i]);
  579. }
  580. }
  581. #define MAX_STREAM_IDS 4
  582. void fdt_fixup_smmu_pcie(void *blob)
  583. {
  584. int count;
  585. u32 stream_ids[MAX_STREAM_IDS];
  586. u32 ctlr_streamid = 0x300;
  587. #ifdef CONFIG_PCIE1
  588. /* PEX1 stream ID fixup */
  589. count = FSL_PEX1_STREAM_ID_END - FSL_PEX1_STREAM_ID_START + 1;
  590. alloc_stream_ids(FSL_PEX1_STREAM_ID_START, count, stream_ids,
  591. MAX_STREAM_IDS);
  592. pcie_set_available_streamids(blob, "/pcie@3400000", stream_ids, count);
  593. append_mmu_masters(blob, "/iommu@5000000", "/pcie@3400000",
  594. &ctlr_streamid, 1);
  595. #endif
  596. #ifdef CONFIG_PCIE2
  597. /* PEX2 stream ID fixup */
  598. count = FSL_PEX2_STREAM_ID_END - FSL_PEX2_STREAM_ID_START + 1;
  599. alloc_stream_ids(FSL_PEX2_STREAM_ID_START, count, stream_ids,
  600. MAX_STREAM_IDS);
  601. pcie_set_available_streamids(blob, "/pcie@3500000", stream_ids, count);
  602. append_mmu_masters(blob, "/iommu@5000000", "/pcie@3500000",
  603. &ctlr_streamid, 1);
  604. #endif
  605. #ifdef CONFIG_PCIE3
  606. /* PEX3 stream ID fixup */
  607. count = FSL_PEX3_STREAM_ID_END - FSL_PEX3_STREAM_ID_START + 1;
  608. alloc_stream_ids(FSL_PEX3_STREAM_ID_START, count, stream_ids,
  609. MAX_STREAM_IDS);
  610. pcie_set_available_streamids(blob, "/pcie@3600000", stream_ids, count);
  611. append_mmu_masters(blob, "/iommu@5000000", "/pcie@3600000",
  612. &ctlr_streamid, 1);
  613. #endif
  614. #ifdef CONFIG_PCIE4
  615. /* PEX4 stream ID fixup */
  616. count = FSL_PEX4_STREAM_ID_END - FSL_PEX4_STREAM_ID_START + 1;
  617. alloc_stream_ids(FSL_PEX4_STREAM_ID_START, count, stream_ids,
  618. MAX_STREAM_IDS);
  619. pcie_set_available_streamids(blob, "/pcie@3700000", stream_ids, count);
  620. append_mmu_masters(blob, "/iommu@5000000", "/pcie@3700000",
  621. &ctlr_streamid, 1);
  622. #endif
  623. }
  624. #endif