eth.c 19 KB

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  1. /*
  2. * Copyright 2015 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <netdev.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/fsl_serdes.h>
  10. #include <hwconfig.h>
  11. #include <fsl_mdio.h>
  12. #include <malloc.h>
  13. #include <fm_eth.h>
  14. #include <i2c.h>
  15. #include <miiphy.h>
  16. #include <fsl-mc/ldpaa_wriop.h>
  17. #include "../common/qixis.h"
  18. #include "ls2080aqds_qixis.h"
  19. #ifdef CONFIG_FSL_MC_ENET
  20. /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks.
  21. * Bank 1 -> Lanes A, B, C, D, E, F, G, H
  22. * Bank 2 -> Lanes A,B, C, D, E, F, G, H
  23. */
  24. /* Mapping of 16 SERDES lanes to LS2080A QDS board slots. A value of '0' here
  25. * means that the mapping must be determined dynamically, or that the lane
  26. * maps to something other than a board slot.
  27. */
  28. static u8 lane_to_slot_fsm1[] = {
  29. 0, 0, 0, 0, 0, 0, 0, 0
  30. };
  31. static u8 lane_to_slot_fsm2[] = {
  32. 0, 0, 0, 0, 0, 0, 0, 0
  33. };
  34. /* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
  35. * housed.
  36. */
  37. static int xqsgii_riser_phy_addr[] = {
  38. XQSGMII_CARD_PHY1_PORT0_ADDR,
  39. XQSGMII_CARD_PHY2_PORT0_ADDR,
  40. XQSGMII_CARD_PHY3_PORT0_ADDR,
  41. XQSGMII_CARD_PHY4_PORT0_ADDR,
  42. XQSGMII_CARD_PHY3_PORT2_ADDR,
  43. XQSGMII_CARD_PHY1_PORT2_ADDR,
  44. XQSGMII_CARD_PHY4_PORT2_ADDR,
  45. XQSGMII_CARD_PHY2_PORT2_ADDR,
  46. };
  47. static int sgmii_riser_phy_addr[] = {
  48. SGMII_CARD_PORT1_PHY_ADDR,
  49. SGMII_CARD_PORT2_PHY_ADDR,
  50. SGMII_CARD_PORT3_PHY_ADDR,
  51. SGMII_CARD_PORT4_PHY_ADDR,
  52. };
  53. /* Slot2 does not have EMI connections */
  54. #define EMI_NONE 0xFFFFFFFF
  55. #define EMI1_SLOT1 0
  56. #define EMI1_SLOT2 1
  57. #define EMI1_SLOT3 2
  58. #define EMI1_SLOT4 3
  59. #define EMI1_SLOT5 4
  60. #define EMI1_SLOT6 5
  61. #define EMI2 6
  62. #define SFP_TX 0
  63. static const char * const mdio_names[] = {
  64. "LS2080A_QDS_MDIO0",
  65. "LS2080A_QDS_MDIO1",
  66. "LS2080A_QDS_MDIO2",
  67. "LS2080A_QDS_MDIO3",
  68. "LS2080A_QDS_MDIO4",
  69. "LS2080A_QDS_MDIO5",
  70. DEFAULT_WRIOP_MDIO2_NAME,
  71. };
  72. struct ls2080a_qds_mdio {
  73. u8 muxval;
  74. struct mii_dev *realbus;
  75. };
  76. static void sgmii_configure_repeater(int serdes_port)
  77. {
  78. struct mii_dev *bus;
  79. uint8_t a = 0xf;
  80. int i, j, ret;
  81. int dpmac_id = 0, dpmac, mii_bus = 0;
  82. unsigned short value;
  83. char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"};
  84. uint8_t i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5f, 0x60};
  85. uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
  86. uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
  87. uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
  88. uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
  89. int *riser_phy_addr = &xqsgii_riser_phy_addr[0];
  90. /* Set I2c to Slot 1 */
  91. i2c_write(0x77, 0, 0, &a, 1);
  92. for (dpmac = 0; dpmac < 8; dpmac++) {
  93. /* Check the PHY status */
  94. switch (serdes_port) {
  95. case 1:
  96. mii_bus = 0;
  97. dpmac_id = dpmac + 1;
  98. break;
  99. case 2:
  100. mii_bus = 1;
  101. dpmac_id = dpmac + 9;
  102. a = 0xb;
  103. i2c_write(0x76, 0, 0, &a, 1);
  104. break;
  105. }
  106. ret = miiphy_set_current_dev(dev[mii_bus]);
  107. if (ret > 0)
  108. goto error;
  109. bus = mdio_get_current_dev();
  110. debug("Reading from bus %s\n", bus->name);
  111. ret = miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f,
  112. 3);
  113. if (ret > 0)
  114. goto error;
  115. mdelay(10);
  116. ret = miiphy_read(dev[mii_bus], riser_phy_addr[dpmac], 0x11,
  117. &value);
  118. if (ret > 0)
  119. goto error;
  120. mdelay(10);
  121. if ((value & 0xfff) == 0x40f) {
  122. printf("DPMAC %d:PHY is ..... Configured\n", dpmac_id);
  123. continue;
  124. }
  125. for (i = 0; i < 4; i++) {
  126. for (j = 0; j < 4; j++) {
  127. a = 0x18;
  128. i2c_write(i2c_addr[dpmac], 6, 1, &a, 1);
  129. a = 0x38;
  130. i2c_write(i2c_addr[dpmac], 4, 1, &a, 1);
  131. a = 0x4;
  132. i2c_write(i2c_addr[dpmac], 8, 1, &a, 1);
  133. i2c_write(i2c_addr[dpmac], 0xf, 1,
  134. &ch_a_eq[i], 1);
  135. i2c_write(i2c_addr[dpmac], 0x11, 1,
  136. &ch_a_ctl2[j], 1);
  137. i2c_write(i2c_addr[dpmac], 0x16, 1,
  138. &ch_b_eq[i], 1);
  139. i2c_write(i2c_addr[dpmac], 0x18, 1,
  140. &ch_b_ctl2[j], 1);
  141. a = 0x14;
  142. i2c_write(i2c_addr[dpmac], 0x23, 1, &a, 1);
  143. a = 0xb5;
  144. i2c_write(i2c_addr[dpmac], 0x2d, 1, &a, 1);
  145. a = 0x20;
  146. i2c_write(i2c_addr[dpmac], 4, 1, &a, 1);
  147. mdelay(100);
  148. ret = miiphy_read(dev[mii_bus],
  149. riser_phy_addr[dpmac],
  150. 0x11, &value);
  151. if (ret > 0)
  152. goto error;
  153. mdelay(1);
  154. ret = miiphy_read(dev[mii_bus],
  155. riser_phy_addr[dpmac],
  156. 0x11, &value);
  157. if (ret > 0)
  158. goto error;
  159. mdelay(10);
  160. if ((value & 0xfff) == 0x40f) {
  161. printf("DPMAC %d :PHY is configured ",
  162. dpmac_id);
  163. printf("after setting repeater 0x%x\n",
  164. value);
  165. i = 5;
  166. j = 5;
  167. } else
  168. printf("DPMAC %d :PHY is failed to ",
  169. dpmac_id);
  170. printf("configure the repeater 0x%x\n",
  171. value);
  172. }
  173. }
  174. }
  175. error:
  176. if (ret)
  177. printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac_id);
  178. return;
  179. }
  180. static void qsgmii_configure_repeater(int dpmac)
  181. {
  182. uint8_t a = 0xf;
  183. int i, j;
  184. int i2c_phy_addr = 0;
  185. int phy_addr = 0;
  186. int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
  187. uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
  188. uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
  189. uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
  190. uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
  191. const char *dev = "LS2080A_QDS_MDIO0";
  192. int ret = 0;
  193. unsigned short value;
  194. /* Set I2c to Slot 1 */
  195. i2c_write(0x77, 0, 0, &a, 1);
  196. switch (dpmac) {
  197. case 1:
  198. case 2:
  199. case 3:
  200. case 4:
  201. i2c_phy_addr = i2c_addr[0];
  202. phy_addr = 0;
  203. break;
  204. case 5:
  205. case 6:
  206. case 7:
  207. case 8:
  208. i2c_phy_addr = i2c_addr[1];
  209. phy_addr = 4;
  210. break;
  211. case 9:
  212. case 10:
  213. case 11:
  214. case 12:
  215. i2c_phy_addr = i2c_addr[2];
  216. phy_addr = 8;
  217. break;
  218. case 13:
  219. case 14:
  220. case 15:
  221. case 16:
  222. i2c_phy_addr = i2c_addr[3];
  223. phy_addr = 0xc;
  224. break;
  225. }
  226. /* Check the PHY status */
  227. ret = miiphy_set_current_dev(dev);
  228. ret = miiphy_write(dev, phy_addr, 0x1f, 3);
  229. mdelay(10);
  230. ret = miiphy_read(dev, phy_addr, 0x11, &value);
  231. mdelay(10);
  232. ret = miiphy_read(dev, phy_addr, 0x11, &value);
  233. mdelay(10);
  234. if ((value & 0xf) == 0xf) {
  235. printf("DPMAC %d :PHY is ..... Configured\n", dpmac);
  236. return;
  237. }
  238. for (i = 0; i < 4; i++) {
  239. for (j = 0; j < 4; j++) {
  240. a = 0x18;
  241. i2c_write(i2c_phy_addr, 6, 1, &a, 1);
  242. a = 0x38;
  243. i2c_write(i2c_phy_addr, 4, 1, &a, 1);
  244. a = 0x4;
  245. i2c_write(i2c_phy_addr, 8, 1, &a, 1);
  246. i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1);
  247. i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1);
  248. i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1);
  249. i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1);
  250. a = 0x14;
  251. i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
  252. a = 0xb5;
  253. i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
  254. a = 0x20;
  255. i2c_write(i2c_phy_addr, 4, 1, &a, 1);
  256. mdelay(100);
  257. ret = miiphy_read(dev, phy_addr, 0x11, &value);
  258. if (ret > 0)
  259. goto error;
  260. mdelay(1);
  261. ret = miiphy_read(dev, phy_addr, 0x11, &value);
  262. if (ret > 0)
  263. goto error;
  264. mdelay(10);
  265. if ((value & 0xf) == 0xf) {
  266. printf("DPMAC %d :PHY is ..... Configured\n",
  267. dpmac);
  268. return;
  269. }
  270. }
  271. }
  272. error:
  273. printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac);
  274. return;
  275. }
  276. static const char *ls2080a_qds_mdio_name_for_muxval(u8 muxval)
  277. {
  278. return mdio_names[muxval];
  279. }
  280. struct mii_dev *mii_dev_for_muxval(u8 muxval)
  281. {
  282. struct mii_dev *bus;
  283. const char *name = ls2080a_qds_mdio_name_for_muxval(muxval);
  284. if (!name) {
  285. printf("No bus for muxval %x\n", muxval);
  286. return NULL;
  287. }
  288. bus = miiphy_get_dev_by_name(name);
  289. if (!bus) {
  290. printf("No bus by name %s\n", name);
  291. return NULL;
  292. }
  293. return bus;
  294. }
  295. static void ls2080a_qds_enable_SFP_TX(u8 muxval)
  296. {
  297. u8 brdcfg9;
  298. brdcfg9 = QIXIS_READ(brdcfg[9]);
  299. brdcfg9 &= ~BRDCFG9_SFPTX_MASK;
  300. brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT);
  301. QIXIS_WRITE(brdcfg[9], brdcfg9);
  302. }
  303. static void ls2080a_qds_mux_mdio(u8 muxval)
  304. {
  305. u8 brdcfg4;
  306. if (muxval <= 5) {
  307. brdcfg4 = QIXIS_READ(brdcfg[4]);
  308. brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
  309. brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
  310. QIXIS_WRITE(brdcfg[4], brdcfg4);
  311. }
  312. }
  313. static int ls2080a_qds_mdio_read(struct mii_dev *bus, int addr,
  314. int devad, int regnum)
  315. {
  316. struct ls2080a_qds_mdio *priv = bus->priv;
  317. ls2080a_qds_mux_mdio(priv->muxval);
  318. return priv->realbus->read(priv->realbus, addr, devad, regnum);
  319. }
  320. static int ls2080a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
  321. int regnum, u16 value)
  322. {
  323. struct ls2080a_qds_mdio *priv = bus->priv;
  324. ls2080a_qds_mux_mdio(priv->muxval);
  325. return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
  326. }
  327. static int ls2080a_qds_mdio_reset(struct mii_dev *bus)
  328. {
  329. struct ls2080a_qds_mdio *priv = bus->priv;
  330. return priv->realbus->reset(priv->realbus);
  331. }
  332. static int ls2080a_qds_mdio_init(char *realbusname, u8 muxval)
  333. {
  334. struct ls2080a_qds_mdio *pmdio;
  335. struct mii_dev *bus = mdio_alloc();
  336. if (!bus) {
  337. printf("Failed to allocate ls2080a_qds MDIO bus\n");
  338. return -1;
  339. }
  340. pmdio = malloc(sizeof(*pmdio));
  341. if (!pmdio) {
  342. printf("Failed to allocate ls2080a_qds private data\n");
  343. free(bus);
  344. return -1;
  345. }
  346. bus->read = ls2080a_qds_mdio_read;
  347. bus->write = ls2080a_qds_mdio_write;
  348. bus->reset = ls2080a_qds_mdio_reset;
  349. sprintf(bus->name, ls2080a_qds_mdio_name_for_muxval(muxval));
  350. pmdio->realbus = miiphy_get_dev_by_name(realbusname);
  351. if (!pmdio->realbus) {
  352. printf("No bus with name %s\n", realbusname);
  353. free(bus);
  354. free(pmdio);
  355. return -1;
  356. }
  357. pmdio->muxval = muxval;
  358. bus->priv = pmdio;
  359. return mdio_register(bus);
  360. }
  361. /*
  362. * Initialize the dpmac_info array.
  363. *
  364. */
  365. static void initialize_dpmac_to_slot(void)
  366. {
  367. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  368. int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
  369. FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
  370. >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
  371. int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
  372. FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
  373. >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
  374. char *env_hwconfig;
  375. env_hwconfig = getenv("hwconfig");
  376. switch (serdes1_prtcl) {
  377. case 0x07:
  378. case 0x09:
  379. case 0x33:
  380. printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
  381. serdes1_prtcl);
  382. lane_to_slot_fsm1[0] = EMI1_SLOT1;
  383. lane_to_slot_fsm1[1] = EMI1_SLOT1;
  384. lane_to_slot_fsm1[2] = EMI1_SLOT1;
  385. lane_to_slot_fsm1[3] = EMI1_SLOT1;
  386. if (hwconfig_f("xqsgmii", env_hwconfig)) {
  387. lane_to_slot_fsm1[4] = EMI1_SLOT1;
  388. lane_to_slot_fsm1[5] = EMI1_SLOT1;
  389. lane_to_slot_fsm1[6] = EMI1_SLOT1;
  390. lane_to_slot_fsm1[7] = EMI1_SLOT1;
  391. } else {
  392. lane_to_slot_fsm1[4] = EMI1_SLOT2;
  393. lane_to_slot_fsm1[5] = EMI1_SLOT2;
  394. lane_to_slot_fsm1[6] = EMI1_SLOT2;
  395. lane_to_slot_fsm1[7] = EMI1_SLOT2;
  396. }
  397. break;
  398. case 0x2A:
  399. printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
  400. serdes1_prtcl);
  401. break;
  402. default:
  403. printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
  404. __func__, serdes1_prtcl);
  405. break;
  406. }
  407. switch (serdes2_prtcl) {
  408. case 0x07:
  409. case 0x08:
  410. case 0x09:
  411. case 0x49:
  412. printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
  413. serdes2_prtcl);
  414. lane_to_slot_fsm2[0] = EMI1_SLOT4;
  415. lane_to_slot_fsm2[1] = EMI1_SLOT4;
  416. lane_to_slot_fsm2[2] = EMI1_SLOT4;
  417. lane_to_slot_fsm2[3] = EMI1_SLOT4;
  418. if (hwconfig_f("xqsgmii", env_hwconfig)) {
  419. lane_to_slot_fsm2[4] = EMI1_SLOT4;
  420. lane_to_slot_fsm2[5] = EMI1_SLOT4;
  421. lane_to_slot_fsm2[6] = EMI1_SLOT4;
  422. lane_to_slot_fsm2[7] = EMI1_SLOT4;
  423. } else {
  424. /* No MDIO physical connection */
  425. lane_to_slot_fsm2[4] = EMI1_SLOT6;
  426. lane_to_slot_fsm2[5] = EMI1_SLOT6;
  427. lane_to_slot_fsm2[6] = EMI1_SLOT6;
  428. lane_to_slot_fsm2[7] = EMI1_SLOT6;
  429. }
  430. break;
  431. default:
  432. printf(" %s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
  433. __func__ , serdes2_prtcl);
  434. break;
  435. }
  436. }
  437. void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
  438. {
  439. int lane, slot;
  440. struct mii_dev *bus;
  441. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  442. int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
  443. FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
  444. >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
  445. int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
  446. FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
  447. >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
  448. int *riser_phy_addr;
  449. char *env_hwconfig = getenv("hwconfig");
  450. if (hwconfig_f("xqsgmii", env_hwconfig))
  451. riser_phy_addr = &xqsgii_riser_phy_addr[0];
  452. else
  453. riser_phy_addr = &sgmii_riser_phy_addr[0];
  454. if (dpmac_id > WRIOP1_DPMAC9)
  455. goto serdes2;
  456. switch (serdes1_prtcl) {
  457. case 0x07:
  458. lane = serdes_get_first_lane(FSL_SRDS_1, SGMII1 + dpmac_id);
  459. slot = lane_to_slot_fsm1[lane];
  460. switch (++slot) {
  461. case 1:
  462. /* Slot housing a SGMII riser card? */
  463. wriop_set_phy_address(dpmac_id,
  464. riser_phy_addr[dpmac_id - 1]);
  465. dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
  466. bus = mii_dev_for_muxval(EMI1_SLOT1);
  467. wriop_set_mdio(dpmac_id, bus);
  468. dpmac_info[dpmac_id].phydev = phy_connect(
  469. dpmac_info[dpmac_id].bus,
  470. dpmac_info[dpmac_id].phy_addr,
  471. NULL,
  472. dpmac_info[dpmac_id].enet_if);
  473. phy_config(dpmac_info[dpmac_id].phydev);
  474. break;
  475. case 2:
  476. /* Slot housing a SGMII riser card? */
  477. wriop_set_phy_address(dpmac_id,
  478. riser_phy_addr[dpmac_id - 1]);
  479. dpmac_info[dpmac_id].board_mux = EMI1_SLOT2;
  480. bus = mii_dev_for_muxval(EMI1_SLOT2);
  481. wriop_set_mdio(dpmac_id, bus);
  482. dpmac_info[dpmac_id].phydev = phy_connect(
  483. dpmac_info[dpmac_id].bus,
  484. dpmac_info[dpmac_id].phy_addr,
  485. NULL,
  486. dpmac_info[dpmac_id].enet_if);
  487. phy_config(dpmac_info[dpmac_id].phydev);
  488. break;
  489. case 3:
  490. break;
  491. case 4:
  492. break;
  493. case 5:
  494. break;
  495. case 6:
  496. break;
  497. }
  498. break;
  499. default:
  500. printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
  501. __func__ , serdes1_prtcl);
  502. break;
  503. }
  504. serdes2:
  505. switch (serdes2_prtcl) {
  506. case 0x07:
  507. case 0x08:
  508. case 0x49:
  509. lane = serdes_get_first_lane(FSL_SRDS_2, SGMII9 +
  510. (dpmac_id - 9));
  511. slot = lane_to_slot_fsm2[lane];
  512. switch (++slot) {
  513. case 1:
  514. break;
  515. case 3:
  516. break;
  517. case 4:
  518. /* Slot housing a SGMII riser card? */
  519. wriop_set_phy_address(dpmac_id,
  520. riser_phy_addr[dpmac_id - 9]);
  521. dpmac_info[dpmac_id].board_mux = EMI1_SLOT4;
  522. bus = mii_dev_for_muxval(EMI1_SLOT4);
  523. wriop_set_mdio(dpmac_id, bus);
  524. dpmac_info[dpmac_id].phydev = phy_connect(
  525. dpmac_info[dpmac_id].bus,
  526. dpmac_info[dpmac_id].phy_addr,
  527. NULL,
  528. dpmac_info[dpmac_id].enet_if);
  529. phy_config(dpmac_info[dpmac_id].phydev);
  530. break;
  531. case 5:
  532. break;
  533. case 6:
  534. /* Slot housing a SGMII riser card? */
  535. wriop_set_phy_address(dpmac_id,
  536. riser_phy_addr[dpmac_id - 13]);
  537. dpmac_info[dpmac_id].board_mux = EMI1_SLOT6;
  538. bus = mii_dev_for_muxval(EMI1_SLOT6);
  539. wriop_set_mdio(dpmac_id, bus);
  540. break;
  541. }
  542. break;
  543. default:
  544. printf("%s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
  545. __func__, serdes2_prtcl);
  546. break;
  547. }
  548. }
  549. void ls2080a_handle_phy_interface_qsgmii(int dpmac_id)
  550. {
  551. int lane = 0, slot;
  552. struct mii_dev *bus;
  553. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  554. int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
  555. FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
  556. >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
  557. switch (serdes1_prtcl) {
  558. case 0x33:
  559. switch (dpmac_id) {
  560. case 1:
  561. case 2:
  562. case 3:
  563. case 4:
  564. lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_A);
  565. break;
  566. case 5:
  567. case 6:
  568. case 7:
  569. case 8:
  570. lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_B);
  571. break;
  572. case 9:
  573. case 10:
  574. case 11:
  575. case 12:
  576. lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_C);
  577. break;
  578. case 13:
  579. case 14:
  580. case 15:
  581. case 16:
  582. lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_D);
  583. break;
  584. }
  585. slot = lane_to_slot_fsm1[lane];
  586. switch (++slot) {
  587. case 1:
  588. /* Slot housing a QSGMII riser card? */
  589. wriop_set_phy_address(dpmac_id, dpmac_id - 1);
  590. dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
  591. bus = mii_dev_for_muxval(EMI1_SLOT1);
  592. wriop_set_mdio(dpmac_id, bus);
  593. dpmac_info[dpmac_id].phydev = phy_connect(
  594. dpmac_info[dpmac_id].bus,
  595. dpmac_info[dpmac_id].phy_addr,
  596. NULL,
  597. dpmac_info[dpmac_id].enet_if);
  598. phy_config(dpmac_info[dpmac_id].phydev);
  599. break;
  600. case 3:
  601. break;
  602. case 4:
  603. break;
  604. case 5:
  605. break;
  606. case 6:
  607. break;
  608. }
  609. break;
  610. default:
  611. printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
  612. serdes1_prtcl);
  613. break;
  614. }
  615. qsgmii_configure_repeater(dpmac_id);
  616. }
  617. void ls2080a_handle_phy_interface_xsgmii(int i)
  618. {
  619. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  620. int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
  621. FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
  622. >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
  623. switch (serdes1_prtcl) {
  624. case 0x2A:
  625. /*
  626. * XFI does not need a PHY to work, but to avoid U-boot use
  627. * default PHY address which is zero to a MAC when it found
  628. * a MAC has no PHY address, we give a PHY address to XFI
  629. * MAC, and should not use a real XAUI PHY address, since
  630. * MDIO can access it successfully, and then MDIO thinks
  631. * the XAUI card is used for the XFI MAC, which will cause
  632. * error.
  633. */
  634. wriop_set_phy_address(i, i + 4);
  635. ls2080a_qds_enable_SFP_TX(SFP_TX);
  636. break;
  637. default:
  638. printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
  639. serdes1_prtcl);
  640. break;
  641. }
  642. }
  643. #endif
  644. int board_eth_init(bd_t *bis)
  645. {
  646. int error;
  647. #ifdef CONFIG_FSL_MC_ENET
  648. struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
  649. int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
  650. FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
  651. >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
  652. int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
  653. FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
  654. >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
  655. struct memac_mdio_info *memac_mdio0_info;
  656. struct memac_mdio_info *memac_mdio1_info;
  657. unsigned int i;
  658. char *env_hwconfig;
  659. env_hwconfig = getenv("hwconfig");
  660. initialize_dpmac_to_slot();
  661. memac_mdio0_info = (struct memac_mdio_info *)malloc(
  662. sizeof(struct memac_mdio_info));
  663. memac_mdio0_info->regs =
  664. (struct memac_mdio_controller *)
  665. CONFIG_SYS_FSL_WRIOP1_MDIO1;
  666. memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
  667. /* Register the real MDIO1 bus */
  668. fm_memac_mdio_init(bis, memac_mdio0_info);
  669. memac_mdio1_info = (struct memac_mdio_info *)malloc(
  670. sizeof(struct memac_mdio_info));
  671. memac_mdio1_info->regs =
  672. (struct memac_mdio_controller *)
  673. CONFIG_SYS_FSL_WRIOP1_MDIO2;
  674. memac_mdio1_info->name = DEFAULT_WRIOP_MDIO2_NAME;
  675. /* Register the real MDIO2 bus */
  676. fm_memac_mdio_init(bis, memac_mdio1_info);
  677. /* Register the muxing front-ends to the MDIO buses */
  678. ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
  679. ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2);
  680. ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3);
  681. ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4);
  682. ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5);
  683. ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6);
  684. ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2);
  685. for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
  686. switch (wriop_get_enet_if(i)) {
  687. case PHY_INTERFACE_MODE_QSGMII:
  688. ls2080a_handle_phy_interface_qsgmii(i);
  689. break;
  690. case PHY_INTERFACE_MODE_SGMII:
  691. ls2080a_handle_phy_interface_sgmii(i);
  692. break;
  693. case PHY_INTERFACE_MODE_XGMII:
  694. ls2080a_handle_phy_interface_xsgmii(i);
  695. break;
  696. default:
  697. break;
  698. if (i == 16)
  699. i = NUM_WRIOP_PORTS;
  700. }
  701. }
  702. error = cpu_eth_init(bis);
  703. if (hwconfig_f("xqsgmii", env_hwconfig)) {
  704. if (serdes1_prtcl == 0x7)
  705. sgmii_configure_repeater(1);
  706. if (serdes2_prtcl == 0x7 || serdes2_prtcl == 0x8 ||
  707. serdes2_prtcl == 0x49)
  708. sgmii_configure_repeater(2);
  709. }
  710. #endif
  711. error = pci_eth_init(bis);
  712. return error;
  713. }
  714. #ifdef CONFIG_FSL_MC_ENET
  715. #endif