README 8.1 KB

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  1. Overview
  2. --------
  3. The LS2080A Development System (QDS) is a high-performance computing,
  4. evaluation, and development platform that supports the QorIQ LS2080A
  5. Layerscape Architecture processor. The LS2080AQDS provides validation and
  6. SW development platform for the Freescale LS2080A processor series, with
  7. a complete debugging environment.
  8. LS2080A SoC Overview
  9. ------------------
  10. The LS2080A integrated multicore processor combines eight ARM Cortex-A57
  11. processor cores with high-performance data path acceleration logic and network
  12. and peripheral bus interfaces required for networking, telecom/datacom,
  13. wireless infrastructure, and mil/aerospace applications.
  14. The LS2080A SoC includes the following function and features:
  15. - Eight 64-bit ARM Cortex-A57 CPUs
  16. - 1 MB platform cache with ECC
  17. - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
  18. - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
  19. the AIOP
  20. - Data path acceleration architecture (DPAA2) incorporating acceleration for
  21. the following functions:
  22. - Packet parsing, classification, and distribution (WRIOP)
  23. - Queue and Hardware buffer management for scheduling, packet sequencing, and
  24. congestion management, buffer allocation and de-allocation (QBMan)
  25. - Cryptography acceleration (SEC) at up to 10 Gbps
  26. - RegEx pattern matching acceleration (PME) at up to 10 Gbps
  27. - Decompression/compression acceleration (DCE) at up to 20 Gbps
  28. - Accelerated I/O processing (AIOP) at up to 20 Gbps
  29. - QDMA engine
  30. - 16 SerDes lanes at up to 10.3125 GHz
  31. - Ethernet interfaces
  32. - Up to eight 10 Gbps Ethernet MACs
  33. - Up to eight 1 / 2.5 Gbps Ethernet MACs
  34. - High-speed peripheral interfaces
  35. - Four PCIe 3.0 controllers, one supporting SR-IOV
  36. - Additional peripheral interfaces
  37. - Two serial ATA (SATA 3.0) controllers
  38. - Two high-speed USB 3.0 controllers with integrated PHY
  39. - Enhanced secure digital host controller (eSDXC/eMMC)
  40. - Serial peripheral interface (SPI) controller
  41. - Quad Serial Peripheral Interface (QSPI) Controller
  42. - Four I2C controllers
  43. - Two DUARTs
  44. - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
  45. - Support for hardware virtualization and partitioning enforcement
  46. - QorIQ platform's trust architecture 3.0
  47. - Service processor (SP) provides pre-boot initialization and secure-boot
  48. capabilities
  49. LS2080AQDS board Overview
  50. -----------------------
  51. - SERDES Connections, 16 lanes supporting:
  52. - PCI Express - 3.0
  53. - SGMII, SGMII 2.5
  54. - QSGMII
  55. - SATA 3.0
  56. - XAUI
  57. - XFI
  58. - DDR Controller
  59. - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
  60. chip-selects and two DIMM connectors. Support is up to 2133MT/s.
  61. - One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects
  62. and two DIMM connectors. Support is up to 1600MT/s.
  63. -IFC/Local Bus
  64. - IFC rev. 2.0 implementation supporting Little Endian connection scheme.
  65. - One in-socket 128 MB NOR flash 16-bit data bus
  66. - One 512 MB NAND flash with ECC support
  67. - IFC Test Port
  68. - PromJet Port
  69. - FPGA connection
  70. - USB 3.0
  71. - Two high speed USB 3.0 ports
  72. - First USB 3.0 port configured as Host with Type-A connector
  73. - Second USB 3.0 port configured as OTG with micro-AB connector
  74. - SDHC: PCIe x1 Right Angle connector for supporting following cards
  75. - 1/4-/8-bit SD/MMC Legacy CARD supporting 3.3V devices only
  76. - 1-/4-/8-bit SD/MMC Card supporting 1.8V devices only
  77. - 4-bit eMMC Card Rev 4.4 (1.8V only)
  78. - 8-bit eMMC Card Rev 4.5 (1.8V only)
  79. - SD Card Rev 2.0 and Rev 3.0
  80. - DSPI: 3 high-speed flash Memory for storage
  81. - 16 MB high-speed flash Memory for boot code and storage (up to 108MHz)
  82. - 8 MB high-speed flash Memory (up to 104 MHz)
  83. - 512 MB low-speed flash Memory (up to 40 MHz)
  84. - QSPI: via NAND/QSPI Card
  85. - 4 I2C controllers
  86. - Two SATA onboard connectors
  87. - UART
  88. - Two 4-pin (HW control) or four 2-pin (SW control) serial ports at up to 115.2 Kbit/s
  89. - Two DB9 D-Type connectors supporting one Serial port each
  90. - ARM JTAG support
  91. Memory map from core's view
  92. ----------------------------
  93. 0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom
  94. 0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR
  95. 0x00_1800_0000 .. 0x00_181F_FFFF OCRAM
  96. 0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1
  97. 0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1
  98. 0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2
  99. 0x80_8000_0000 .. 0xFF_FFFF_FFFF DDR region #2
  100. Other addresses are either reserved, or not used directly by u-boot.
  101. This list should be updated when more addresses are used.
  102. IFC region map from core's view
  103. -------------------------------
  104. During boot i.e. IFC Region #1:-
  105. 0x30000000 - 0x37ffffff : 128MB : NOR flash
  106. 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
  107. 0x3C000000 - 0x40000000 : 64MB : FPGA etc
  108. After relocate to DDR i.e. IFC Region #2:-
  109. 0x5_1000_0000..0x5_1fff_ffff Memory Hole
  110. 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
  111. 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
  112. 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
  113. 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
  114. Booting Options
  115. ---------------
  116. a) Promjet Boot
  117. b) NOR boot
  118. c) NAND boot
  119. d) SD boot
  120. e) QSPI boot
  121. Environment Variables
  122. ---------------------
  123. - mcboottimeout: MC boot timeout in milliseconds. If this variable is not defined
  124. the value CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS will be assumed.
  125. - mcmemsize: MC DRAM block size. If this variable is not defined
  126. the value CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE will be assumed.
  127. Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
  128. -------------------------------------------------------------------
  129. One needs to use appropriate bootargs to boot Linux flavors which do
  130. not support 48-bit VA (for e.g. < Linux 3.18) by appending mem=2048M, as shown
  131. below:
  132. => setenv bootargs 'console=ttyS1,115200 root=/dev/ram
  133. earlycon=uart8250,mmio,0x21c0600,115200 default_hugepagesz=2m hugepagesz=2m
  134. hugepages=16 mem=2048M'
  135. X-QSGMII-16PORT riser card
  136. ----------------------------
  137. The X-QSGMII-16PORT is a 4xQSGMII/8xSGMII riser card with eighth SerDes
  138. interfaces implemented in PCIe form factor board.
  139. It supports followings
  140. - Card can operate with up to 4 QSGMII lane simultaneously
  141. - Card can operate with up to 8 SGMII lane simultaneously
  142. Supported card configuration
  143. - CSEL : ON ON ON ON
  144. - MSEL1 : ON ON ON ON OFF OFF OFF OFF
  145. - MSEL2 : OFF OFF OFF OFF ON ON ON ON
  146. To enable this card: modify hwconfig to add "xqsgmii" variable.
  147. Supported PHY addresses during SGMII:
  148. #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
  149. #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
  150. #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
  151. #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
  152. #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
  153. #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
  154. #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
  155. #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
  156. Mapping DPMACx to PHY during QSGMII
  157. DPMAC1 -> PHY1-P0
  158. DPMAC2 -> PHY2-P0
  159. DPMAC3 -> PHY3-P0
  160. DPMAC4 -> PHY4-P0
  161. DPMAC5 -> PHY3-P2
  162. DPMAC6 -> PHY1-P2
  163. DPMAC7 -> PHY4-P1
  164. DPMAC8 -> PHY2-P2
  165. DPMAC9 -> PHY1-P0
  166. DPMAC10 -> PHY2-P0
  167. DPMAC11 -> PHY3-P0
  168. DPMAC12 -> PHY4-P0
  169. DPMAC13 -> PHY3-P2
  170. DPMAC14 -> PHY1-P2
  171. DPMAC15 -> PHY4-P1
  172. DPMAC16 -> PHY2-P2
  173. Supported PHY address during QSGMII
  174. #define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
  175. #define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
  176. #define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
  177. #define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
  178. #define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
  179. #define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
  180. #define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
  181. #define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
  182. #define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
  183. #define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
  184. #define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
  185. #define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
  186. #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
  187. #define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
  188. #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
  189. #define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
  190. Mapping DPMACx to PHY during QSGMII
  191. DPMAC1 -> PHY1-P3
  192. DPMAC2 -> PHY1-P2
  193. DPMAC3 -> PHY1-P1
  194. DPMAC4 -> PHY1-P0
  195. DPMAC5 -> PHY2-P3
  196. DPMAC6 -> PHY2-P2
  197. DPMAC7 -> PHY2-P1
  198. DPMAC8 -> PHY2-P0
  199. DPMAC9 -> PHY3-P0
  200. DPMAC10 -> PHY3-P1
  201. DPMAC11 -> PHY3-P2
  202. DPMAC12 -> PHY3-P3
  203. DPMAC13 -> PHY4-P0
  204. DPMAC14 -> PHY4-P1
  205. DPMAC15 -> PHY4-P2
  206. DPMAC16 -> PHY4-P3