ddr.c 5.3 KB

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  1. /*
  2. * Copyright 2014 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <fsl_ddr_sdram.h>
  8. #include <fsl_ddr_dimm_params.h>
  9. #include "ddr.h"
  10. DECLARE_GLOBAL_DATA_PTR;
  11. void fsl_ddr_board_options(memctl_options_t *popts,
  12. dimm_params_t *pdimm,
  13. unsigned int ctrl_num)
  14. {
  15. const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  16. ulong ddr_freq;
  17. if (ctrl_num > 3) {
  18. printf("Not supported controller number %d\n", ctrl_num);
  19. return;
  20. }
  21. if (!pdimm->n_ranks)
  22. return;
  23. /*
  24. * we use identical timing for all slots. If needed, change the code
  25. * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
  26. */
  27. if (popts->registered_dimm_en)
  28. pbsp = rdimms[ctrl_num];
  29. else
  30. pbsp = udimms[ctrl_num];
  31. /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
  32. * freqency and n_banks specified in board_specific_parameters table.
  33. */
  34. ddr_freq = get_ddr_freq(0) / 1000000;
  35. while (pbsp->datarate_mhz_high) {
  36. if (pbsp->n_ranks == pdimm->n_ranks &&
  37. (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
  38. if (ddr_freq <= pbsp->datarate_mhz_high) {
  39. popts->clk_adjust = pbsp->clk_adjust;
  40. popts->wrlvl_start = pbsp->wrlvl_start;
  41. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  42. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  43. goto found;
  44. }
  45. pbsp_highest = pbsp;
  46. }
  47. pbsp++;
  48. }
  49. if (pbsp_highest) {
  50. printf("Error: board specific timing not found for data rate %lu MT/s\n"
  51. "Trying to use the highest speed (%u) parameters\n",
  52. ddr_freq, pbsp_highest->datarate_mhz_high);
  53. popts->clk_adjust = pbsp_highest->clk_adjust;
  54. popts->wrlvl_start = pbsp_highest->wrlvl_start;
  55. popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  56. popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  57. } else {
  58. panic("DIMM is not supported by this board");
  59. }
  60. found:
  61. debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
  62. "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
  63. pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
  64. pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
  65. pbsp->wrlvl_ctl_3);
  66. #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  67. if (ctrl_num == CONFIG_DP_DDR_CTRL) {
  68. /* force DDR bus width to 32 bits */
  69. popts->data_bus_width = 1;
  70. popts->otf_burst_chop_en = 0;
  71. popts->burst_length = DDR_BL8;
  72. popts->bstopre = 0; /* enable auto precharge */
  73. }
  74. #endif
  75. /*
  76. * Factors to consider for half-strength driver enable:
  77. * - number of DIMMs installed
  78. */
  79. popts->half_strength_driver_enable = 1;
  80. /*
  81. * Write leveling override
  82. */
  83. popts->wrlvl_override = 1;
  84. popts->wrlvl_sample = 0xf;
  85. /*
  86. * Rtt and Rtt_WR override
  87. */
  88. popts->rtt_override = 0;
  89. /* Enable ZQ calibration */
  90. popts->zq_en = 1;
  91. #ifdef CONFIG_SYS_FSL_DDR4
  92. popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
  93. popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
  94. DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
  95. #else
  96. /* DHC_EN =1, ODT = 75 Ohm */
  97. popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
  98. popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
  99. #endif
  100. }
  101. #ifdef CONFIG_SYS_DDR_RAW_TIMING
  102. dimm_params_t ddr_raw_timing = {
  103. .n_ranks = 2,
  104. .rank_density = 1073741824u,
  105. .capacity = 2147483648,
  106. .primary_sdram_width = 64,
  107. .ec_sdram_width = 0,
  108. .registered_dimm = 0,
  109. .mirrored_dimm = 0,
  110. .n_row_addr = 14,
  111. .n_col_addr = 10,
  112. .n_banks_per_sdram_device = 8,
  113. .edc_config = 0,
  114. .burst_lengths_bitmask = 0x0c,
  115. .tckmin_x_ps = 937,
  116. .caslat_x = 0x6FC << 4, /* 14,13,11,10,9,8,7,6 */
  117. .taa_ps = 13090,
  118. .twr_ps = 15000,
  119. .trcd_ps = 13090,
  120. .trrd_ps = 5000,
  121. .trp_ps = 13090,
  122. .tras_ps = 33000,
  123. .trc_ps = 46090,
  124. .trfc_ps = 160000,
  125. .twtr_ps = 7500,
  126. .trtp_ps = 7500,
  127. .refresh_rate_ps = 7800000,
  128. .tfaw_ps = 25000,
  129. };
  130. int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
  131. unsigned int controller_number,
  132. unsigned int dimm_number)
  133. {
  134. const char dimm_model[] = "Fixed DDR on board";
  135. if (((controller_number == 0) && (dimm_number == 0)) ||
  136. ((controller_number == 1) && (dimm_number == 0))) {
  137. memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
  138. memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
  139. memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
  140. }
  141. return 0;
  142. }
  143. #endif
  144. phys_size_t initdram(int board_type)
  145. {
  146. phys_size_t dram_size;
  147. puts("Initializing DDR....");
  148. puts("using SPD\n");
  149. dram_size = fsl_ddr_sdram();
  150. return dram_size;
  151. }
  152. void dram_init_banksize(void)
  153. {
  154. #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
  155. phys_size_t dp_ddr_size;
  156. #endif
  157. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  158. if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
  159. gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
  160. gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
  161. gd->bd->bi_dram[1].size = gd->ram_size -
  162. CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
  163. } else {
  164. gd->bd->bi_dram[0].size = gd->ram_size;
  165. }
  166. #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
  167. /* initialize DP-DDR here */
  168. puts("DP-DDR: ");
  169. /*
  170. * DDR controller use 0 as the base address for binding.
  171. * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
  172. */
  173. dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
  174. CONFIG_DP_DDR_CTRL,
  175. CONFIG_DP_DDR_NUM_CTRLS,
  176. CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
  177. NULL, NULL, NULL);
  178. if (dp_ddr_size) {
  179. gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
  180. gd->bd->bi_dram[2].size = dp_ddr_size;
  181. } else {
  182. puts("Not detected");
  183. }
  184. #endif
  185. }