ls2080a_stream_id.h 1.9 KB

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  1. /*
  2. * Copyright 2014 Freescale Semiconductor, Inc.
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. *
  6. */
  7. #ifndef __FSL_STREAM_ID_H
  8. #define __FSL_STREAM_ID_H
  9. /* Stream IDs on ls2080a devices are not hardwired and are
  10. * programmed by sw. There are a limited number of stream IDs
  11. * available, and the partitioning of them is scenario dependent.
  12. * This header defines the partitioning between legacy, PCI,
  13. * and DPAA2 devices.
  14. *
  15. * This partitiong can be customized in this file depending
  16. * on the specific hardware config-- e.g. perhaps not all
  17. * PEX controllers are in use.
  18. *
  19. * On LS2080 stream IDs are programmed in AMQ registers (32-bits) for
  20. * each of the different bus masters. The relationship between
  21. * the AMQ registers and stream IDs is defined in the table below:
  22. * AMQ bit streamID bit
  23. * ---------------------------
  24. * PL[18] 9
  25. * BMT[17] 8
  26. * VA[16] 7
  27. * [15] -
  28. * ICID[14:7] -
  29. * ICID[6:0] 6-0
  30. * ----------------------------
  31. */
  32. #define AMQ_PL_MASK (0x1 << 18) /* priviledge bit */
  33. #define AMQ_BMT_MASK (0x1 << 17) /* bypass bit */
  34. #define FSL_INVALID_STREAM_ID 0
  35. #define FSL_BYPASS_AMQ (AMQ_PL_MASK | AMQ_BMT_MASK)
  36. /* legacy devices */
  37. #define FSL_USB1_STREAM_ID 1
  38. #define FSL_USB2_STREAM_ID 2
  39. #define FSL_SDMMC_STREAM_ID 3
  40. #define FSL_SATA1_STREAM_ID 4
  41. #define FSL_SATA2_STREAM_ID 5
  42. #define FSL_DMA_STREAM_ID 6
  43. /* PCI - programmed in PEXn_LUT by OS */
  44. /* 4 IDs per controller */
  45. #define FSL_PEX1_STREAM_ID_START 7
  46. #define FSL_PEX1_STREAM_ID_END 10
  47. #define FSL_PEX2_STREAM_ID_START 11
  48. #define FSL_PEX2_STREAM_ID_END 14
  49. #define FSL_PEX3_STREAM_ID_START 15
  50. #define FSL_PEX3_STREAM_ID_END 18
  51. #define FSL_PEX4_STREAM_ID_START 19
  52. #define FSL_PEX4_STREAM_ID_END 22
  53. /* DPAA2 - set in MC DPC and alloced by MC */
  54. #define FSL_DPAA2_STREAM_ID_START 23
  55. #define FSL_DPAA2_STREAM_ID_END 63
  56. #endif