cpu.h 9.8 KB

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  1. /*
  2. * Copyright 2014-2015, Freescale Semiconductor
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #ifndef _FSL_LAYERSCAPE_CPU_H
  7. #define _FSL_LAYERSCAPE_CPU_H
  8. static struct cpu_type cpu_type_list[] = {
  9. CPU_TYPE_ENTRY(LS2080, LS2080, 8),
  10. CPU_TYPE_ENTRY(LS2085, LS2085, 8),
  11. CPU_TYPE_ENTRY(LS2045, LS2045, 4),
  12. CPU_TYPE_ENTRY(LS1043, LS1043, 4),
  13. };
  14. #ifndef CONFIG_SYS_DCACHE_OFF
  15. #define SECTION_SHIFT_L0 39UL
  16. #define SECTION_SHIFT_L1 30UL
  17. #define SECTION_SHIFT_L2 21UL
  18. #define BLOCK_SIZE_L0 0x8000000000
  19. #define BLOCK_SIZE_L1 0x40000000
  20. #define BLOCK_SIZE_L2 0x200000
  21. #define NUM_OF_ENTRY 512
  22. #define TCR_EL2_PS_40BIT (2 << 16)
  23. #define LAYERSCAPE_VA_BITS (40)
  24. #define LAYERSCAPE_TCR (TCR_TG0_4K | \
  25. TCR_EL2_PS_40BIT | \
  26. TCR_SHARED_NON | \
  27. TCR_ORGN_NC | \
  28. TCR_IRGN_NC | \
  29. TCR_T0SZ(LAYERSCAPE_VA_BITS))
  30. #define LAYERSCAPE_TCR_FINAL (TCR_TG0_4K | \
  31. TCR_EL2_PS_40BIT | \
  32. TCR_SHARED_OUTER | \
  33. TCR_ORGN_WBWA | \
  34. TCR_IRGN_WBWA | \
  35. TCR_T0SZ(LAYERSCAPE_VA_BITS))
  36. #ifdef CONFIG_FSL_LSCH3
  37. #define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
  38. #define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
  39. #define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000
  40. #define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
  41. #define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
  42. #define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000
  43. #define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000
  44. #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
  45. #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
  46. #define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000
  47. #define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000
  48. #define CONFIG_SYS_FSL_IFC_BASE2 0x500000000
  49. #define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000
  50. #define CONFIG_SYS_FSL_DCSR_BASE 0x700000000
  51. #define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000
  52. #define CONFIG_SYS_FSL_MC_BASE 0x80c000000
  53. #define CONFIG_SYS_FSL_MC_SIZE 0x4000000
  54. #define CONFIG_SYS_FSL_NI_BASE 0x810000000
  55. #define CONFIG_SYS_FSL_NI_SIZE 0x8000000
  56. #define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000
  57. #define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000
  58. #define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000
  59. #define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000
  60. #define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000
  61. #define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000
  62. #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000
  63. #define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000
  64. #define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000
  65. #define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000
  66. #define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000
  67. #define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000
  68. #define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000
  69. #define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000
  70. #define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000
  71. #elif defined(CONFIG_FSL_LSCH2)
  72. #define CONFIG_SYS_FSL_BOOTROM_BASE 0x0
  73. #define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000
  74. #define CONFIG_SYS_FSL_CCSR_BASE 0x1000000
  75. #define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000
  76. #define CONFIG_SYS_FSL_DCSR_BASE 0x20000000
  77. #define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000
  78. #define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
  79. #define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000
  80. #define CONFIG_SYS_FSL_IFC_BASE 0x60000000
  81. #define CONFIG_SYS_FSL_IFC_SIZE 0x20000000
  82. #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
  83. #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
  84. #define CONFIG_SYS_FSL_QBMAN_BASE 0x500000000
  85. #define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000
  86. #define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000
  87. #define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */
  88. #define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000
  89. #define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000
  90. #define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000
  91. #define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000
  92. #define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */
  93. #endif
  94. struct sys_mmu_table {
  95. u64 virt_addr;
  96. u64 phys_addr;
  97. u64 size;
  98. u64 memory_type;
  99. u64 share;
  100. };
  101. struct table_info {
  102. u64 *ptr;
  103. u64 table_base;
  104. u64 entry_size;
  105. };
  106. static const struct sys_mmu_table early_mmu_table[] = {
  107. #ifdef CONFIG_FSL_LSCH3
  108. { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
  109. CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
  110. { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
  111. CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
  112. /* For IFC Region #1, only the first 4MB is cache-enabled */
  113. { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
  114. CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PMD_SECT_NON_SHARE },
  115. { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
  116. CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
  117. CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
  118. MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
  119. { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
  120. CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
  121. { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
  122. CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
  123. { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
  124. CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
  125. { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
  126. CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
  127. #elif defined(CONFIG_FSL_LSCH2)
  128. { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
  129. CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
  130. { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
  131. CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
  132. { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
  133. CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
  134. { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
  135. CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
  136. { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
  137. CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
  138. { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
  139. CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
  140. #endif
  141. };
  142. static const struct sys_mmu_table final_mmu_table[] = {
  143. #ifdef CONFIG_FSL_LSCH3
  144. { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
  145. CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
  146. { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
  147. CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
  148. { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
  149. CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
  150. { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
  151. CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
  152. { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
  153. CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
  154. { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
  155. CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
  156. { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
  157. CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
  158. { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
  159. CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
  160. /* For QBMAN portal, only the first 64MB is cache-enabled */
  161. { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
  162. CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, PMD_SECT_NON_SHARE },
  163. { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
  164. CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
  165. CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
  166. MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
  167. { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
  168. CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
  169. { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
  170. CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
  171. { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
  172. CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
  173. #ifdef CONFIG_LS2080A
  174. { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
  175. CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
  176. #endif
  177. { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
  178. CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
  179. { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
  180. CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
  181. { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
  182. CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
  183. { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
  184. CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
  185. #elif defined(CONFIG_FSL_LSCH2)
  186. { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
  187. CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
  188. { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
  189. CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
  190. { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
  191. CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
  192. { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
  193. CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
  194. { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
  195. CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
  196. { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
  197. CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
  198. { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
  199. CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
  200. PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
  201. { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
  202. CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
  203. { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
  204. CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
  205. { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
  206. CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
  207. { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
  208. CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
  209. { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
  210. CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
  211. { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
  212. CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PMD_SECT_OUTER_SHARE },
  213. #endif
  214. };
  215. #endif
  216. int fsl_qoriq_core_to_cluster(unsigned int core);
  217. u32 cpu_mask(void);
  218. #endif /* _FSL_LAYERSCAPE_CPU_H */