meson-g12a-usb3-pcie.c 8.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Meson G12A USB3+PCIE Combo PHY driver
  4. *
  5. * Copyright (C) 2018 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
  6. * Copyright (C) 2019 BayLibre, SAS
  7. * Author: Neil Armstrong <narmstron@baylibre.com>
  8. */
  9. #include <common.h>
  10. #include <clk.h>
  11. #include <dm.h>
  12. #include <regmap.h>
  13. #include <errno.h>
  14. #include <asm/io.h>
  15. #include <reset.h>
  16. #include <bitfield.h>
  17. #include <generic-phy.h>
  18. #include <linux/bitops.h>
  19. #include <linux/compat.h>
  20. #include <linux/bitfield.h>
  21. #define PHY_R0 0x00
  22. #define PHY_R0_PCIE_POWER_STATE GENMASK(4, 0)
  23. #define PHY_R0_PCIE_USB3_SWITCH GENMASK(6, 5)
  24. #define PHY_R1 0x04
  25. #define PHY_R1_PHY_TX1_TERM_OFFSET GENMASK(4, 0)
  26. #define PHY_R1_PHY_TX0_TERM_OFFSET GENMASK(9, 5)
  27. #define PHY_R1_PHY_RX1_EQ GENMASK(12, 10)
  28. #define PHY_R1_PHY_RX0_EQ GENMASK(15, 13)
  29. #define PHY_R1_PHY_LOS_LEVEL GENMASK(20, 16)
  30. #define PHY_R1_PHY_LOS_BIAS GENMASK(23, 21)
  31. #define PHY_R1_PHY_REF_CLKDIV2 BIT(24)
  32. #define PHY_R1_PHY_MPLL_MULTIPLIER GENMASK(31, 25)
  33. #define PHY_R2 0x08
  34. #define PHY_R2_PCS_TX_DEEMPH_GEN2_6DB GENMASK(5, 0)
  35. #define PHY_R2_PCS_TX_DEEMPH_GEN2_3P5DB GENMASK(11, 6)
  36. #define PHY_R2_PCS_TX_DEEMPH_GEN1 GENMASK(17, 12)
  37. #define PHY_R2_PHY_TX_VBOOST_LVL GENMASK(20, 18)
  38. #define PHY_R4 0x10
  39. #define PHY_R4_PHY_CR_WRITE BIT(0)
  40. #define PHY_R4_PHY_CR_READ BIT(1)
  41. #define PHY_R4_PHY_CR_DATA_IN GENMASK(17, 2)
  42. #define PHY_R4_PHY_CR_CAP_DATA BIT(18)
  43. #define PHY_R4_PHY_CR_CAP_ADDR BIT(19)
  44. #define PHY_R5 0x14
  45. #define PHY_R5_PHY_CR_DATA_OUT GENMASK(15, 0)
  46. #define PHY_R5_PHY_CR_ACK BIT(16)
  47. #define PHY_R5_PHY_BS_OUT BIT(17)
  48. struct phy_g12a_usb3_pcie_priv {
  49. struct regmap *regmap;
  50. #if CONFIG_IS_ENABLED(CLK)
  51. struct clk clk;
  52. #endif
  53. struct reset_ctl_bulk resets;
  54. };
  55. static int phy_g12a_usb3_pcie_cr_bus_addr(struct phy_g12a_usb3_pcie_priv *priv,
  56. unsigned int addr)
  57. {
  58. unsigned int val, reg;
  59. int ret;
  60. reg = FIELD_PREP(PHY_R4_PHY_CR_DATA_IN, addr);
  61. regmap_write(priv->regmap, PHY_R4, reg);
  62. regmap_write(priv->regmap, PHY_R4, reg);
  63. regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_CAP_ADDR);
  64. ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
  65. (val & PHY_R5_PHY_CR_ACK),
  66. 5, 1000);
  67. if (ret)
  68. return ret;
  69. regmap_write(priv->regmap, PHY_R4, reg);
  70. ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
  71. !(val & PHY_R5_PHY_CR_ACK),
  72. 5, 1000);
  73. if (ret)
  74. return ret;
  75. return 0;
  76. }
  77. static int
  78. phy_g12a_usb3_pcie_cr_bus_read(struct phy_g12a_usb3_pcie_priv *priv,
  79. unsigned int addr, unsigned int *data)
  80. {
  81. unsigned int val;
  82. int ret;
  83. ret = phy_g12a_usb3_pcie_cr_bus_addr(priv, addr);
  84. if (ret)
  85. return ret;
  86. regmap_write(priv->regmap, PHY_R4, 0);
  87. regmap_write(priv->regmap, PHY_R4, PHY_R4_PHY_CR_READ);
  88. ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
  89. (val & PHY_R5_PHY_CR_ACK),
  90. 5, 1000);
  91. if (ret)
  92. return ret;
  93. *data = FIELD_GET(PHY_R5_PHY_CR_DATA_OUT, val);
  94. regmap_write(priv->regmap, PHY_R4, 0);
  95. ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
  96. !(val & PHY_R5_PHY_CR_ACK),
  97. 5, 1000);
  98. if (ret)
  99. return ret;
  100. return 0;
  101. }
  102. static int
  103. phy_g12a_usb3_pcie_cr_bus_write(struct phy_g12a_usb3_pcie_priv *priv,
  104. unsigned int addr, unsigned int data)
  105. {
  106. unsigned int val, reg;
  107. int ret;
  108. ret = phy_g12a_usb3_pcie_cr_bus_addr(priv, addr);
  109. if (ret)
  110. return ret;
  111. reg = FIELD_PREP(PHY_R4_PHY_CR_DATA_IN, data);
  112. regmap_write(priv->regmap, PHY_R4, reg);
  113. regmap_write(priv->regmap, PHY_R4, reg);
  114. regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_CAP_DATA);
  115. ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
  116. (val & PHY_R5_PHY_CR_ACK),
  117. 5, 1000);
  118. if (ret)
  119. return ret;
  120. regmap_write(priv->regmap, PHY_R4, reg);
  121. ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
  122. (val & PHY_R5_PHY_CR_ACK) == 0,
  123. 5, 1000);
  124. if (ret)
  125. return ret;
  126. regmap_write(priv->regmap, PHY_R4, reg);
  127. regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_WRITE);
  128. ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
  129. (val & PHY_R5_PHY_CR_ACK),
  130. 5, 1000);
  131. if (ret)
  132. return ret;
  133. regmap_write(priv->regmap, PHY_R4, reg);
  134. ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
  135. (val & PHY_R5_PHY_CR_ACK) == 0,
  136. 5, 1000);
  137. if (ret)
  138. return ret;
  139. return 0;
  140. }
  141. static int
  142. phy_g12a_usb3_pcie_cr_bus_update_bits(struct phy_g12a_usb3_pcie_priv *priv,
  143. uint offset, uint mask, uint val)
  144. {
  145. uint reg;
  146. int ret;
  147. ret = phy_g12a_usb3_pcie_cr_bus_read(priv, offset, &reg);
  148. if (ret)
  149. return ret;
  150. reg &= ~mask;
  151. return phy_g12a_usb3_pcie_cr_bus_write(priv, offset, reg | val);
  152. }
  153. static int phy_meson_g12a_usb3_init(struct phy *phy)
  154. {
  155. struct udevice *dev = phy->dev;
  156. struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(dev);
  157. unsigned int data;
  158. int ret;
  159. /* TOFIX Handle PCIE mode */
  160. ret = reset_assert_bulk(&priv->resets);
  161. udelay(1);
  162. ret |= reset_deassert_bulk(&priv->resets);
  163. if (ret)
  164. return ret;
  165. /* Switch PHY to USB3 */
  166. regmap_update_bits(priv->regmap, PHY_R0,
  167. PHY_R0_PCIE_USB3_SWITCH,
  168. PHY_R0_PCIE_USB3_SWITCH);
  169. /*
  170. * WORKAROUND: There is SSPHY suspend bug due to
  171. * which USB enumerates
  172. * in HS mode instead of SS mode. Workaround it by asserting
  173. * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus
  174. * mode
  175. */
  176. ret = phy_g12a_usb3_pcie_cr_bus_update_bits(priv, 0x102d,
  177. BIT(7), BIT(7));
  178. if (ret)
  179. return ret;
  180. ret = phy_g12a_usb3_pcie_cr_bus_update_bits(priv, 0x1010, 0xff0, 20);
  181. if (ret)
  182. return ret;
  183. /*
  184. * Fix RX Equalization setting as follows
  185. * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0
  186. * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1
  187. * LANE0.RX_OVRD_IN_HI.RX_EQ set to 3
  188. * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1
  189. */
  190. ret = phy_g12a_usb3_pcie_cr_bus_read(priv, 0x1006, &data);
  191. if (ret)
  192. return ret;
  193. data &= ~BIT(6);
  194. data |= BIT(7);
  195. data &= ~(0x7 << 8);
  196. data |= (0x3 << 8);
  197. data |= (1 << 11);
  198. ret = phy_g12a_usb3_pcie_cr_bus_write(priv, 0x1006, data);
  199. if (ret)
  200. return ret;
  201. /*
  202. * Set EQ and TX launch amplitudes as follows
  203. * LANE0.TX_OVRD_DRV_LO.PREEMPH set to 22
  204. * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 127
  205. * LANE0.TX_OVRD_DRV_LO.EN set to 1.
  206. */
  207. ret = phy_g12a_usb3_pcie_cr_bus_read(priv, 0x1002, &data);
  208. if (ret)
  209. return ret;
  210. data &= ~0x3f80;
  211. data |= (0x16 << 7);
  212. data &= ~0x7f;
  213. data |= (0x7f | BIT(14));
  214. ret = phy_g12a_usb3_pcie_cr_bus_write(priv, 0x1002, data);
  215. if (ret)
  216. return ret;
  217. /*
  218. * MPLL_LOOP_CTL.PROP_CNTRL = 8
  219. */
  220. ret = phy_g12a_usb3_pcie_cr_bus_update_bits(priv, 0x30,
  221. 0xf << 4, 8 << 4);
  222. if (ret)
  223. return ret;
  224. regmap_update_bits(priv->regmap, PHY_R2,
  225. PHY_R2_PHY_TX_VBOOST_LVL,
  226. FIELD_PREP(PHY_R2_PHY_TX_VBOOST_LVL, 0x4));
  227. regmap_update_bits(priv->regmap, PHY_R1,
  228. PHY_R1_PHY_LOS_BIAS | PHY_R1_PHY_LOS_LEVEL,
  229. FIELD_PREP(PHY_R1_PHY_LOS_BIAS, 4) |
  230. FIELD_PREP(PHY_R1_PHY_LOS_LEVEL, 9));
  231. return ret;
  232. }
  233. static int phy_meson_g12a_usb3_exit(struct phy *phy)
  234. {
  235. struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(phy->dev);
  236. return reset_assert_bulk(&priv->resets);
  237. }
  238. struct phy_ops meson_g12a_usb3_pcie_phy_ops = {
  239. .init = phy_meson_g12a_usb3_init,
  240. .exit = phy_meson_g12a_usb3_exit,
  241. };
  242. int meson_g12a_usb3_pcie_phy_probe(struct udevice *dev)
  243. {
  244. struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(dev);
  245. int ret;
  246. ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
  247. if (ret)
  248. return ret;
  249. ret = reset_get_bulk(dev, &priv->resets);
  250. if (ret == -ENOTSUPP)
  251. return 0;
  252. else if (ret)
  253. return ret;
  254. #if CONFIG_IS_ENABLED(CLK)
  255. ret = clk_get_by_index(dev, 0, &priv->clk);
  256. if (ret < 0)
  257. return ret;
  258. ret = clk_enable(&priv->clk);
  259. if (ret && ret != -ENOENT && ret != -ENOTSUPP) {
  260. pr_err("failed to enable PHY clock\n");
  261. clk_free(&priv->clk);
  262. return ret;
  263. }
  264. #endif
  265. return 0;
  266. }
  267. static const struct udevice_id meson_g12a_usb3_pcie_phy_ids[] = {
  268. { .compatible = "amlogic,g12a-usb3-pcie-phy" },
  269. { }
  270. };
  271. U_BOOT_DRIVER(meson_g12a_usb3_pcie_phy) = {
  272. .name = "meson_g12a_usb3_pcie_phy",
  273. .id = UCLASS_PHY,
  274. .of_match = meson_g12a_usb3_pcie_phy_ids,
  275. .probe = meson_g12a_usb3_pcie_phy_probe,
  276. .ops = &meson_g12a_usb3_pcie_phy_ops,
  277. .priv_auto_alloc_size = sizeof(struct phy_g12a_usb3_pcie_priv),
  278. };