e1000.c 170 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /**************************************************************************
  3. Intel Pro 1000 for ppcboot/das-u-boot
  4. Drivers are port from Intel's Linux driver e1000-4.3.15
  5. and from Etherboot pro 1000 driver by mrakes at vivato dot net
  6. tested on both gig copper and gig fiber boards
  7. ***************************************************************************/
  8. /*******************************************************************************
  9. Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
  10. Contact Information:
  11. Linux NICS <linux.nics@intel.com>
  12. Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  13. *******************************************************************************/
  14. /*
  15. * Copyright (C) Archway Digital Solutions.
  16. *
  17. * written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
  18. * 2/9/2002
  19. *
  20. * Copyright (C) Linux Networx.
  21. * Massive upgrade to work with the new intel gigabit NICs.
  22. * <ebiederman at lnxi dot com>
  23. *
  24. * Copyright 2011 Freescale Semiconductor, Inc.
  25. */
  26. #include <common.h>
  27. #include <cpu_func.h>
  28. #include <dm.h>
  29. #include <errno.h>
  30. #include <memalign.h>
  31. #include <pci.h>
  32. #include "e1000.h"
  33. #define TOUT_LOOP 100000
  34. #ifdef CONFIG_DM_ETH
  35. #define virt_to_bus(devno, v) dm_pci_virt_to_mem(devno, (void *) (v))
  36. #define bus_to_phys(devno, a) dm_pci_mem_to_phys(devno, a)
  37. #else
  38. #define virt_to_bus(devno, v) pci_virt_to_mem(devno, (void *) (v))
  39. #define bus_to_phys(devno, a) pci_mem_to_phys(devno, a)
  40. #endif
  41. #define E1000_DEFAULT_PCI_PBA 0x00000030
  42. #define E1000_DEFAULT_PCIE_PBA 0x000a0026
  43. /* NIC specific static variables go here */
  44. /* Intel i210 needs the DMA descriptor rings aligned to 128b */
  45. #define E1000_BUFFER_ALIGN 128
  46. /*
  47. * TODO(sjg@chromium.org): Even with driver model we share these buffers.
  48. * Concurrent receiving on multiple active Ethernet devices will not work.
  49. * Normally U-Boot does not support this anyway. To fix it in this driver,
  50. * move these buffers and the tx/rx pointers to struct e1000_hw.
  51. */
  52. DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN);
  53. DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN);
  54. DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN);
  55. static int tx_tail;
  56. static int rx_tail, rx_last;
  57. #ifdef CONFIG_DM_ETH
  58. static int num_cards; /* Number of E1000 devices seen so far */
  59. #endif
  60. static struct pci_device_id e1000_supported[] = {
  61. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542) },
  62. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER) },
  63. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER) },
  64. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER) },
  65. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER) },
  66. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER) },
  67. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM) },
  68. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM) },
  69. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER) },
  70. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER) },
  71. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER) },
  72. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER) },
  73. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER) },
  74. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER) },
  75. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM) },
  76. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER) },
  77. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF) },
  78. /* E1000 PCIe card */
  79. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER) },
  80. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER) },
  81. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES) },
  82. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER) },
  83. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER) },
  84. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER) },
  85. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE) },
  86. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL) },
  87. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD) },
  88. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER) },
  89. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER) },
  90. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES) },
  91. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI) },
  92. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E) },
  93. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT) },
  94. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L) },
  95. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L) },
  96. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3) },
  97. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT) },
  98. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT) },
  99. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT) },
  100. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT) },
  101. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED) },
  102. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED) },
  103. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER) },
  104. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER) },
  105. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS) },
  106. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES) },
  107. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS) },
  108. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX) },
  109. {}
  110. };
  111. /* Function forward declarations */
  112. static int e1000_setup_link(struct e1000_hw *hw);
  113. static int e1000_setup_fiber_link(struct e1000_hw *hw);
  114. static int e1000_setup_copper_link(struct e1000_hw *hw);
  115. static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
  116. static void e1000_config_collision_dist(struct e1000_hw *hw);
  117. static int e1000_config_mac_to_phy(struct e1000_hw *hw);
  118. static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
  119. static int e1000_check_for_link(struct e1000_hw *hw);
  120. static int e1000_wait_autoneg(struct e1000_hw *hw);
  121. static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
  122. uint16_t * duplex);
  123. static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
  124. uint16_t * phy_data);
  125. static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
  126. uint16_t phy_data);
  127. static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
  128. static int e1000_phy_reset(struct e1000_hw *hw);
  129. static int e1000_detect_gig_phy(struct e1000_hw *hw);
  130. static void e1000_set_media_type(struct e1000_hw *hw);
  131. static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
  132. static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
  133. static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
  134. #ifndef CONFIG_E1000_NO_NVM
  135. static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
  136. static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
  137. static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
  138. uint16_t words,
  139. uint16_t *data);
  140. /******************************************************************************
  141. * Raises the EEPROM's clock input.
  142. *
  143. * hw - Struct containing variables accessed by shared code
  144. * eecd - EECD's current value
  145. *****************************************************************************/
  146. void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
  147. {
  148. /* Raise the clock input to the EEPROM (by setting the SK bit), and then
  149. * wait 50 microseconds.
  150. */
  151. *eecd = *eecd | E1000_EECD_SK;
  152. E1000_WRITE_REG(hw, EECD, *eecd);
  153. E1000_WRITE_FLUSH(hw);
  154. udelay(50);
  155. }
  156. /******************************************************************************
  157. * Lowers the EEPROM's clock input.
  158. *
  159. * hw - Struct containing variables accessed by shared code
  160. * eecd - EECD's current value
  161. *****************************************************************************/
  162. void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
  163. {
  164. /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
  165. * wait 50 microseconds.
  166. */
  167. *eecd = *eecd & ~E1000_EECD_SK;
  168. E1000_WRITE_REG(hw, EECD, *eecd);
  169. E1000_WRITE_FLUSH(hw);
  170. udelay(50);
  171. }
  172. /******************************************************************************
  173. * Shift data bits out to the EEPROM.
  174. *
  175. * hw - Struct containing variables accessed by shared code
  176. * data - data to send to the EEPROM
  177. * count - number of bits to shift out
  178. *****************************************************************************/
  179. static void
  180. e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
  181. {
  182. uint32_t eecd;
  183. uint32_t mask;
  184. /* We need to shift "count" bits out to the EEPROM. So, value in the
  185. * "data" parameter will be shifted out to the EEPROM one bit at a time.
  186. * In order to do this, "data" must be broken down into bits.
  187. */
  188. mask = 0x01 << (count - 1);
  189. eecd = E1000_READ_REG(hw, EECD);
  190. eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
  191. do {
  192. /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
  193. * and then raising and then lowering the clock (the SK bit controls
  194. * the clock input to the EEPROM). A "0" is shifted out to the EEPROM
  195. * by setting "DI" to "0" and then raising and then lowering the clock.
  196. */
  197. eecd &= ~E1000_EECD_DI;
  198. if (data & mask)
  199. eecd |= E1000_EECD_DI;
  200. E1000_WRITE_REG(hw, EECD, eecd);
  201. E1000_WRITE_FLUSH(hw);
  202. udelay(50);
  203. e1000_raise_ee_clk(hw, &eecd);
  204. e1000_lower_ee_clk(hw, &eecd);
  205. mask = mask >> 1;
  206. } while (mask);
  207. /* We leave the "DI" bit set to "0" when we leave this routine. */
  208. eecd &= ~E1000_EECD_DI;
  209. E1000_WRITE_REG(hw, EECD, eecd);
  210. }
  211. /******************************************************************************
  212. * Shift data bits in from the EEPROM
  213. *
  214. * hw - Struct containing variables accessed by shared code
  215. *****************************************************************************/
  216. static uint16_t
  217. e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
  218. {
  219. uint32_t eecd;
  220. uint32_t i;
  221. uint16_t data;
  222. /* In order to read a register from the EEPROM, we need to shift 'count'
  223. * bits in from the EEPROM. Bits are "shifted in" by raising the clock
  224. * input to the EEPROM (setting the SK bit), and then reading the
  225. * value of the "DO" bit. During this "shifting in" process the
  226. * "DI" bit should always be clear.
  227. */
  228. eecd = E1000_READ_REG(hw, EECD);
  229. eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
  230. data = 0;
  231. for (i = 0; i < count; i++) {
  232. data = data << 1;
  233. e1000_raise_ee_clk(hw, &eecd);
  234. eecd = E1000_READ_REG(hw, EECD);
  235. eecd &= ~(E1000_EECD_DI);
  236. if (eecd & E1000_EECD_DO)
  237. data |= 1;
  238. e1000_lower_ee_clk(hw, &eecd);
  239. }
  240. return data;
  241. }
  242. /******************************************************************************
  243. * Returns EEPROM to a "standby" state
  244. *
  245. * hw - Struct containing variables accessed by shared code
  246. *****************************************************************************/
  247. void e1000_standby_eeprom(struct e1000_hw *hw)
  248. {
  249. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  250. uint32_t eecd;
  251. eecd = E1000_READ_REG(hw, EECD);
  252. if (eeprom->type == e1000_eeprom_microwire) {
  253. eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
  254. E1000_WRITE_REG(hw, EECD, eecd);
  255. E1000_WRITE_FLUSH(hw);
  256. udelay(eeprom->delay_usec);
  257. /* Clock high */
  258. eecd |= E1000_EECD_SK;
  259. E1000_WRITE_REG(hw, EECD, eecd);
  260. E1000_WRITE_FLUSH(hw);
  261. udelay(eeprom->delay_usec);
  262. /* Select EEPROM */
  263. eecd |= E1000_EECD_CS;
  264. E1000_WRITE_REG(hw, EECD, eecd);
  265. E1000_WRITE_FLUSH(hw);
  266. udelay(eeprom->delay_usec);
  267. /* Clock low */
  268. eecd &= ~E1000_EECD_SK;
  269. E1000_WRITE_REG(hw, EECD, eecd);
  270. E1000_WRITE_FLUSH(hw);
  271. udelay(eeprom->delay_usec);
  272. } else if (eeprom->type == e1000_eeprom_spi) {
  273. /* Toggle CS to flush commands */
  274. eecd |= E1000_EECD_CS;
  275. E1000_WRITE_REG(hw, EECD, eecd);
  276. E1000_WRITE_FLUSH(hw);
  277. udelay(eeprom->delay_usec);
  278. eecd &= ~E1000_EECD_CS;
  279. E1000_WRITE_REG(hw, EECD, eecd);
  280. E1000_WRITE_FLUSH(hw);
  281. udelay(eeprom->delay_usec);
  282. }
  283. }
  284. /***************************************************************************
  285. * Description: Determines if the onboard NVM is FLASH or EEPROM.
  286. *
  287. * hw - Struct containing variables accessed by shared code
  288. ****************************************************************************/
  289. static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
  290. {
  291. uint32_t eecd = 0;
  292. DEBUGFUNC();
  293. if (hw->mac_type == e1000_ich8lan)
  294. return false;
  295. if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
  296. eecd = E1000_READ_REG(hw, EECD);
  297. /* Isolate bits 15 & 16 */
  298. eecd = ((eecd >> 15) & 0x03);
  299. /* If both bits are set, device is Flash type */
  300. if (eecd == 0x03)
  301. return false;
  302. }
  303. return true;
  304. }
  305. /******************************************************************************
  306. * Prepares EEPROM for access
  307. *
  308. * hw - Struct containing variables accessed by shared code
  309. *
  310. * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
  311. * function should be called before issuing a command to the EEPROM.
  312. *****************************************************************************/
  313. int32_t e1000_acquire_eeprom(struct e1000_hw *hw)
  314. {
  315. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  316. uint32_t eecd, i = 0;
  317. DEBUGFUNC();
  318. if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
  319. return -E1000_ERR_SWFW_SYNC;
  320. eecd = E1000_READ_REG(hw, EECD);
  321. if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) {
  322. /* Request EEPROM Access */
  323. if (hw->mac_type > e1000_82544) {
  324. eecd |= E1000_EECD_REQ;
  325. E1000_WRITE_REG(hw, EECD, eecd);
  326. eecd = E1000_READ_REG(hw, EECD);
  327. while ((!(eecd & E1000_EECD_GNT)) &&
  328. (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
  329. i++;
  330. udelay(5);
  331. eecd = E1000_READ_REG(hw, EECD);
  332. }
  333. if (!(eecd & E1000_EECD_GNT)) {
  334. eecd &= ~E1000_EECD_REQ;
  335. E1000_WRITE_REG(hw, EECD, eecd);
  336. DEBUGOUT("Could not acquire EEPROM grant\n");
  337. return -E1000_ERR_EEPROM;
  338. }
  339. }
  340. }
  341. /* Setup EEPROM for Read/Write */
  342. if (eeprom->type == e1000_eeprom_microwire) {
  343. /* Clear SK and DI */
  344. eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
  345. E1000_WRITE_REG(hw, EECD, eecd);
  346. /* Set CS */
  347. eecd |= E1000_EECD_CS;
  348. E1000_WRITE_REG(hw, EECD, eecd);
  349. } else if (eeprom->type == e1000_eeprom_spi) {
  350. /* Clear SK and CS */
  351. eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
  352. E1000_WRITE_REG(hw, EECD, eecd);
  353. udelay(1);
  354. }
  355. return E1000_SUCCESS;
  356. }
  357. /******************************************************************************
  358. * Sets up eeprom variables in the hw struct. Must be called after mac_type
  359. * is configured. Additionally, if this is ICH8, the flash controller GbE
  360. * registers must be mapped, or this will crash.
  361. *
  362. * hw - Struct containing variables accessed by shared code
  363. *****************************************************************************/
  364. static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
  365. {
  366. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  367. uint32_t eecd;
  368. int32_t ret_val = E1000_SUCCESS;
  369. uint16_t eeprom_size;
  370. if (hw->mac_type == e1000_igb)
  371. eecd = E1000_READ_REG(hw, I210_EECD);
  372. else
  373. eecd = E1000_READ_REG(hw, EECD);
  374. DEBUGFUNC();
  375. switch (hw->mac_type) {
  376. case e1000_82542_rev2_0:
  377. case e1000_82542_rev2_1:
  378. case e1000_82543:
  379. case e1000_82544:
  380. eeprom->type = e1000_eeprom_microwire;
  381. eeprom->word_size = 64;
  382. eeprom->opcode_bits = 3;
  383. eeprom->address_bits = 6;
  384. eeprom->delay_usec = 50;
  385. eeprom->use_eerd = false;
  386. eeprom->use_eewr = false;
  387. break;
  388. case e1000_82540:
  389. case e1000_82545:
  390. case e1000_82545_rev_3:
  391. case e1000_82546:
  392. case e1000_82546_rev_3:
  393. eeprom->type = e1000_eeprom_microwire;
  394. eeprom->opcode_bits = 3;
  395. eeprom->delay_usec = 50;
  396. if (eecd & E1000_EECD_SIZE) {
  397. eeprom->word_size = 256;
  398. eeprom->address_bits = 8;
  399. } else {
  400. eeprom->word_size = 64;
  401. eeprom->address_bits = 6;
  402. }
  403. eeprom->use_eerd = false;
  404. eeprom->use_eewr = false;
  405. break;
  406. case e1000_82541:
  407. case e1000_82541_rev_2:
  408. case e1000_82547:
  409. case e1000_82547_rev_2:
  410. if (eecd & E1000_EECD_TYPE) {
  411. eeprom->type = e1000_eeprom_spi;
  412. eeprom->opcode_bits = 8;
  413. eeprom->delay_usec = 1;
  414. if (eecd & E1000_EECD_ADDR_BITS) {
  415. eeprom->page_size = 32;
  416. eeprom->address_bits = 16;
  417. } else {
  418. eeprom->page_size = 8;
  419. eeprom->address_bits = 8;
  420. }
  421. } else {
  422. eeprom->type = e1000_eeprom_microwire;
  423. eeprom->opcode_bits = 3;
  424. eeprom->delay_usec = 50;
  425. if (eecd & E1000_EECD_ADDR_BITS) {
  426. eeprom->word_size = 256;
  427. eeprom->address_bits = 8;
  428. } else {
  429. eeprom->word_size = 64;
  430. eeprom->address_bits = 6;
  431. }
  432. }
  433. eeprom->use_eerd = false;
  434. eeprom->use_eewr = false;
  435. break;
  436. case e1000_82571:
  437. case e1000_82572:
  438. eeprom->type = e1000_eeprom_spi;
  439. eeprom->opcode_bits = 8;
  440. eeprom->delay_usec = 1;
  441. if (eecd & E1000_EECD_ADDR_BITS) {
  442. eeprom->page_size = 32;
  443. eeprom->address_bits = 16;
  444. } else {
  445. eeprom->page_size = 8;
  446. eeprom->address_bits = 8;
  447. }
  448. eeprom->use_eerd = false;
  449. eeprom->use_eewr = false;
  450. break;
  451. case e1000_82573:
  452. case e1000_82574:
  453. eeprom->type = e1000_eeprom_spi;
  454. eeprom->opcode_bits = 8;
  455. eeprom->delay_usec = 1;
  456. if (eecd & E1000_EECD_ADDR_BITS) {
  457. eeprom->page_size = 32;
  458. eeprom->address_bits = 16;
  459. } else {
  460. eeprom->page_size = 8;
  461. eeprom->address_bits = 8;
  462. }
  463. if (e1000_is_onboard_nvm_eeprom(hw) == false) {
  464. eeprom->use_eerd = true;
  465. eeprom->use_eewr = true;
  466. eeprom->type = e1000_eeprom_flash;
  467. eeprom->word_size = 2048;
  468. /* Ensure that the Autonomous FLASH update bit is cleared due to
  469. * Flash update issue on parts which use a FLASH for NVM. */
  470. eecd &= ~E1000_EECD_AUPDEN;
  471. E1000_WRITE_REG(hw, EECD, eecd);
  472. }
  473. break;
  474. case e1000_80003es2lan:
  475. eeprom->type = e1000_eeprom_spi;
  476. eeprom->opcode_bits = 8;
  477. eeprom->delay_usec = 1;
  478. if (eecd & E1000_EECD_ADDR_BITS) {
  479. eeprom->page_size = 32;
  480. eeprom->address_bits = 16;
  481. } else {
  482. eeprom->page_size = 8;
  483. eeprom->address_bits = 8;
  484. }
  485. eeprom->use_eerd = true;
  486. eeprom->use_eewr = false;
  487. break;
  488. case e1000_igb:
  489. /* i210 has 4k of iNVM mapped as EEPROM */
  490. eeprom->type = e1000_eeprom_invm;
  491. eeprom->opcode_bits = 8;
  492. eeprom->delay_usec = 1;
  493. eeprom->page_size = 32;
  494. eeprom->address_bits = 16;
  495. eeprom->use_eerd = true;
  496. eeprom->use_eewr = false;
  497. break;
  498. default:
  499. break;
  500. }
  501. if (eeprom->type == e1000_eeprom_spi ||
  502. eeprom->type == e1000_eeprom_invm) {
  503. /* eeprom_size will be an enum [0..8] that maps
  504. * to eeprom sizes 128B to
  505. * 32KB (incremented by powers of 2).
  506. */
  507. if (hw->mac_type <= e1000_82547_rev_2) {
  508. /* Set to default value for initial eeprom read. */
  509. eeprom->word_size = 64;
  510. ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
  511. &eeprom_size);
  512. if (ret_val)
  513. return ret_val;
  514. eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
  515. >> EEPROM_SIZE_SHIFT;
  516. /* 256B eeprom size was not supported in earlier
  517. * hardware, so we bump eeprom_size up one to
  518. * ensure that "1" (which maps to 256B) is never
  519. * the result used in the shifting logic below. */
  520. if (eeprom_size)
  521. eeprom_size++;
  522. } else {
  523. eeprom_size = (uint16_t)((eecd &
  524. E1000_EECD_SIZE_EX_MASK) >>
  525. E1000_EECD_SIZE_EX_SHIFT);
  526. }
  527. eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
  528. }
  529. return ret_val;
  530. }
  531. /******************************************************************************
  532. * Polls the status bit (bit 1) of the EERD to determine when the read is done.
  533. *
  534. * hw - Struct containing variables accessed by shared code
  535. *****************************************************************************/
  536. static int32_t
  537. e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
  538. {
  539. uint32_t attempts = 100000;
  540. uint32_t i, reg = 0;
  541. int32_t done = E1000_ERR_EEPROM;
  542. for (i = 0; i < attempts; i++) {
  543. if (eerd == E1000_EEPROM_POLL_READ) {
  544. if (hw->mac_type == e1000_igb)
  545. reg = E1000_READ_REG(hw, I210_EERD);
  546. else
  547. reg = E1000_READ_REG(hw, EERD);
  548. } else {
  549. if (hw->mac_type == e1000_igb)
  550. reg = E1000_READ_REG(hw, I210_EEWR);
  551. else
  552. reg = E1000_READ_REG(hw, EEWR);
  553. }
  554. if (reg & E1000_EEPROM_RW_REG_DONE) {
  555. done = E1000_SUCCESS;
  556. break;
  557. }
  558. udelay(5);
  559. }
  560. return done;
  561. }
  562. /******************************************************************************
  563. * Reads a 16 bit word from the EEPROM using the EERD register.
  564. *
  565. * hw - Struct containing variables accessed by shared code
  566. * offset - offset of word in the EEPROM to read
  567. * data - word read from the EEPROM
  568. * words - number of words to read
  569. *****************************************************************************/
  570. static int32_t
  571. e1000_read_eeprom_eerd(struct e1000_hw *hw,
  572. uint16_t offset,
  573. uint16_t words,
  574. uint16_t *data)
  575. {
  576. uint32_t i, eerd = 0;
  577. int32_t error = 0;
  578. for (i = 0; i < words; i++) {
  579. eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
  580. E1000_EEPROM_RW_REG_START;
  581. if (hw->mac_type == e1000_igb)
  582. E1000_WRITE_REG(hw, I210_EERD, eerd);
  583. else
  584. E1000_WRITE_REG(hw, EERD, eerd);
  585. error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
  586. if (error)
  587. break;
  588. if (hw->mac_type == e1000_igb) {
  589. data[i] = (E1000_READ_REG(hw, I210_EERD) >>
  590. E1000_EEPROM_RW_REG_DATA);
  591. } else {
  592. data[i] = (E1000_READ_REG(hw, EERD) >>
  593. E1000_EEPROM_RW_REG_DATA);
  594. }
  595. }
  596. return error;
  597. }
  598. void e1000_release_eeprom(struct e1000_hw *hw)
  599. {
  600. uint32_t eecd;
  601. DEBUGFUNC();
  602. eecd = E1000_READ_REG(hw, EECD);
  603. if (hw->eeprom.type == e1000_eeprom_spi) {
  604. eecd |= E1000_EECD_CS; /* Pull CS high */
  605. eecd &= ~E1000_EECD_SK; /* Lower SCK */
  606. E1000_WRITE_REG(hw, EECD, eecd);
  607. udelay(hw->eeprom.delay_usec);
  608. } else if (hw->eeprom.type == e1000_eeprom_microwire) {
  609. /* cleanup eeprom */
  610. /* CS on Microwire is active-high */
  611. eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
  612. E1000_WRITE_REG(hw, EECD, eecd);
  613. /* Rising edge of clock */
  614. eecd |= E1000_EECD_SK;
  615. E1000_WRITE_REG(hw, EECD, eecd);
  616. E1000_WRITE_FLUSH(hw);
  617. udelay(hw->eeprom.delay_usec);
  618. /* Falling edge of clock */
  619. eecd &= ~E1000_EECD_SK;
  620. E1000_WRITE_REG(hw, EECD, eecd);
  621. E1000_WRITE_FLUSH(hw);
  622. udelay(hw->eeprom.delay_usec);
  623. }
  624. /* Stop requesting EEPROM access */
  625. if (hw->mac_type > e1000_82544) {
  626. eecd &= ~E1000_EECD_REQ;
  627. E1000_WRITE_REG(hw, EECD, eecd);
  628. }
  629. e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
  630. }
  631. /******************************************************************************
  632. * Reads a 16 bit word from the EEPROM.
  633. *
  634. * hw - Struct containing variables accessed by shared code
  635. *****************************************************************************/
  636. static int32_t
  637. e1000_spi_eeprom_ready(struct e1000_hw *hw)
  638. {
  639. uint16_t retry_count = 0;
  640. uint8_t spi_stat_reg;
  641. DEBUGFUNC();
  642. /* Read "Status Register" repeatedly until the LSB is cleared. The
  643. * EEPROM will signal that the command has been completed by clearing
  644. * bit 0 of the internal status register. If it's not cleared within
  645. * 5 milliseconds, then error out.
  646. */
  647. retry_count = 0;
  648. do {
  649. e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
  650. hw->eeprom.opcode_bits);
  651. spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
  652. if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
  653. break;
  654. udelay(5);
  655. retry_count += 5;
  656. e1000_standby_eeprom(hw);
  657. } while (retry_count < EEPROM_MAX_RETRY_SPI);
  658. /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
  659. * only 0-5mSec on 5V devices)
  660. */
  661. if (retry_count >= EEPROM_MAX_RETRY_SPI) {
  662. DEBUGOUT("SPI EEPROM Status error\n");
  663. return -E1000_ERR_EEPROM;
  664. }
  665. return E1000_SUCCESS;
  666. }
  667. /******************************************************************************
  668. * Reads a 16 bit word from the EEPROM.
  669. *
  670. * hw - Struct containing variables accessed by shared code
  671. * offset - offset of word in the EEPROM to read
  672. * data - word read from the EEPROM
  673. *****************************************************************************/
  674. static int32_t
  675. e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
  676. uint16_t words, uint16_t *data)
  677. {
  678. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  679. uint32_t i = 0;
  680. DEBUGFUNC();
  681. /* If eeprom is not yet detected, do so now */
  682. if (eeprom->word_size == 0)
  683. e1000_init_eeprom_params(hw);
  684. /* A check for invalid values: offset too large, too many words,
  685. * and not enough words.
  686. */
  687. if ((offset >= eeprom->word_size) ||
  688. (words > eeprom->word_size - offset) ||
  689. (words == 0)) {
  690. DEBUGOUT("\"words\" parameter out of bounds."
  691. "Words = %d, size = %d\n", offset, eeprom->word_size);
  692. return -E1000_ERR_EEPROM;
  693. }
  694. /* EEPROM's that don't use EERD to read require us to bit-bang the SPI
  695. * directly. In this case, we need to acquire the EEPROM so that
  696. * FW or other port software does not interrupt.
  697. */
  698. if (e1000_is_onboard_nvm_eeprom(hw) == true &&
  699. hw->eeprom.use_eerd == false) {
  700. /* Prepare the EEPROM for bit-bang reading */
  701. if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
  702. return -E1000_ERR_EEPROM;
  703. }
  704. /* Eerd register EEPROM access requires no eeprom aquire/release */
  705. if (eeprom->use_eerd == true)
  706. return e1000_read_eeprom_eerd(hw, offset, words, data);
  707. /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
  708. * acquired the EEPROM at this point, so any returns should relase it */
  709. if (eeprom->type == e1000_eeprom_spi) {
  710. uint16_t word_in;
  711. uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
  712. if (e1000_spi_eeprom_ready(hw)) {
  713. e1000_release_eeprom(hw);
  714. return -E1000_ERR_EEPROM;
  715. }
  716. e1000_standby_eeprom(hw);
  717. /* Some SPI eeproms use the 8th address bit embedded in
  718. * the opcode */
  719. if ((eeprom->address_bits == 8) && (offset >= 128))
  720. read_opcode |= EEPROM_A8_OPCODE_SPI;
  721. /* Send the READ command (opcode + addr) */
  722. e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
  723. e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
  724. eeprom->address_bits);
  725. /* Read the data. The address of the eeprom internally
  726. * increments with each byte (spi) being read, saving on the
  727. * overhead of eeprom setup and tear-down. The address
  728. * counter will roll over if reading beyond the size of
  729. * the eeprom, thus allowing the entire memory to be read
  730. * starting from any offset. */
  731. for (i = 0; i < words; i++) {
  732. word_in = e1000_shift_in_ee_bits(hw, 16);
  733. data[i] = (word_in >> 8) | (word_in << 8);
  734. }
  735. } else if (eeprom->type == e1000_eeprom_microwire) {
  736. for (i = 0; i < words; i++) {
  737. /* Send the READ command (opcode + addr) */
  738. e1000_shift_out_ee_bits(hw,
  739. EEPROM_READ_OPCODE_MICROWIRE,
  740. eeprom->opcode_bits);
  741. e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
  742. eeprom->address_bits);
  743. /* Read the data. For microwire, each word requires
  744. * the overhead of eeprom setup and tear-down. */
  745. data[i] = e1000_shift_in_ee_bits(hw, 16);
  746. e1000_standby_eeprom(hw);
  747. }
  748. }
  749. /* End this read operation */
  750. e1000_release_eeprom(hw);
  751. return E1000_SUCCESS;
  752. }
  753. #ifndef CONFIG_DM_ETH
  754. /******************************************************************************
  755. * e1000_write_eeprom_srwr - Write to Shadow Ram using EEWR
  756. * @hw: pointer to the HW structure
  757. * @offset: offset within the Shadow Ram to be written to
  758. * @words: number of words to write
  759. * @data: 16 bit word(s) to be written to the Shadow Ram
  760. *
  761. * Writes data to Shadow Ram at offset using EEWR register.
  762. *
  763. * If e1000_update_eeprom_checksum_i210 is not called after this function, the
  764. * Shadow Ram will most likely contain an invalid checksum.
  765. *****************************************************************************/
  766. static int32_t e1000_write_eeprom_srwr(struct e1000_hw *hw, uint16_t offset,
  767. uint16_t words, uint16_t *data)
  768. {
  769. struct e1000_eeprom_info *eeprom = &hw->eeprom;
  770. uint32_t i, k, eewr = 0;
  771. uint32_t attempts = 100000;
  772. int32_t ret_val = 0;
  773. /* A check for invalid values: offset too large, too many words,
  774. * too many words for the offset, and not enough words.
  775. */
  776. if ((offset >= eeprom->word_size) ||
  777. (words > (eeprom->word_size - offset)) || (words == 0)) {
  778. DEBUGOUT("nvm parameter(s) out of bounds\n");
  779. ret_val = -E1000_ERR_EEPROM;
  780. goto out;
  781. }
  782. for (i = 0; i < words; i++) {
  783. eewr = ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT)
  784. | (data[i] << E1000_EEPROM_RW_REG_DATA) |
  785. E1000_EEPROM_RW_REG_START;
  786. E1000_WRITE_REG(hw, I210_EEWR, eewr);
  787. for (k = 0; k < attempts; k++) {
  788. if (E1000_EEPROM_RW_REG_DONE &
  789. E1000_READ_REG(hw, I210_EEWR)) {
  790. ret_val = 0;
  791. break;
  792. }
  793. udelay(5);
  794. }
  795. if (ret_val) {
  796. DEBUGOUT("Shadow RAM write EEWR timed out\n");
  797. break;
  798. }
  799. }
  800. out:
  801. return ret_val;
  802. }
  803. /******************************************************************************
  804. * e1000_pool_flash_update_done_i210 - Pool FLUDONE status.
  805. * @hw: pointer to the HW structure
  806. *
  807. *****************************************************************************/
  808. static int32_t e1000_pool_flash_update_done_i210(struct e1000_hw *hw)
  809. {
  810. int32_t ret_val = -E1000_ERR_EEPROM;
  811. uint32_t i, reg;
  812. for (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) {
  813. reg = E1000_READ_REG(hw, EECD);
  814. if (reg & E1000_EECD_FLUDONE_I210) {
  815. ret_val = 0;
  816. break;
  817. }
  818. udelay(5);
  819. }
  820. return ret_val;
  821. }
  822. /******************************************************************************
  823. * e1000_update_flash_i210 - Commit EEPROM to the flash
  824. * @hw: pointer to the HW structure
  825. *
  826. *****************************************************************************/
  827. static int32_t e1000_update_flash_i210(struct e1000_hw *hw)
  828. {
  829. int32_t ret_val = 0;
  830. uint32_t flup;
  831. ret_val = e1000_pool_flash_update_done_i210(hw);
  832. if (ret_val == -E1000_ERR_EEPROM) {
  833. DEBUGOUT("Flash update time out\n");
  834. goto out;
  835. }
  836. flup = E1000_READ_REG(hw, EECD) | E1000_EECD_FLUPD_I210;
  837. E1000_WRITE_REG(hw, EECD, flup);
  838. ret_val = e1000_pool_flash_update_done_i210(hw);
  839. if (ret_val)
  840. DEBUGOUT("Flash update time out\n");
  841. else
  842. DEBUGOUT("Flash update complete\n");
  843. out:
  844. return ret_val;
  845. }
  846. /******************************************************************************
  847. * e1000_update_eeprom_checksum_i210 - Update EEPROM checksum
  848. * @hw: pointer to the HW structure
  849. *
  850. * Updates the EEPROM checksum by reading/adding each word of the EEPROM
  851. * up to the checksum. Then calculates the EEPROM checksum and writes the
  852. * value to the EEPROM. Next commit EEPROM data onto the Flash.
  853. *****************************************************************************/
  854. static int32_t e1000_update_eeprom_checksum_i210(struct e1000_hw *hw)
  855. {
  856. int32_t ret_val = 0;
  857. uint16_t checksum = 0;
  858. uint16_t i, nvm_data;
  859. /* Read the first word from the EEPROM. If this times out or fails, do
  860. * not continue or we could be in for a very long wait while every
  861. * EEPROM read fails
  862. */
  863. ret_val = e1000_read_eeprom_eerd(hw, 0, 1, &nvm_data);
  864. if (ret_val) {
  865. DEBUGOUT("EEPROM read failed\n");
  866. goto out;
  867. }
  868. if (!(e1000_get_hw_eeprom_semaphore(hw))) {
  869. /* Do not use hw->nvm.ops.write, hw->nvm.ops.read
  870. * because we do not want to take the synchronization
  871. * semaphores twice here.
  872. */
  873. for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
  874. ret_val = e1000_read_eeprom_eerd(hw, i, 1, &nvm_data);
  875. if (ret_val) {
  876. e1000_put_hw_eeprom_semaphore(hw);
  877. DEBUGOUT("EEPROM Read Error while updating checksum.\n");
  878. goto out;
  879. }
  880. checksum += nvm_data;
  881. }
  882. checksum = (uint16_t)EEPROM_SUM - checksum;
  883. ret_val = e1000_write_eeprom_srwr(hw, EEPROM_CHECKSUM_REG, 1,
  884. &checksum);
  885. if (ret_val) {
  886. e1000_put_hw_eeprom_semaphore(hw);
  887. DEBUGOUT("EEPROM Write Error while updating checksum.\n");
  888. goto out;
  889. }
  890. e1000_put_hw_eeprom_semaphore(hw);
  891. ret_val = e1000_update_flash_i210(hw);
  892. } else {
  893. ret_val = -E1000_ERR_SWFW_SYNC;
  894. }
  895. out:
  896. return ret_val;
  897. }
  898. #endif
  899. /******************************************************************************
  900. * Verifies that the EEPROM has a valid checksum
  901. *
  902. * hw - Struct containing variables accessed by shared code
  903. *
  904. * Reads the first 64 16 bit words of the EEPROM and sums the values read.
  905. * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
  906. * valid.
  907. *****************************************************************************/
  908. static int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
  909. {
  910. uint16_t i, checksum, checksum_reg, *buf;
  911. DEBUGFUNC();
  912. /* Allocate a temporary buffer */
  913. buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1));
  914. if (!buf) {
  915. E1000_ERR(hw, "Unable to allocate EEPROM buffer!\n");
  916. return -E1000_ERR_EEPROM;
  917. }
  918. /* Read the EEPROM */
  919. if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) {
  920. E1000_ERR(hw, "Unable to read EEPROM!\n");
  921. return -E1000_ERR_EEPROM;
  922. }
  923. /* Compute the checksum */
  924. checksum = 0;
  925. for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
  926. checksum += buf[i];
  927. checksum = ((uint16_t)EEPROM_SUM) - checksum;
  928. checksum_reg = buf[i];
  929. /* Verify it! */
  930. if (checksum == checksum_reg)
  931. return 0;
  932. /* Hrm, verification failed, print an error */
  933. E1000_ERR(hw, "EEPROM checksum is incorrect!\n");
  934. E1000_ERR(hw, " ...register was 0x%04hx, calculated 0x%04hx\n",
  935. checksum_reg, checksum);
  936. return -E1000_ERR_EEPROM;
  937. }
  938. #endif /* CONFIG_E1000_NO_NVM */
  939. /*****************************************************************************
  940. * Set PHY to class A mode
  941. * Assumes the following operations will follow to enable the new class mode.
  942. * 1. Do a PHY soft reset
  943. * 2. Restart auto-negotiation or force link.
  944. *
  945. * hw - Struct containing variables accessed by shared code
  946. ****************************************************************************/
  947. static int32_t
  948. e1000_set_phy_mode(struct e1000_hw *hw)
  949. {
  950. #ifndef CONFIG_E1000_NO_NVM
  951. int32_t ret_val;
  952. uint16_t eeprom_data;
  953. DEBUGFUNC();
  954. if ((hw->mac_type == e1000_82545_rev_3) &&
  955. (hw->media_type == e1000_media_type_copper)) {
  956. ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
  957. 1, &eeprom_data);
  958. if (ret_val)
  959. return ret_val;
  960. if ((eeprom_data != EEPROM_RESERVED_WORD) &&
  961. (eeprom_data & EEPROM_PHY_CLASS_A)) {
  962. ret_val = e1000_write_phy_reg(hw,
  963. M88E1000_PHY_PAGE_SELECT, 0x000B);
  964. if (ret_val)
  965. return ret_val;
  966. ret_val = e1000_write_phy_reg(hw,
  967. M88E1000_PHY_GEN_CONTROL, 0x8104);
  968. if (ret_val)
  969. return ret_val;
  970. hw->phy_reset_disable = false;
  971. }
  972. }
  973. #endif
  974. return E1000_SUCCESS;
  975. }
  976. #ifndef CONFIG_E1000_NO_NVM
  977. /***************************************************************************
  978. *
  979. * Obtaining software semaphore bit (SMBI) before resetting PHY.
  980. *
  981. * hw: Struct containing variables accessed by shared code
  982. *
  983. * returns: - E1000_ERR_RESET if fail to obtain semaphore.
  984. * E1000_SUCCESS at any other case.
  985. *
  986. ***************************************************************************/
  987. static int32_t
  988. e1000_get_software_semaphore(struct e1000_hw *hw)
  989. {
  990. int32_t timeout = hw->eeprom.word_size + 1;
  991. uint32_t swsm;
  992. DEBUGFUNC();
  993. if (hw->mac_type != e1000_80003es2lan && hw->mac_type != e1000_igb)
  994. return E1000_SUCCESS;
  995. while (timeout) {
  996. swsm = E1000_READ_REG(hw, SWSM);
  997. /* If SMBI bit cleared, it is now set and we hold
  998. * the semaphore */
  999. if (!(swsm & E1000_SWSM_SMBI))
  1000. break;
  1001. mdelay(1);
  1002. timeout--;
  1003. }
  1004. if (!timeout) {
  1005. DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
  1006. return -E1000_ERR_RESET;
  1007. }
  1008. return E1000_SUCCESS;
  1009. }
  1010. #endif
  1011. /***************************************************************************
  1012. * This function clears HW semaphore bits.
  1013. *
  1014. * hw: Struct containing variables accessed by shared code
  1015. *
  1016. * returns: - None.
  1017. *
  1018. ***************************************************************************/
  1019. static void
  1020. e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
  1021. {
  1022. #ifndef CONFIG_E1000_NO_NVM
  1023. uint32_t swsm;
  1024. DEBUGFUNC();
  1025. if (!hw->eeprom_semaphore_present)
  1026. return;
  1027. swsm = E1000_READ_REG(hw, SWSM);
  1028. if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) {
  1029. /* Release both semaphores. */
  1030. swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
  1031. } else
  1032. swsm &= ~(E1000_SWSM_SWESMBI);
  1033. E1000_WRITE_REG(hw, SWSM, swsm);
  1034. #endif
  1035. }
  1036. /***************************************************************************
  1037. *
  1038. * Using the combination of SMBI and SWESMBI semaphore bits when resetting
  1039. * adapter or Eeprom access.
  1040. *
  1041. * hw: Struct containing variables accessed by shared code
  1042. *
  1043. * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
  1044. * E1000_SUCCESS at any other case.
  1045. *
  1046. ***************************************************************************/
  1047. static int32_t
  1048. e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
  1049. {
  1050. #ifndef CONFIG_E1000_NO_NVM
  1051. int32_t timeout;
  1052. uint32_t swsm;
  1053. DEBUGFUNC();
  1054. if (!hw->eeprom_semaphore_present)
  1055. return E1000_SUCCESS;
  1056. if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) {
  1057. /* Get the SW semaphore. */
  1058. if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
  1059. return -E1000_ERR_EEPROM;
  1060. }
  1061. /* Get the FW semaphore. */
  1062. timeout = hw->eeprom.word_size + 1;
  1063. while (timeout) {
  1064. swsm = E1000_READ_REG(hw, SWSM);
  1065. swsm |= E1000_SWSM_SWESMBI;
  1066. E1000_WRITE_REG(hw, SWSM, swsm);
  1067. /* if we managed to set the bit we got the semaphore. */
  1068. swsm = E1000_READ_REG(hw, SWSM);
  1069. if (swsm & E1000_SWSM_SWESMBI)
  1070. break;
  1071. udelay(50);
  1072. timeout--;
  1073. }
  1074. if (!timeout) {
  1075. /* Release semaphores */
  1076. e1000_put_hw_eeprom_semaphore(hw);
  1077. DEBUGOUT("Driver can't access the Eeprom - "
  1078. "SWESMBI bit is set.\n");
  1079. return -E1000_ERR_EEPROM;
  1080. }
  1081. #endif
  1082. return E1000_SUCCESS;
  1083. }
  1084. /* Take ownership of the PHY */
  1085. static int32_t
  1086. e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
  1087. {
  1088. uint32_t swfw_sync = 0;
  1089. uint32_t swmask = mask;
  1090. uint32_t fwmask = mask << 16;
  1091. int32_t timeout = 200;
  1092. DEBUGFUNC();
  1093. while (timeout) {
  1094. if (e1000_get_hw_eeprom_semaphore(hw))
  1095. return -E1000_ERR_SWFW_SYNC;
  1096. swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
  1097. if (!(swfw_sync & (fwmask | swmask)))
  1098. break;
  1099. /* firmware currently using resource (fwmask) */
  1100. /* or other software thread currently using resource (swmask) */
  1101. e1000_put_hw_eeprom_semaphore(hw);
  1102. mdelay(5);
  1103. timeout--;
  1104. }
  1105. if (!timeout) {
  1106. DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
  1107. return -E1000_ERR_SWFW_SYNC;
  1108. }
  1109. swfw_sync |= swmask;
  1110. E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
  1111. e1000_put_hw_eeprom_semaphore(hw);
  1112. return E1000_SUCCESS;
  1113. }
  1114. static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
  1115. {
  1116. uint32_t swfw_sync = 0;
  1117. DEBUGFUNC();
  1118. while (e1000_get_hw_eeprom_semaphore(hw))
  1119. ; /* Empty */
  1120. swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
  1121. swfw_sync &= ~mask;
  1122. E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
  1123. e1000_put_hw_eeprom_semaphore(hw);
  1124. }
  1125. static bool e1000_is_second_port(struct e1000_hw *hw)
  1126. {
  1127. switch (hw->mac_type) {
  1128. case e1000_80003es2lan:
  1129. case e1000_82546:
  1130. case e1000_82571:
  1131. if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
  1132. return true;
  1133. /* Fallthrough */
  1134. default:
  1135. return false;
  1136. }
  1137. }
  1138. #ifndef CONFIG_E1000_NO_NVM
  1139. /******************************************************************************
  1140. * Reads the adapter's MAC address from the EEPROM
  1141. *
  1142. * hw - Struct containing variables accessed by shared code
  1143. * enetaddr - buffering where the MAC address will be stored
  1144. *****************************************************************************/
  1145. static int e1000_read_mac_addr_from_eeprom(struct e1000_hw *hw,
  1146. unsigned char enetaddr[6])
  1147. {
  1148. uint16_t offset;
  1149. uint16_t eeprom_data;
  1150. int i;
  1151. for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
  1152. offset = i >> 1;
  1153. if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
  1154. DEBUGOUT("EEPROM Read Error\n");
  1155. return -E1000_ERR_EEPROM;
  1156. }
  1157. enetaddr[i] = eeprom_data & 0xff;
  1158. enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
  1159. }
  1160. return 0;
  1161. }
  1162. /******************************************************************************
  1163. * Reads the adapter's MAC address from the RAL/RAH registers
  1164. *
  1165. * hw - Struct containing variables accessed by shared code
  1166. * enetaddr - buffering where the MAC address will be stored
  1167. *****************************************************************************/
  1168. static int e1000_read_mac_addr_from_regs(struct e1000_hw *hw,
  1169. unsigned char enetaddr[6])
  1170. {
  1171. uint16_t offset, tmp;
  1172. uint32_t reg_data = 0;
  1173. int i;
  1174. if (hw->mac_type != e1000_igb)
  1175. return -E1000_ERR_MAC_TYPE;
  1176. for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
  1177. offset = i >> 1;
  1178. if (offset == 0)
  1179. reg_data = E1000_READ_REG_ARRAY(hw, RA, 0);
  1180. else if (offset == 1)
  1181. reg_data >>= 16;
  1182. else if (offset == 2)
  1183. reg_data = E1000_READ_REG_ARRAY(hw, RA, 1);
  1184. tmp = reg_data & 0xffff;
  1185. enetaddr[i] = tmp & 0xff;
  1186. enetaddr[i + 1] = (tmp >> 8) & 0xff;
  1187. }
  1188. return 0;
  1189. }
  1190. /******************************************************************************
  1191. * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
  1192. * second function of dual function devices
  1193. *
  1194. * hw - Struct containing variables accessed by shared code
  1195. * enetaddr - buffering where the MAC address will be stored
  1196. *****************************************************************************/
  1197. static int e1000_read_mac_addr(struct e1000_hw *hw, unsigned char enetaddr[6])
  1198. {
  1199. int ret_val;
  1200. if (hw->mac_type == e1000_igb) {
  1201. /* i210 preloads MAC address into RAL/RAH registers */
  1202. ret_val = e1000_read_mac_addr_from_regs(hw, enetaddr);
  1203. } else {
  1204. ret_val = e1000_read_mac_addr_from_eeprom(hw, enetaddr);
  1205. }
  1206. if (ret_val)
  1207. return ret_val;
  1208. /* Invert the last bit if this is the second device */
  1209. if (e1000_is_second_port(hw))
  1210. enetaddr[5] ^= 1;
  1211. return 0;
  1212. }
  1213. #endif
  1214. /******************************************************************************
  1215. * Initializes receive address filters.
  1216. *
  1217. * hw - Struct containing variables accessed by shared code
  1218. *
  1219. * Places the MAC address in receive address register 0 and clears the rest
  1220. * of the receive addresss registers. Clears the multicast table. Assumes
  1221. * the receiver is in reset when the routine is called.
  1222. *****************************************************************************/
  1223. static void
  1224. e1000_init_rx_addrs(struct e1000_hw *hw, unsigned char enetaddr[6])
  1225. {
  1226. uint32_t i;
  1227. uint32_t addr_low;
  1228. uint32_t addr_high;
  1229. DEBUGFUNC();
  1230. /* Setup the receive address. */
  1231. DEBUGOUT("Programming MAC Address into RAR[0]\n");
  1232. addr_low = (enetaddr[0] |
  1233. (enetaddr[1] << 8) |
  1234. (enetaddr[2] << 16) | (enetaddr[3] << 24));
  1235. addr_high = (enetaddr[4] | (enetaddr[5] << 8) | E1000_RAH_AV);
  1236. E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
  1237. E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
  1238. /* Zero out the other 15 receive addresses. */
  1239. DEBUGOUT("Clearing RAR[1-15]\n");
  1240. for (i = 1; i < E1000_RAR_ENTRIES; i++) {
  1241. E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
  1242. E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
  1243. }
  1244. }
  1245. /******************************************************************************
  1246. * Clears the VLAN filer table
  1247. *
  1248. * hw - Struct containing variables accessed by shared code
  1249. *****************************************************************************/
  1250. static void
  1251. e1000_clear_vfta(struct e1000_hw *hw)
  1252. {
  1253. uint32_t offset;
  1254. for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
  1255. E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
  1256. }
  1257. /******************************************************************************
  1258. * Set the mac type member in the hw struct.
  1259. *
  1260. * hw - Struct containing variables accessed by shared code
  1261. *****************************************************************************/
  1262. int32_t
  1263. e1000_set_mac_type(struct e1000_hw *hw)
  1264. {
  1265. DEBUGFUNC();
  1266. switch (hw->device_id) {
  1267. case E1000_DEV_ID_82542:
  1268. switch (hw->revision_id) {
  1269. case E1000_82542_2_0_REV_ID:
  1270. hw->mac_type = e1000_82542_rev2_0;
  1271. break;
  1272. case E1000_82542_2_1_REV_ID:
  1273. hw->mac_type = e1000_82542_rev2_1;
  1274. break;
  1275. default:
  1276. /* Invalid 82542 revision ID */
  1277. return -E1000_ERR_MAC_TYPE;
  1278. }
  1279. break;
  1280. case E1000_DEV_ID_82543GC_FIBER:
  1281. case E1000_DEV_ID_82543GC_COPPER:
  1282. hw->mac_type = e1000_82543;
  1283. break;
  1284. case E1000_DEV_ID_82544EI_COPPER:
  1285. case E1000_DEV_ID_82544EI_FIBER:
  1286. case E1000_DEV_ID_82544GC_COPPER:
  1287. case E1000_DEV_ID_82544GC_LOM:
  1288. hw->mac_type = e1000_82544;
  1289. break;
  1290. case E1000_DEV_ID_82540EM:
  1291. case E1000_DEV_ID_82540EM_LOM:
  1292. case E1000_DEV_ID_82540EP:
  1293. case E1000_DEV_ID_82540EP_LOM:
  1294. case E1000_DEV_ID_82540EP_LP:
  1295. hw->mac_type = e1000_82540;
  1296. break;
  1297. case E1000_DEV_ID_82545EM_COPPER:
  1298. case E1000_DEV_ID_82545EM_FIBER:
  1299. hw->mac_type = e1000_82545;
  1300. break;
  1301. case E1000_DEV_ID_82545GM_COPPER:
  1302. case E1000_DEV_ID_82545GM_FIBER:
  1303. case E1000_DEV_ID_82545GM_SERDES:
  1304. hw->mac_type = e1000_82545_rev_3;
  1305. break;
  1306. case E1000_DEV_ID_82546EB_COPPER:
  1307. case E1000_DEV_ID_82546EB_FIBER:
  1308. case E1000_DEV_ID_82546EB_QUAD_COPPER:
  1309. hw->mac_type = e1000_82546;
  1310. break;
  1311. case E1000_DEV_ID_82546GB_COPPER:
  1312. case E1000_DEV_ID_82546GB_FIBER:
  1313. case E1000_DEV_ID_82546GB_SERDES:
  1314. case E1000_DEV_ID_82546GB_PCIE:
  1315. case E1000_DEV_ID_82546GB_QUAD_COPPER:
  1316. case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
  1317. hw->mac_type = e1000_82546_rev_3;
  1318. break;
  1319. case E1000_DEV_ID_82541EI:
  1320. case E1000_DEV_ID_82541EI_MOBILE:
  1321. case E1000_DEV_ID_82541ER_LOM:
  1322. hw->mac_type = e1000_82541;
  1323. break;
  1324. case E1000_DEV_ID_82541ER:
  1325. case E1000_DEV_ID_82541GI:
  1326. case E1000_DEV_ID_82541GI_LF:
  1327. case E1000_DEV_ID_82541GI_MOBILE:
  1328. hw->mac_type = e1000_82541_rev_2;
  1329. break;
  1330. case E1000_DEV_ID_82547EI:
  1331. case E1000_DEV_ID_82547EI_MOBILE:
  1332. hw->mac_type = e1000_82547;
  1333. break;
  1334. case E1000_DEV_ID_82547GI:
  1335. hw->mac_type = e1000_82547_rev_2;
  1336. break;
  1337. case E1000_DEV_ID_82571EB_COPPER:
  1338. case E1000_DEV_ID_82571EB_FIBER:
  1339. case E1000_DEV_ID_82571EB_SERDES:
  1340. case E1000_DEV_ID_82571EB_SERDES_DUAL:
  1341. case E1000_DEV_ID_82571EB_SERDES_QUAD:
  1342. case E1000_DEV_ID_82571EB_QUAD_COPPER:
  1343. case E1000_DEV_ID_82571PT_QUAD_COPPER:
  1344. case E1000_DEV_ID_82571EB_QUAD_FIBER:
  1345. case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
  1346. hw->mac_type = e1000_82571;
  1347. break;
  1348. case E1000_DEV_ID_82572EI_COPPER:
  1349. case E1000_DEV_ID_82572EI_FIBER:
  1350. case E1000_DEV_ID_82572EI_SERDES:
  1351. case E1000_DEV_ID_82572EI:
  1352. hw->mac_type = e1000_82572;
  1353. break;
  1354. case E1000_DEV_ID_82573E:
  1355. case E1000_DEV_ID_82573E_IAMT:
  1356. case E1000_DEV_ID_82573L:
  1357. hw->mac_type = e1000_82573;
  1358. break;
  1359. case E1000_DEV_ID_82574L:
  1360. hw->mac_type = e1000_82574;
  1361. break;
  1362. case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
  1363. case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
  1364. case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
  1365. case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
  1366. hw->mac_type = e1000_80003es2lan;
  1367. break;
  1368. case E1000_DEV_ID_ICH8_IGP_M_AMT:
  1369. case E1000_DEV_ID_ICH8_IGP_AMT:
  1370. case E1000_DEV_ID_ICH8_IGP_C:
  1371. case E1000_DEV_ID_ICH8_IFE:
  1372. case E1000_DEV_ID_ICH8_IFE_GT:
  1373. case E1000_DEV_ID_ICH8_IFE_G:
  1374. case E1000_DEV_ID_ICH8_IGP_M:
  1375. hw->mac_type = e1000_ich8lan;
  1376. break;
  1377. case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED:
  1378. case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED:
  1379. case PCI_DEVICE_ID_INTEL_I210_COPPER:
  1380. case PCI_DEVICE_ID_INTEL_I211_COPPER:
  1381. case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS:
  1382. case PCI_DEVICE_ID_INTEL_I210_SERDES:
  1383. case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS:
  1384. case PCI_DEVICE_ID_INTEL_I210_1000BASEKX:
  1385. hw->mac_type = e1000_igb;
  1386. break;
  1387. default:
  1388. /* Should never have loaded on this device */
  1389. return -E1000_ERR_MAC_TYPE;
  1390. }
  1391. return E1000_SUCCESS;
  1392. }
  1393. /******************************************************************************
  1394. * Reset the transmit and receive units; mask and clear all interrupts.
  1395. *
  1396. * hw - Struct containing variables accessed by shared code
  1397. *****************************************************************************/
  1398. void
  1399. e1000_reset_hw(struct e1000_hw *hw)
  1400. {
  1401. uint32_t ctrl;
  1402. uint32_t ctrl_ext;
  1403. uint32_t manc;
  1404. uint32_t pba = 0;
  1405. uint32_t reg;
  1406. DEBUGFUNC();
  1407. /* get the correct pba value for both PCI and PCIe*/
  1408. if (hw->mac_type < e1000_82571)
  1409. pba = E1000_DEFAULT_PCI_PBA;
  1410. else
  1411. pba = E1000_DEFAULT_PCIE_PBA;
  1412. /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
  1413. if (hw->mac_type == e1000_82542_rev2_0) {
  1414. DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
  1415. #ifdef CONFIG_DM_ETH
  1416. dm_pci_write_config16(hw->pdev, PCI_COMMAND,
  1417. hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
  1418. #else
  1419. pci_write_config_word(hw->pdev, PCI_COMMAND,
  1420. hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
  1421. #endif
  1422. }
  1423. /* Clear interrupt mask to stop board from generating interrupts */
  1424. DEBUGOUT("Masking off all interrupts\n");
  1425. if (hw->mac_type == e1000_igb)
  1426. E1000_WRITE_REG(hw, I210_IAM, 0);
  1427. E1000_WRITE_REG(hw, IMC, 0xffffffff);
  1428. /* Disable the Transmit and Receive units. Then delay to allow
  1429. * any pending transactions to complete before we hit the MAC with
  1430. * the global reset.
  1431. */
  1432. E1000_WRITE_REG(hw, RCTL, 0);
  1433. E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
  1434. E1000_WRITE_FLUSH(hw);
  1435. /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
  1436. hw->tbi_compatibility_on = false;
  1437. /* Delay to allow any outstanding PCI transactions to complete before
  1438. * resetting the device
  1439. */
  1440. mdelay(10);
  1441. /* Issue a global reset to the MAC. This will reset the chip's
  1442. * transmit, receive, DMA, and link units. It will not effect
  1443. * the current PCI configuration. The global reset bit is self-
  1444. * clearing, and should clear within a microsecond.
  1445. */
  1446. DEBUGOUT("Issuing a global reset to MAC\n");
  1447. ctrl = E1000_READ_REG(hw, CTRL);
  1448. E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
  1449. /* Force a reload from the EEPROM if necessary */
  1450. if (hw->mac_type == e1000_igb) {
  1451. mdelay(20);
  1452. reg = E1000_READ_REG(hw, STATUS);
  1453. if (reg & E1000_STATUS_PF_RST_DONE)
  1454. DEBUGOUT("PF OK\n");
  1455. reg = E1000_READ_REG(hw, I210_EECD);
  1456. if (reg & E1000_EECD_AUTO_RD)
  1457. DEBUGOUT("EEC OK\n");
  1458. } else if (hw->mac_type < e1000_82540) {
  1459. /* Wait for reset to complete */
  1460. udelay(10);
  1461. ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  1462. ctrl_ext |= E1000_CTRL_EXT_EE_RST;
  1463. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  1464. E1000_WRITE_FLUSH(hw);
  1465. /* Wait for EEPROM reload */
  1466. mdelay(2);
  1467. } else {
  1468. /* Wait for EEPROM reload (it happens automatically) */
  1469. mdelay(4);
  1470. /* Dissable HW ARPs on ASF enabled adapters */
  1471. manc = E1000_READ_REG(hw, MANC);
  1472. manc &= ~(E1000_MANC_ARP_EN);
  1473. E1000_WRITE_REG(hw, MANC, manc);
  1474. }
  1475. /* Clear interrupt mask to stop board from generating interrupts */
  1476. DEBUGOUT("Masking off all interrupts\n");
  1477. if (hw->mac_type == e1000_igb)
  1478. E1000_WRITE_REG(hw, I210_IAM, 0);
  1479. E1000_WRITE_REG(hw, IMC, 0xffffffff);
  1480. /* Clear any pending interrupt events. */
  1481. E1000_READ_REG(hw, ICR);
  1482. /* If MWI was previously enabled, reenable it. */
  1483. if (hw->mac_type == e1000_82542_rev2_0) {
  1484. #ifdef CONFIG_DM_ETH
  1485. dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
  1486. #else
  1487. pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
  1488. #endif
  1489. }
  1490. if (hw->mac_type != e1000_igb)
  1491. E1000_WRITE_REG(hw, PBA, pba);
  1492. }
  1493. /******************************************************************************
  1494. *
  1495. * Initialize a number of hardware-dependent bits
  1496. *
  1497. * hw: Struct containing variables accessed by shared code
  1498. *
  1499. * This function contains hardware limitation workarounds for PCI-E adapters
  1500. *
  1501. *****************************************************************************/
  1502. static void
  1503. e1000_initialize_hardware_bits(struct e1000_hw *hw)
  1504. {
  1505. if ((hw->mac_type >= e1000_82571) &&
  1506. (!hw->initialize_hw_bits_disable)) {
  1507. /* Settings common to all PCI-express silicon */
  1508. uint32_t reg_ctrl, reg_ctrl_ext;
  1509. uint32_t reg_tarc0, reg_tarc1;
  1510. uint32_t reg_tctl;
  1511. uint32_t reg_txdctl, reg_txdctl1;
  1512. /* link autonegotiation/sync workarounds */
  1513. reg_tarc0 = E1000_READ_REG(hw, TARC0);
  1514. reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
  1515. /* Enable not-done TX descriptor counting */
  1516. reg_txdctl = E1000_READ_REG(hw, TXDCTL);
  1517. reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
  1518. E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
  1519. reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
  1520. reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
  1521. E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
  1522. switch (hw->mac_type) {
  1523. case e1000_igb: /* IGB is cool */
  1524. return;
  1525. case e1000_82571:
  1526. case e1000_82572:
  1527. /* Clear PHY TX compatible mode bits */
  1528. reg_tarc1 = E1000_READ_REG(hw, TARC1);
  1529. reg_tarc1 &= ~((1 << 30)|(1 << 29));
  1530. /* link autonegotiation/sync workarounds */
  1531. reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));
  1532. /* TX ring control fixes */
  1533. reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));
  1534. /* Multiple read bit is reversed polarity */
  1535. reg_tctl = E1000_READ_REG(hw, TCTL);
  1536. if (reg_tctl & E1000_TCTL_MULR)
  1537. reg_tarc1 &= ~(1 << 28);
  1538. else
  1539. reg_tarc1 |= (1 << 28);
  1540. E1000_WRITE_REG(hw, TARC1, reg_tarc1);
  1541. break;
  1542. case e1000_82573:
  1543. case e1000_82574:
  1544. reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  1545. reg_ctrl_ext &= ~(1 << 23);
  1546. reg_ctrl_ext |= (1 << 22);
  1547. /* TX byte count fix */
  1548. reg_ctrl = E1000_READ_REG(hw, CTRL);
  1549. reg_ctrl &= ~(1 << 29);
  1550. E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
  1551. E1000_WRITE_REG(hw, CTRL, reg_ctrl);
  1552. break;
  1553. case e1000_80003es2lan:
  1554. /* improve small packet performace for fiber/serdes */
  1555. if ((hw->media_type == e1000_media_type_fiber)
  1556. || (hw->media_type ==
  1557. e1000_media_type_internal_serdes)) {
  1558. reg_tarc0 &= ~(1 << 20);
  1559. }
  1560. /* Multiple read bit is reversed polarity */
  1561. reg_tctl = E1000_READ_REG(hw, TCTL);
  1562. reg_tarc1 = E1000_READ_REG(hw, TARC1);
  1563. if (reg_tctl & E1000_TCTL_MULR)
  1564. reg_tarc1 &= ~(1 << 28);
  1565. else
  1566. reg_tarc1 |= (1 << 28);
  1567. E1000_WRITE_REG(hw, TARC1, reg_tarc1);
  1568. break;
  1569. case e1000_ich8lan:
  1570. /* Reduce concurrent DMA requests to 3 from 4 */
  1571. if ((hw->revision_id < 3) ||
  1572. ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
  1573. (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
  1574. reg_tarc0 |= ((1 << 29)|(1 << 28));
  1575. reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  1576. reg_ctrl_ext |= (1 << 22);
  1577. E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
  1578. /* workaround TX hang with TSO=on */
  1579. reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));
  1580. /* Multiple read bit is reversed polarity */
  1581. reg_tctl = E1000_READ_REG(hw, TCTL);
  1582. reg_tarc1 = E1000_READ_REG(hw, TARC1);
  1583. if (reg_tctl & E1000_TCTL_MULR)
  1584. reg_tarc1 &= ~(1 << 28);
  1585. else
  1586. reg_tarc1 |= (1 << 28);
  1587. /* workaround TX hang with TSO=on */
  1588. reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));
  1589. E1000_WRITE_REG(hw, TARC1, reg_tarc1);
  1590. break;
  1591. default:
  1592. break;
  1593. }
  1594. E1000_WRITE_REG(hw, TARC0, reg_tarc0);
  1595. }
  1596. }
  1597. /******************************************************************************
  1598. * Performs basic configuration of the adapter.
  1599. *
  1600. * hw - Struct containing variables accessed by shared code
  1601. *
  1602. * Assumes that the controller has previously been reset and is in a
  1603. * post-reset uninitialized state. Initializes the receive address registers,
  1604. * multicast table, and VLAN filter table. Calls routines to setup link
  1605. * configuration and flow control settings. Clears all on-chip counters. Leaves
  1606. * the transmit and receive units disabled and uninitialized.
  1607. *****************************************************************************/
  1608. static int
  1609. e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6])
  1610. {
  1611. uint32_t ctrl;
  1612. uint32_t i;
  1613. int32_t ret_val;
  1614. uint16_t pcix_cmd_word;
  1615. uint16_t pcix_stat_hi_word;
  1616. uint16_t cmd_mmrbc;
  1617. uint16_t stat_mmrbc;
  1618. uint32_t mta_size;
  1619. uint32_t reg_data;
  1620. uint32_t ctrl_ext;
  1621. DEBUGFUNC();
  1622. /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
  1623. if ((hw->mac_type == e1000_ich8lan) &&
  1624. ((hw->revision_id < 3) ||
  1625. ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
  1626. (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
  1627. reg_data = E1000_READ_REG(hw, STATUS);
  1628. reg_data &= ~0x80000000;
  1629. E1000_WRITE_REG(hw, STATUS, reg_data);
  1630. }
  1631. /* Do not need initialize Identification LED */
  1632. /* Set the media type and TBI compatibility */
  1633. e1000_set_media_type(hw);
  1634. /* Must be called after e1000_set_media_type
  1635. * because media_type is used */
  1636. e1000_initialize_hardware_bits(hw);
  1637. /* Disabling VLAN filtering. */
  1638. DEBUGOUT("Initializing the IEEE VLAN\n");
  1639. /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
  1640. if (hw->mac_type != e1000_ich8lan) {
  1641. if (hw->mac_type < e1000_82545_rev_3)
  1642. E1000_WRITE_REG(hw, VET, 0);
  1643. e1000_clear_vfta(hw);
  1644. }
  1645. /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
  1646. if (hw->mac_type == e1000_82542_rev2_0) {
  1647. DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
  1648. #ifdef CONFIG_DM_ETH
  1649. dm_pci_write_config16(hw->pdev, PCI_COMMAND,
  1650. hw->
  1651. pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
  1652. #else
  1653. pci_write_config_word(hw->pdev, PCI_COMMAND,
  1654. hw->
  1655. pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
  1656. #endif
  1657. E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
  1658. E1000_WRITE_FLUSH(hw);
  1659. mdelay(5);
  1660. }
  1661. /* Setup the receive address. This involves initializing all of the Receive
  1662. * Address Registers (RARs 0 - 15).
  1663. */
  1664. e1000_init_rx_addrs(hw, enetaddr);
  1665. /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
  1666. if (hw->mac_type == e1000_82542_rev2_0) {
  1667. E1000_WRITE_REG(hw, RCTL, 0);
  1668. E1000_WRITE_FLUSH(hw);
  1669. mdelay(1);
  1670. #ifdef CONFIG_DM_ETH
  1671. dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
  1672. #else
  1673. pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
  1674. #endif
  1675. }
  1676. /* Zero out the Multicast HASH table */
  1677. DEBUGOUT("Zeroing the MTA\n");
  1678. mta_size = E1000_MC_TBL_SIZE;
  1679. if (hw->mac_type == e1000_ich8lan)
  1680. mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
  1681. for (i = 0; i < mta_size; i++) {
  1682. E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
  1683. /* use write flush to prevent Memory Write Block (MWB) from
  1684. * occuring when accessing our register space */
  1685. E1000_WRITE_FLUSH(hw);
  1686. }
  1687. switch (hw->mac_type) {
  1688. case e1000_82545_rev_3:
  1689. case e1000_82546_rev_3:
  1690. case e1000_igb:
  1691. break;
  1692. default:
  1693. /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
  1694. if (hw->bus_type == e1000_bus_type_pcix) {
  1695. #ifdef CONFIG_DM_ETH
  1696. dm_pci_read_config16(hw->pdev, PCIX_COMMAND_REGISTER,
  1697. &pcix_cmd_word);
  1698. dm_pci_read_config16(hw->pdev, PCIX_STATUS_REGISTER_HI,
  1699. &pcix_stat_hi_word);
  1700. #else
  1701. pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
  1702. &pcix_cmd_word);
  1703. pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
  1704. &pcix_stat_hi_word);
  1705. #endif
  1706. cmd_mmrbc =
  1707. (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
  1708. PCIX_COMMAND_MMRBC_SHIFT;
  1709. stat_mmrbc =
  1710. (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
  1711. PCIX_STATUS_HI_MMRBC_SHIFT;
  1712. if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
  1713. stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
  1714. if (cmd_mmrbc > stat_mmrbc) {
  1715. pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
  1716. pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
  1717. #ifdef CONFIG_DM_ETH
  1718. dm_pci_write_config16(hw->pdev, PCIX_COMMAND_REGISTER,
  1719. pcix_cmd_word);
  1720. #else
  1721. pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
  1722. pcix_cmd_word);
  1723. #endif
  1724. }
  1725. }
  1726. break;
  1727. }
  1728. /* More time needed for PHY to initialize */
  1729. if (hw->mac_type == e1000_ich8lan)
  1730. mdelay(15);
  1731. if (hw->mac_type == e1000_igb)
  1732. mdelay(15);
  1733. /* Call a subroutine to configure the link and setup flow control. */
  1734. ret_val = e1000_setup_link(hw);
  1735. /* Set the transmit descriptor write-back policy */
  1736. if (hw->mac_type > e1000_82544) {
  1737. ctrl = E1000_READ_REG(hw, TXDCTL);
  1738. ctrl =
  1739. (ctrl & ~E1000_TXDCTL_WTHRESH) |
  1740. E1000_TXDCTL_FULL_TX_DESC_WB;
  1741. E1000_WRITE_REG(hw, TXDCTL, ctrl);
  1742. }
  1743. /* Set the receive descriptor write back policy */
  1744. if (hw->mac_type >= e1000_82571) {
  1745. ctrl = E1000_READ_REG(hw, RXDCTL);
  1746. ctrl =
  1747. (ctrl & ~E1000_RXDCTL_WTHRESH) |
  1748. E1000_RXDCTL_FULL_RX_DESC_WB;
  1749. E1000_WRITE_REG(hw, RXDCTL, ctrl);
  1750. }
  1751. switch (hw->mac_type) {
  1752. default:
  1753. break;
  1754. case e1000_80003es2lan:
  1755. /* Enable retransmit on late collisions */
  1756. reg_data = E1000_READ_REG(hw, TCTL);
  1757. reg_data |= E1000_TCTL_RTLC;
  1758. E1000_WRITE_REG(hw, TCTL, reg_data);
  1759. /* Configure Gigabit Carry Extend Padding */
  1760. reg_data = E1000_READ_REG(hw, TCTL_EXT);
  1761. reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
  1762. reg_data |= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
  1763. E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
  1764. /* Configure Transmit Inter-Packet Gap */
  1765. reg_data = E1000_READ_REG(hw, TIPG);
  1766. reg_data &= ~E1000_TIPG_IPGT_MASK;
  1767. reg_data |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
  1768. E1000_WRITE_REG(hw, TIPG, reg_data);
  1769. reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
  1770. reg_data &= ~0x00100000;
  1771. E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
  1772. /* Fall through */
  1773. case e1000_82571:
  1774. case e1000_82572:
  1775. case e1000_ich8lan:
  1776. ctrl = E1000_READ_REG(hw, TXDCTL1);
  1777. ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH)
  1778. | E1000_TXDCTL_FULL_TX_DESC_WB;
  1779. E1000_WRITE_REG(hw, TXDCTL1, ctrl);
  1780. break;
  1781. case e1000_82573:
  1782. case e1000_82574:
  1783. reg_data = E1000_READ_REG(hw, GCR);
  1784. reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
  1785. E1000_WRITE_REG(hw, GCR, reg_data);
  1786. case e1000_igb:
  1787. break;
  1788. }
  1789. if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER ||
  1790. hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
  1791. ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  1792. /* Relaxed ordering must be disabled to avoid a parity
  1793. * error crash in a PCI slot. */
  1794. ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
  1795. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  1796. }
  1797. return ret_val;
  1798. }
  1799. /******************************************************************************
  1800. * Configures flow control and link settings.
  1801. *
  1802. * hw - Struct containing variables accessed by shared code
  1803. *
  1804. * Determines which flow control settings to use. Calls the apropriate media-
  1805. * specific link configuration function. Configures the flow control settings.
  1806. * Assuming the adapter has a valid link partner, a valid link should be
  1807. * established. Assumes the hardware has previously been reset and the
  1808. * transmitter and receiver are not enabled.
  1809. *****************************************************************************/
  1810. static int
  1811. e1000_setup_link(struct e1000_hw *hw)
  1812. {
  1813. int32_t ret_val;
  1814. #ifndef CONFIG_E1000_NO_NVM
  1815. uint32_t ctrl_ext;
  1816. uint16_t eeprom_data;
  1817. #endif
  1818. DEBUGFUNC();
  1819. /* In the case of the phy reset being blocked, we already have a link.
  1820. * We do not have to set it up again. */
  1821. if (e1000_check_phy_reset_block(hw))
  1822. return E1000_SUCCESS;
  1823. #ifndef CONFIG_E1000_NO_NVM
  1824. /* Read and store word 0x0F of the EEPROM. This word contains bits
  1825. * that determine the hardware's default PAUSE (flow control) mode,
  1826. * a bit that determines whether the HW defaults to enabling or
  1827. * disabling auto-negotiation, and the direction of the
  1828. * SW defined pins. If there is no SW over-ride of the flow
  1829. * control setting, then the variable hw->fc will
  1830. * be initialized based on a value in the EEPROM.
  1831. */
  1832. if (e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1,
  1833. &eeprom_data) < 0) {
  1834. DEBUGOUT("EEPROM Read Error\n");
  1835. return -E1000_ERR_EEPROM;
  1836. }
  1837. #endif
  1838. if (hw->fc == e1000_fc_default) {
  1839. switch (hw->mac_type) {
  1840. case e1000_ich8lan:
  1841. case e1000_82573:
  1842. case e1000_82574:
  1843. case e1000_igb:
  1844. hw->fc = e1000_fc_full;
  1845. break;
  1846. default:
  1847. #ifndef CONFIG_E1000_NO_NVM
  1848. ret_val = e1000_read_eeprom(hw,
  1849. EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
  1850. if (ret_val) {
  1851. DEBUGOUT("EEPROM Read Error\n");
  1852. return -E1000_ERR_EEPROM;
  1853. }
  1854. if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
  1855. hw->fc = e1000_fc_none;
  1856. else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
  1857. EEPROM_WORD0F_ASM_DIR)
  1858. hw->fc = e1000_fc_tx_pause;
  1859. else
  1860. #endif
  1861. hw->fc = e1000_fc_full;
  1862. break;
  1863. }
  1864. }
  1865. /* We want to save off the original Flow Control configuration just
  1866. * in case we get disconnected and then reconnected into a different
  1867. * hub or switch with different Flow Control capabilities.
  1868. */
  1869. if (hw->mac_type == e1000_82542_rev2_0)
  1870. hw->fc &= (~e1000_fc_tx_pause);
  1871. if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
  1872. hw->fc &= (~e1000_fc_rx_pause);
  1873. hw->original_fc = hw->fc;
  1874. DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc);
  1875. #ifndef CONFIG_E1000_NO_NVM
  1876. /* Take the 4 bits from EEPROM word 0x0F that determine the initial
  1877. * polarity value for the SW controlled pins, and setup the
  1878. * Extended Device Control reg with that info.
  1879. * This is needed because one of the SW controlled pins is used for
  1880. * signal detection. So this should be done before e1000_setup_pcs_link()
  1881. * or e1000_phy_setup() is called.
  1882. */
  1883. if (hw->mac_type == e1000_82543) {
  1884. ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
  1885. SWDPIO__EXT_SHIFT);
  1886. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  1887. }
  1888. #endif
  1889. /* Call the necessary subroutine to configure the link. */
  1890. ret_val = (hw->media_type == e1000_media_type_fiber) ?
  1891. e1000_setup_fiber_link(hw) : e1000_setup_copper_link(hw);
  1892. if (ret_val < 0) {
  1893. return ret_val;
  1894. }
  1895. /* Initialize the flow control address, type, and PAUSE timer
  1896. * registers to their default values. This is done even if flow
  1897. * control is disabled, because it does not hurt anything to
  1898. * initialize these registers.
  1899. */
  1900. DEBUGOUT("Initializing the Flow Control address, type"
  1901. "and timer regs\n");
  1902. /* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
  1903. if (hw->mac_type != e1000_ich8lan) {
  1904. E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
  1905. E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
  1906. E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
  1907. }
  1908. E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
  1909. /* Set the flow control receive threshold registers. Normally,
  1910. * these registers will be set to a default threshold that may be
  1911. * adjusted later by the driver's runtime code. However, if the
  1912. * ability to transmit pause frames in not enabled, then these
  1913. * registers will be set to 0.
  1914. */
  1915. if (!(hw->fc & e1000_fc_tx_pause)) {
  1916. E1000_WRITE_REG(hw, FCRTL, 0);
  1917. E1000_WRITE_REG(hw, FCRTH, 0);
  1918. } else {
  1919. /* We need to set up the Receive Threshold high and low water marks
  1920. * as well as (optionally) enabling the transmission of XON frames.
  1921. */
  1922. if (hw->fc_send_xon) {
  1923. E1000_WRITE_REG(hw, FCRTL,
  1924. (hw->fc_low_water | E1000_FCRTL_XONE));
  1925. E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
  1926. } else {
  1927. E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
  1928. E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
  1929. }
  1930. }
  1931. return ret_val;
  1932. }
  1933. /******************************************************************************
  1934. * Sets up link for a fiber based adapter
  1935. *
  1936. * hw - Struct containing variables accessed by shared code
  1937. *
  1938. * Manipulates Physical Coding Sublayer functions in order to configure
  1939. * link. Assumes the hardware has been previously reset and the transmitter
  1940. * and receiver are not enabled.
  1941. *****************************************************************************/
  1942. static int
  1943. e1000_setup_fiber_link(struct e1000_hw *hw)
  1944. {
  1945. uint32_t ctrl;
  1946. uint32_t status;
  1947. uint32_t txcw = 0;
  1948. uint32_t i;
  1949. uint32_t signal;
  1950. int32_t ret_val;
  1951. DEBUGFUNC();
  1952. /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
  1953. * set when the optics detect a signal. On older adapters, it will be
  1954. * cleared when there is a signal
  1955. */
  1956. ctrl = E1000_READ_REG(hw, CTRL);
  1957. if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
  1958. signal = E1000_CTRL_SWDPIN1;
  1959. else
  1960. signal = 0;
  1961. printf("signal for %s is %x (ctrl %08x)!!!!\n", hw->name, signal,
  1962. ctrl);
  1963. /* Take the link out of reset */
  1964. ctrl &= ~(E1000_CTRL_LRST);
  1965. e1000_config_collision_dist(hw);
  1966. /* Check for a software override of the flow control settings, and setup
  1967. * the device accordingly. If auto-negotiation is enabled, then software
  1968. * will have to set the "PAUSE" bits to the correct value in the Tranmsit
  1969. * Config Word Register (TXCW) and re-start auto-negotiation. However, if
  1970. * auto-negotiation is disabled, then software will have to manually
  1971. * configure the two flow control enable bits in the CTRL register.
  1972. *
  1973. * The possible values of the "fc" parameter are:
  1974. * 0: Flow control is completely disabled
  1975. * 1: Rx flow control is enabled (we can receive pause frames, but
  1976. * not send pause frames).
  1977. * 2: Tx flow control is enabled (we can send pause frames but we do
  1978. * not support receiving pause frames).
  1979. * 3: Both Rx and TX flow control (symmetric) are enabled.
  1980. */
  1981. switch (hw->fc) {
  1982. case e1000_fc_none:
  1983. /* Flow control is completely disabled by a software over-ride. */
  1984. txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
  1985. break;
  1986. case e1000_fc_rx_pause:
  1987. /* RX Flow control is enabled and TX Flow control is disabled by a
  1988. * software over-ride. Since there really isn't a way to advertise
  1989. * that we are capable of RX Pause ONLY, we will advertise that we
  1990. * support both symmetric and asymmetric RX PAUSE. Later, we will
  1991. * disable the adapter's ability to send PAUSE frames.
  1992. */
  1993. txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
  1994. break;
  1995. case e1000_fc_tx_pause:
  1996. /* TX Flow control is enabled, and RX Flow control is disabled, by a
  1997. * software over-ride.
  1998. */
  1999. txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
  2000. break;
  2001. case e1000_fc_full:
  2002. /* Flow control (both RX and TX) is enabled by a software over-ride. */
  2003. txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
  2004. break;
  2005. default:
  2006. DEBUGOUT("Flow control param set incorrectly\n");
  2007. return -E1000_ERR_CONFIG;
  2008. break;
  2009. }
  2010. /* Since auto-negotiation is enabled, take the link out of reset (the link
  2011. * will be in reset, because we previously reset the chip). This will
  2012. * restart auto-negotiation. If auto-neogtiation is successful then the
  2013. * link-up status bit will be set and the flow control enable bits (RFCE
  2014. * and TFCE) will be set according to their negotiated value.
  2015. */
  2016. DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw);
  2017. E1000_WRITE_REG(hw, TXCW, txcw);
  2018. E1000_WRITE_REG(hw, CTRL, ctrl);
  2019. E1000_WRITE_FLUSH(hw);
  2020. hw->txcw = txcw;
  2021. mdelay(1);
  2022. /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
  2023. * indication in the Device Status Register. Time-out if a link isn't
  2024. * seen in 500 milliseconds seconds (Auto-negotiation should complete in
  2025. * less than 500 milliseconds even if the other end is doing it in SW).
  2026. */
  2027. if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
  2028. DEBUGOUT("Looking for Link\n");
  2029. for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
  2030. mdelay(10);
  2031. status = E1000_READ_REG(hw, STATUS);
  2032. if (status & E1000_STATUS_LU)
  2033. break;
  2034. }
  2035. if (i == (LINK_UP_TIMEOUT / 10)) {
  2036. /* AutoNeg failed to achieve a link, so we'll call
  2037. * e1000_check_for_link. This routine will force the link up if we
  2038. * detect a signal. This will allow us to communicate with
  2039. * non-autonegotiating link partners.
  2040. */
  2041. DEBUGOUT("Never got a valid link from auto-neg!!!\n");
  2042. hw->autoneg_failed = 1;
  2043. ret_val = e1000_check_for_link(hw);
  2044. if (ret_val < 0) {
  2045. DEBUGOUT("Error while checking for link\n");
  2046. return ret_val;
  2047. }
  2048. hw->autoneg_failed = 0;
  2049. } else {
  2050. hw->autoneg_failed = 0;
  2051. DEBUGOUT("Valid Link Found\n");
  2052. }
  2053. } else {
  2054. DEBUGOUT("No Signal Detected\n");
  2055. return -E1000_ERR_NOLINK;
  2056. }
  2057. return 0;
  2058. }
  2059. /******************************************************************************
  2060. * Make sure we have a valid PHY and change PHY mode before link setup.
  2061. *
  2062. * hw - Struct containing variables accessed by shared code
  2063. ******************************************************************************/
  2064. static int32_t
  2065. e1000_copper_link_preconfig(struct e1000_hw *hw)
  2066. {
  2067. uint32_t ctrl;
  2068. int32_t ret_val;
  2069. uint16_t phy_data;
  2070. DEBUGFUNC();
  2071. ctrl = E1000_READ_REG(hw, CTRL);
  2072. /* With 82543, we need to force speed and duplex on the MAC equal to what
  2073. * the PHY speed and duplex configuration is. In addition, we need to
  2074. * perform a hardware reset on the PHY to take it out of reset.
  2075. */
  2076. if (hw->mac_type > e1000_82543) {
  2077. ctrl |= E1000_CTRL_SLU;
  2078. ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
  2079. E1000_WRITE_REG(hw, CTRL, ctrl);
  2080. } else {
  2081. ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX
  2082. | E1000_CTRL_SLU);
  2083. E1000_WRITE_REG(hw, CTRL, ctrl);
  2084. ret_val = e1000_phy_hw_reset(hw);
  2085. if (ret_val)
  2086. return ret_val;
  2087. }
  2088. /* Make sure we have a valid PHY */
  2089. ret_val = e1000_detect_gig_phy(hw);
  2090. if (ret_val) {
  2091. DEBUGOUT("Error, did not detect valid phy.\n");
  2092. return ret_val;
  2093. }
  2094. DEBUGOUT("Phy ID = %x\n", hw->phy_id);
  2095. /* Set PHY to class A mode (if necessary) */
  2096. ret_val = e1000_set_phy_mode(hw);
  2097. if (ret_val)
  2098. return ret_val;
  2099. if ((hw->mac_type == e1000_82545_rev_3) ||
  2100. (hw->mac_type == e1000_82546_rev_3)) {
  2101. ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
  2102. &phy_data);
  2103. phy_data |= 0x00000008;
  2104. ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
  2105. phy_data);
  2106. }
  2107. if (hw->mac_type <= e1000_82543 ||
  2108. hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
  2109. hw->mac_type == e1000_82541_rev_2
  2110. || hw->mac_type == e1000_82547_rev_2)
  2111. hw->phy_reset_disable = false;
  2112. return E1000_SUCCESS;
  2113. }
  2114. /*****************************************************************************
  2115. *
  2116. * This function sets the lplu state according to the active flag. When
  2117. * activating lplu this function also disables smart speed and vise versa.
  2118. * lplu will not be activated unless the device autonegotiation advertisment
  2119. * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
  2120. * hw: Struct containing variables accessed by shared code
  2121. * active - true to enable lplu false to disable lplu.
  2122. *
  2123. * returns: - E1000_ERR_PHY if fail to read/write the PHY
  2124. * E1000_SUCCESS at any other case.
  2125. *
  2126. ****************************************************************************/
  2127. static int32_t
  2128. e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active)
  2129. {
  2130. uint32_t phy_ctrl = 0;
  2131. int32_t ret_val;
  2132. uint16_t phy_data;
  2133. DEBUGFUNC();
  2134. if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
  2135. && hw->phy_type != e1000_phy_igp_3)
  2136. return E1000_SUCCESS;
  2137. /* During driver activity LPLU should not be used or it will attain link
  2138. * from the lowest speeds starting from 10Mbps. The capability is used
  2139. * for Dx transitions and states */
  2140. if (hw->mac_type == e1000_82541_rev_2
  2141. || hw->mac_type == e1000_82547_rev_2) {
  2142. ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
  2143. &phy_data);
  2144. if (ret_val)
  2145. return ret_val;
  2146. } else if (hw->mac_type == e1000_ich8lan) {
  2147. /* MAC writes into PHY register based on the state transition
  2148. * and start auto-negotiation. SW driver can overwrite the
  2149. * settings in CSR PHY power control E1000_PHY_CTRL register. */
  2150. phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
  2151. } else {
  2152. ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
  2153. &phy_data);
  2154. if (ret_val)
  2155. return ret_val;
  2156. }
  2157. if (!active) {
  2158. if (hw->mac_type == e1000_82541_rev_2 ||
  2159. hw->mac_type == e1000_82547_rev_2) {
  2160. phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
  2161. ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
  2162. phy_data);
  2163. if (ret_val)
  2164. return ret_val;
  2165. } else {
  2166. if (hw->mac_type == e1000_ich8lan) {
  2167. phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
  2168. E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
  2169. } else {
  2170. phy_data &= ~IGP02E1000_PM_D3_LPLU;
  2171. ret_val = e1000_write_phy_reg(hw,
  2172. IGP02E1000_PHY_POWER_MGMT, phy_data);
  2173. if (ret_val)
  2174. return ret_val;
  2175. }
  2176. }
  2177. /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
  2178. * Dx states where the power conservation is most important. During
  2179. * driver activity we should enable SmartSpeed, so performance is
  2180. * maintained. */
  2181. if (hw->smart_speed == e1000_smart_speed_on) {
  2182. ret_val = e1000_read_phy_reg(hw,
  2183. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  2184. if (ret_val)
  2185. return ret_val;
  2186. phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
  2187. ret_val = e1000_write_phy_reg(hw,
  2188. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  2189. if (ret_val)
  2190. return ret_val;
  2191. } else if (hw->smart_speed == e1000_smart_speed_off) {
  2192. ret_val = e1000_read_phy_reg(hw,
  2193. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  2194. if (ret_val)
  2195. return ret_val;
  2196. phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  2197. ret_val = e1000_write_phy_reg(hw,
  2198. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  2199. if (ret_val)
  2200. return ret_val;
  2201. }
  2202. } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT)
  2203. || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) ||
  2204. (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
  2205. if (hw->mac_type == e1000_82541_rev_2 ||
  2206. hw->mac_type == e1000_82547_rev_2) {
  2207. phy_data |= IGP01E1000_GMII_FLEX_SPD;
  2208. ret_val = e1000_write_phy_reg(hw,
  2209. IGP01E1000_GMII_FIFO, phy_data);
  2210. if (ret_val)
  2211. return ret_val;
  2212. } else {
  2213. if (hw->mac_type == e1000_ich8lan) {
  2214. phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
  2215. E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
  2216. } else {
  2217. phy_data |= IGP02E1000_PM_D3_LPLU;
  2218. ret_val = e1000_write_phy_reg(hw,
  2219. IGP02E1000_PHY_POWER_MGMT, phy_data);
  2220. if (ret_val)
  2221. return ret_val;
  2222. }
  2223. }
  2224. /* When LPLU is enabled we should disable SmartSpeed */
  2225. ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
  2226. &phy_data);
  2227. if (ret_val)
  2228. return ret_val;
  2229. phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  2230. ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
  2231. phy_data);
  2232. if (ret_val)
  2233. return ret_val;
  2234. }
  2235. return E1000_SUCCESS;
  2236. }
  2237. /*****************************************************************************
  2238. *
  2239. * This function sets the lplu d0 state according to the active flag. When
  2240. * activating lplu this function also disables smart speed and vise versa.
  2241. * lplu will not be activated unless the device autonegotiation advertisment
  2242. * meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
  2243. * hw: Struct containing variables accessed by shared code
  2244. * active - true to enable lplu false to disable lplu.
  2245. *
  2246. * returns: - E1000_ERR_PHY if fail to read/write the PHY
  2247. * E1000_SUCCESS at any other case.
  2248. *
  2249. ****************************************************************************/
  2250. static int32_t
  2251. e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
  2252. {
  2253. uint32_t phy_ctrl = 0;
  2254. int32_t ret_val;
  2255. uint16_t phy_data;
  2256. DEBUGFUNC();
  2257. if (hw->mac_type <= e1000_82547_rev_2)
  2258. return E1000_SUCCESS;
  2259. if (hw->mac_type == e1000_ich8lan) {
  2260. phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
  2261. } else if (hw->mac_type == e1000_igb) {
  2262. phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL);
  2263. } else {
  2264. ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
  2265. &phy_data);
  2266. if (ret_val)
  2267. return ret_val;
  2268. }
  2269. if (!active) {
  2270. if (hw->mac_type == e1000_ich8lan) {
  2271. phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
  2272. E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
  2273. } else if (hw->mac_type == e1000_igb) {
  2274. phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
  2275. E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
  2276. } else {
  2277. phy_data &= ~IGP02E1000_PM_D0_LPLU;
  2278. ret_val = e1000_write_phy_reg(hw,
  2279. IGP02E1000_PHY_POWER_MGMT, phy_data);
  2280. if (ret_val)
  2281. return ret_val;
  2282. }
  2283. if (hw->mac_type == e1000_igb)
  2284. return E1000_SUCCESS;
  2285. /* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
  2286. * Dx states where the power conservation is most important. During
  2287. * driver activity we should enable SmartSpeed, so performance is
  2288. * maintained. */
  2289. if (hw->smart_speed == e1000_smart_speed_on) {
  2290. ret_val = e1000_read_phy_reg(hw,
  2291. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  2292. if (ret_val)
  2293. return ret_val;
  2294. phy_data |= IGP01E1000_PSCFR_SMART_SPEED;
  2295. ret_val = e1000_write_phy_reg(hw,
  2296. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  2297. if (ret_val)
  2298. return ret_val;
  2299. } else if (hw->smart_speed == e1000_smart_speed_off) {
  2300. ret_val = e1000_read_phy_reg(hw,
  2301. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  2302. if (ret_val)
  2303. return ret_val;
  2304. phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  2305. ret_val = e1000_write_phy_reg(hw,
  2306. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  2307. if (ret_val)
  2308. return ret_val;
  2309. }
  2310. } else {
  2311. if (hw->mac_type == e1000_ich8lan) {
  2312. phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
  2313. E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
  2314. } else if (hw->mac_type == e1000_igb) {
  2315. phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
  2316. E1000_WRITE_REG(hw, I210_PHY_CTRL, phy_ctrl);
  2317. } else {
  2318. phy_data |= IGP02E1000_PM_D0_LPLU;
  2319. ret_val = e1000_write_phy_reg(hw,
  2320. IGP02E1000_PHY_POWER_MGMT, phy_data);
  2321. if (ret_val)
  2322. return ret_val;
  2323. }
  2324. if (hw->mac_type == e1000_igb)
  2325. return E1000_SUCCESS;
  2326. /* When LPLU is enabled we should disable SmartSpeed */
  2327. ret_val = e1000_read_phy_reg(hw,
  2328. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  2329. if (ret_val)
  2330. return ret_val;
  2331. phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  2332. ret_val = e1000_write_phy_reg(hw,
  2333. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  2334. if (ret_val)
  2335. return ret_val;
  2336. }
  2337. return E1000_SUCCESS;
  2338. }
  2339. /********************************************************************
  2340. * Copper link setup for e1000_phy_igp series.
  2341. *
  2342. * hw - Struct containing variables accessed by shared code
  2343. *********************************************************************/
  2344. static int32_t
  2345. e1000_copper_link_igp_setup(struct e1000_hw *hw)
  2346. {
  2347. uint32_t led_ctrl;
  2348. int32_t ret_val;
  2349. uint16_t phy_data;
  2350. DEBUGFUNC();
  2351. if (hw->phy_reset_disable)
  2352. return E1000_SUCCESS;
  2353. ret_val = e1000_phy_reset(hw);
  2354. if (ret_val) {
  2355. DEBUGOUT("Error Resetting the PHY\n");
  2356. return ret_val;
  2357. }
  2358. /* Wait 15ms for MAC to configure PHY from eeprom settings */
  2359. mdelay(15);
  2360. if (hw->mac_type != e1000_ich8lan) {
  2361. /* Configure activity LED after PHY reset */
  2362. led_ctrl = E1000_READ_REG(hw, LEDCTL);
  2363. led_ctrl &= IGP_ACTIVITY_LED_MASK;
  2364. led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
  2365. E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
  2366. }
  2367. /* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
  2368. if (hw->phy_type == e1000_phy_igp) {
  2369. /* disable lplu d3 during driver init */
  2370. ret_val = e1000_set_d3_lplu_state(hw, false);
  2371. if (ret_val) {
  2372. DEBUGOUT("Error Disabling LPLU D3\n");
  2373. return ret_val;
  2374. }
  2375. }
  2376. /* disable lplu d0 during driver init */
  2377. ret_val = e1000_set_d0_lplu_state(hw, false);
  2378. if (ret_val) {
  2379. DEBUGOUT("Error Disabling LPLU D0\n");
  2380. return ret_val;
  2381. }
  2382. /* Configure mdi-mdix settings */
  2383. ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
  2384. if (ret_val)
  2385. return ret_val;
  2386. if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
  2387. hw->dsp_config_state = e1000_dsp_config_disabled;
  2388. /* Force MDI for earlier revs of the IGP PHY */
  2389. phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX
  2390. | IGP01E1000_PSCR_FORCE_MDI_MDIX);
  2391. hw->mdix = 1;
  2392. } else {
  2393. hw->dsp_config_state = e1000_dsp_config_enabled;
  2394. phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
  2395. switch (hw->mdix) {
  2396. case 1:
  2397. phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
  2398. break;
  2399. case 2:
  2400. phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
  2401. break;
  2402. case 0:
  2403. default:
  2404. phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
  2405. break;
  2406. }
  2407. }
  2408. ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
  2409. if (ret_val)
  2410. return ret_val;
  2411. /* set auto-master slave resolution settings */
  2412. if (hw->autoneg) {
  2413. e1000_ms_type phy_ms_setting = hw->master_slave;
  2414. if (hw->ffe_config_state == e1000_ffe_config_active)
  2415. hw->ffe_config_state = e1000_ffe_config_enabled;
  2416. if (hw->dsp_config_state == e1000_dsp_config_activated)
  2417. hw->dsp_config_state = e1000_dsp_config_enabled;
  2418. /* when autonegotiation advertisment is only 1000Mbps then we
  2419. * should disable SmartSpeed and enable Auto MasterSlave
  2420. * resolution as hardware default. */
  2421. if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
  2422. /* Disable SmartSpeed */
  2423. ret_val = e1000_read_phy_reg(hw,
  2424. IGP01E1000_PHY_PORT_CONFIG, &phy_data);
  2425. if (ret_val)
  2426. return ret_val;
  2427. phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
  2428. ret_val = e1000_write_phy_reg(hw,
  2429. IGP01E1000_PHY_PORT_CONFIG, phy_data);
  2430. if (ret_val)
  2431. return ret_val;
  2432. /* Set auto Master/Slave resolution process */
  2433. ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
  2434. &phy_data);
  2435. if (ret_val)
  2436. return ret_val;
  2437. phy_data &= ~CR_1000T_MS_ENABLE;
  2438. ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
  2439. phy_data);
  2440. if (ret_val)
  2441. return ret_val;
  2442. }
  2443. ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
  2444. if (ret_val)
  2445. return ret_val;
  2446. /* load defaults for future use */
  2447. hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
  2448. ((phy_data & CR_1000T_MS_VALUE) ?
  2449. e1000_ms_force_master :
  2450. e1000_ms_force_slave) :
  2451. e1000_ms_auto;
  2452. switch (phy_ms_setting) {
  2453. case e1000_ms_force_master:
  2454. phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
  2455. break;
  2456. case e1000_ms_force_slave:
  2457. phy_data |= CR_1000T_MS_ENABLE;
  2458. phy_data &= ~(CR_1000T_MS_VALUE);
  2459. break;
  2460. case e1000_ms_auto:
  2461. phy_data &= ~CR_1000T_MS_ENABLE;
  2462. default:
  2463. break;
  2464. }
  2465. ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
  2466. if (ret_val)
  2467. return ret_val;
  2468. }
  2469. return E1000_SUCCESS;
  2470. }
  2471. /*****************************************************************************
  2472. * This function checks the mode of the firmware.
  2473. *
  2474. * returns - true when the mode is IAMT or false.
  2475. ****************************************************************************/
  2476. bool
  2477. e1000_check_mng_mode(struct e1000_hw *hw)
  2478. {
  2479. uint32_t fwsm;
  2480. DEBUGFUNC();
  2481. fwsm = E1000_READ_REG(hw, FWSM);
  2482. if (hw->mac_type == e1000_ich8lan) {
  2483. if ((fwsm & E1000_FWSM_MODE_MASK) ==
  2484. (E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
  2485. return true;
  2486. } else if ((fwsm & E1000_FWSM_MODE_MASK) ==
  2487. (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
  2488. return true;
  2489. return false;
  2490. }
  2491. static int32_t
  2492. e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data)
  2493. {
  2494. uint16_t swfw = E1000_SWFW_PHY0_SM;
  2495. uint32_t reg_val;
  2496. DEBUGFUNC();
  2497. if (e1000_is_second_port(hw))
  2498. swfw = E1000_SWFW_PHY1_SM;
  2499. if (e1000_swfw_sync_acquire(hw, swfw))
  2500. return -E1000_ERR_SWFW_SYNC;
  2501. reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT)
  2502. & E1000_KUMCTRLSTA_OFFSET) | data;
  2503. E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
  2504. udelay(2);
  2505. return E1000_SUCCESS;
  2506. }
  2507. static int32_t
  2508. e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data)
  2509. {
  2510. uint16_t swfw = E1000_SWFW_PHY0_SM;
  2511. uint32_t reg_val;
  2512. DEBUGFUNC();
  2513. if (e1000_is_second_port(hw))
  2514. swfw = E1000_SWFW_PHY1_SM;
  2515. if (e1000_swfw_sync_acquire(hw, swfw)) {
  2516. debug("%s[%i]\n", __func__, __LINE__);
  2517. return -E1000_ERR_SWFW_SYNC;
  2518. }
  2519. /* Write register address */
  2520. reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
  2521. E1000_KUMCTRLSTA_OFFSET) | E1000_KUMCTRLSTA_REN;
  2522. E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
  2523. udelay(2);
  2524. /* Read the data returned */
  2525. reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
  2526. *data = (uint16_t)reg_val;
  2527. return E1000_SUCCESS;
  2528. }
  2529. /********************************************************************
  2530. * Copper link setup for e1000_phy_gg82563 series.
  2531. *
  2532. * hw - Struct containing variables accessed by shared code
  2533. *********************************************************************/
  2534. static int32_t
  2535. e1000_copper_link_ggp_setup(struct e1000_hw *hw)
  2536. {
  2537. int32_t ret_val;
  2538. uint16_t phy_data;
  2539. uint32_t reg_data;
  2540. DEBUGFUNC();
  2541. if (!hw->phy_reset_disable) {
  2542. /* Enable CRS on TX for half-duplex operation. */
  2543. ret_val = e1000_read_phy_reg(hw,
  2544. GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
  2545. if (ret_val)
  2546. return ret_val;
  2547. phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
  2548. /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
  2549. phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
  2550. ret_val = e1000_write_phy_reg(hw,
  2551. GG82563_PHY_MAC_SPEC_CTRL, phy_data);
  2552. if (ret_val)
  2553. return ret_val;
  2554. /* Options:
  2555. * MDI/MDI-X = 0 (default)
  2556. * 0 - Auto for all speeds
  2557. * 1 - MDI mode
  2558. * 2 - MDI-X mode
  2559. * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
  2560. */
  2561. ret_val = e1000_read_phy_reg(hw,
  2562. GG82563_PHY_SPEC_CTRL, &phy_data);
  2563. if (ret_val)
  2564. return ret_val;
  2565. phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
  2566. switch (hw->mdix) {
  2567. case 1:
  2568. phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
  2569. break;
  2570. case 2:
  2571. phy_data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
  2572. break;
  2573. case 0:
  2574. default:
  2575. phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
  2576. break;
  2577. }
  2578. /* Options:
  2579. * disable_polarity_correction = 0 (default)
  2580. * Automatic Correction for Reversed Cable Polarity
  2581. * 0 - Disabled
  2582. * 1 - Enabled
  2583. */
  2584. phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
  2585. ret_val = e1000_write_phy_reg(hw,
  2586. GG82563_PHY_SPEC_CTRL, phy_data);
  2587. if (ret_val)
  2588. return ret_val;
  2589. /* SW Reset the PHY so all changes take effect */
  2590. ret_val = e1000_phy_reset(hw);
  2591. if (ret_val) {
  2592. DEBUGOUT("Error Resetting the PHY\n");
  2593. return ret_val;
  2594. }
  2595. } /* phy_reset_disable */
  2596. if (hw->mac_type == e1000_80003es2lan) {
  2597. /* Bypass RX and TX FIFO's */
  2598. ret_val = e1000_write_kmrn_reg(hw,
  2599. E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
  2600. E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS
  2601. | E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
  2602. if (ret_val)
  2603. return ret_val;
  2604. ret_val = e1000_read_phy_reg(hw,
  2605. GG82563_PHY_SPEC_CTRL_2, &phy_data);
  2606. if (ret_val)
  2607. return ret_val;
  2608. phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
  2609. ret_val = e1000_write_phy_reg(hw,
  2610. GG82563_PHY_SPEC_CTRL_2, phy_data);
  2611. if (ret_val)
  2612. return ret_val;
  2613. reg_data = E1000_READ_REG(hw, CTRL_EXT);
  2614. reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
  2615. E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
  2616. ret_val = e1000_read_phy_reg(hw,
  2617. GG82563_PHY_PWR_MGMT_CTRL, &phy_data);
  2618. if (ret_val)
  2619. return ret_val;
  2620. /* Do not init these registers when the HW is in IAMT mode, since the
  2621. * firmware will have already initialized them. We only initialize
  2622. * them if the HW is not in IAMT mode.
  2623. */
  2624. if (e1000_check_mng_mode(hw) == false) {
  2625. /* Enable Electrical Idle on the PHY */
  2626. phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
  2627. ret_val = e1000_write_phy_reg(hw,
  2628. GG82563_PHY_PWR_MGMT_CTRL, phy_data);
  2629. if (ret_val)
  2630. return ret_val;
  2631. ret_val = e1000_read_phy_reg(hw,
  2632. GG82563_PHY_KMRN_MODE_CTRL, &phy_data);
  2633. if (ret_val)
  2634. return ret_val;
  2635. phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
  2636. ret_val = e1000_write_phy_reg(hw,
  2637. GG82563_PHY_KMRN_MODE_CTRL, phy_data);
  2638. if (ret_val)
  2639. return ret_val;
  2640. }
  2641. /* Workaround: Disable padding in Kumeran interface in the MAC
  2642. * and in the PHY to avoid CRC errors.
  2643. */
  2644. ret_val = e1000_read_phy_reg(hw,
  2645. GG82563_PHY_INBAND_CTRL, &phy_data);
  2646. if (ret_val)
  2647. return ret_val;
  2648. phy_data |= GG82563_ICR_DIS_PADDING;
  2649. ret_val = e1000_write_phy_reg(hw,
  2650. GG82563_PHY_INBAND_CTRL, phy_data);
  2651. if (ret_val)
  2652. return ret_val;
  2653. }
  2654. return E1000_SUCCESS;
  2655. }
  2656. /********************************************************************
  2657. * Copper link setup for e1000_phy_m88 series.
  2658. *
  2659. * hw - Struct containing variables accessed by shared code
  2660. *********************************************************************/
  2661. static int32_t
  2662. e1000_copper_link_mgp_setup(struct e1000_hw *hw)
  2663. {
  2664. int32_t ret_val;
  2665. uint16_t phy_data;
  2666. DEBUGFUNC();
  2667. if (hw->phy_reset_disable)
  2668. return E1000_SUCCESS;
  2669. /* Enable CRS on TX. This must be set for half-duplex operation. */
  2670. ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
  2671. if (ret_val)
  2672. return ret_val;
  2673. phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
  2674. /* Options:
  2675. * MDI/MDI-X = 0 (default)
  2676. * 0 - Auto for all speeds
  2677. * 1 - MDI mode
  2678. * 2 - MDI-X mode
  2679. * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
  2680. */
  2681. phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
  2682. switch (hw->mdix) {
  2683. case 1:
  2684. phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
  2685. break;
  2686. case 2:
  2687. phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
  2688. break;
  2689. case 3:
  2690. phy_data |= M88E1000_PSCR_AUTO_X_1000T;
  2691. break;
  2692. case 0:
  2693. default:
  2694. phy_data |= M88E1000_PSCR_AUTO_X_MODE;
  2695. break;
  2696. }
  2697. /* Options:
  2698. * disable_polarity_correction = 0 (default)
  2699. * Automatic Correction for Reversed Cable Polarity
  2700. * 0 - Disabled
  2701. * 1 - Enabled
  2702. */
  2703. phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
  2704. ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
  2705. if (ret_val)
  2706. return ret_val;
  2707. if (hw->phy_revision < M88E1011_I_REV_4) {
  2708. /* Force TX_CLK in the Extended PHY Specific Control Register
  2709. * to 25MHz clock.
  2710. */
  2711. ret_val = e1000_read_phy_reg(hw,
  2712. M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
  2713. if (ret_val)
  2714. return ret_val;
  2715. phy_data |= M88E1000_EPSCR_TX_CLK_25;
  2716. if ((hw->phy_revision == E1000_REVISION_2) &&
  2717. (hw->phy_id == M88E1111_I_PHY_ID)) {
  2718. /* Vidalia Phy, set the downshift counter to 5x */
  2719. phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
  2720. phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
  2721. ret_val = e1000_write_phy_reg(hw,
  2722. M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
  2723. if (ret_val)
  2724. return ret_val;
  2725. } else {
  2726. /* Configure Master and Slave downshift values */
  2727. phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
  2728. | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
  2729. phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
  2730. | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
  2731. ret_val = e1000_write_phy_reg(hw,
  2732. M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
  2733. if (ret_val)
  2734. return ret_val;
  2735. }
  2736. }
  2737. /* SW Reset the PHY so all changes take effect */
  2738. ret_val = e1000_phy_reset(hw);
  2739. if (ret_val) {
  2740. DEBUGOUT("Error Resetting the PHY\n");
  2741. return ret_val;
  2742. }
  2743. return E1000_SUCCESS;
  2744. }
  2745. /********************************************************************
  2746. * Setup auto-negotiation and flow control advertisements,
  2747. * and then perform auto-negotiation.
  2748. *
  2749. * hw - Struct containing variables accessed by shared code
  2750. *********************************************************************/
  2751. static int32_t
  2752. e1000_copper_link_autoneg(struct e1000_hw *hw)
  2753. {
  2754. int32_t ret_val;
  2755. uint16_t phy_data;
  2756. DEBUGFUNC();
  2757. /* Perform some bounds checking on the hw->autoneg_advertised
  2758. * parameter. If this variable is zero, then set it to the default.
  2759. */
  2760. hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
  2761. /* If autoneg_advertised is zero, we assume it was not defaulted
  2762. * by the calling code so we set to advertise full capability.
  2763. */
  2764. if (hw->autoneg_advertised == 0)
  2765. hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
  2766. /* IFE phy only supports 10/100 */
  2767. if (hw->phy_type == e1000_phy_ife)
  2768. hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
  2769. DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
  2770. ret_val = e1000_phy_setup_autoneg(hw);
  2771. if (ret_val) {
  2772. DEBUGOUT("Error Setting up Auto-Negotiation\n");
  2773. return ret_val;
  2774. }
  2775. DEBUGOUT("Restarting Auto-Neg\n");
  2776. /* Restart auto-negotiation by setting the Auto Neg Enable bit and
  2777. * the Auto Neg Restart bit in the PHY control register.
  2778. */
  2779. ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
  2780. if (ret_val)
  2781. return ret_val;
  2782. phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
  2783. ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
  2784. if (ret_val)
  2785. return ret_val;
  2786. /* Does the user want to wait for Auto-Neg to complete here, or
  2787. * check at a later time (for example, callback routine).
  2788. */
  2789. /* If we do not wait for autonegtation to complete I
  2790. * do not see a valid link status.
  2791. * wait_autoneg_complete = 1 .
  2792. */
  2793. if (hw->wait_autoneg_complete) {
  2794. ret_val = e1000_wait_autoneg(hw);
  2795. if (ret_val) {
  2796. DEBUGOUT("Error while waiting for autoneg"
  2797. "to complete\n");
  2798. return ret_val;
  2799. }
  2800. }
  2801. hw->get_link_status = true;
  2802. return E1000_SUCCESS;
  2803. }
  2804. /******************************************************************************
  2805. * Config the MAC and the PHY after link is up.
  2806. * 1) Set up the MAC to the current PHY speed/duplex
  2807. * if we are on 82543. If we
  2808. * are on newer silicon, we only need to configure
  2809. * collision distance in the Transmit Control Register.
  2810. * 2) Set up flow control on the MAC to that established with
  2811. * the link partner.
  2812. * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
  2813. *
  2814. * hw - Struct containing variables accessed by shared code
  2815. ******************************************************************************/
  2816. static int32_t
  2817. e1000_copper_link_postconfig(struct e1000_hw *hw)
  2818. {
  2819. int32_t ret_val;
  2820. DEBUGFUNC();
  2821. if (hw->mac_type >= e1000_82544) {
  2822. e1000_config_collision_dist(hw);
  2823. } else {
  2824. ret_val = e1000_config_mac_to_phy(hw);
  2825. if (ret_val) {
  2826. DEBUGOUT("Error configuring MAC to PHY settings\n");
  2827. return ret_val;
  2828. }
  2829. }
  2830. ret_val = e1000_config_fc_after_link_up(hw);
  2831. if (ret_val) {
  2832. DEBUGOUT("Error Configuring Flow Control\n");
  2833. return ret_val;
  2834. }
  2835. return E1000_SUCCESS;
  2836. }
  2837. /******************************************************************************
  2838. * Detects which PHY is present and setup the speed and duplex
  2839. *
  2840. * hw - Struct containing variables accessed by shared code
  2841. ******************************************************************************/
  2842. static int
  2843. e1000_setup_copper_link(struct e1000_hw *hw)
  2844. {
  2845. int32_t ret_val;
  2846. uint16_t i;
  2847. uint16_t phy_data;
  2848. uint16_t reg_data;
  2849. DEBUGFUNC();
  2850. switch (hw->mac_type) {
  2851. case e1000_80003es2lan:
  2852. case e1000_ich8lan:
  2853. /* Set the mac to wait the maximum time between each
  2854. * iteration and increase the max iterations when
  2855. * polling the phy; this fixes erroneous timeouts at 10Mbps. */
  2856. ret_val = e1000_write_kmrn_reg(hw,
  2857. GG82563_REG(0x34, 4), 0xFFFF);
  2858. if (ret_val)
  2859. return ret_val;
  2860. ret_val = e1000_read_kmrn_reg(hw,
  2861. GG82563_REG(0x34, 9), &reg_data);
  2862. if (ret_val)
  2863. return ret_val;
  2864. reg_data |= 0x3F;
  2865. ret_val = e1000_write_kmrn_reg(hw,
  2866. GG82563_REG(0x34, 9), reg_data);
  2867. if (ret_val)
  2868. return ret_val;
  2869. default:
  2870. break;
  2871. }
  2872. /* Check if it is a valid PHY and set PHY mode if necessary. */
  2873. ret_val = e1000_copper_link_preconfig(hw);
  2874. if (ret_val)
  2875. return ret_val;
  2876. switch (hw->mac_type) {
  2877. case e1000_80003es2lan:
  2878. /* Kumeran registers are written-only */
  2879. reg_data =
  2880. E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
  2881. reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
  2882. ret_val = e1000_write_kmrn_reg(hw,
  2883. E1000_KUMCTRLSTA_OFFSET_INB_CTRL, reg_data);
  2884. if (ret_val)
  2885. return ret_val;
  2886. break;
  2887. default:
  2888. break;
  2889. }
  2890. if (hw->phy_type == e1000_phy_igp ||
  2891. hw->phy_type == e1000_phy_igp_3 ||
  2892. hw->phy_type == e1000_phy_igp_2) {
  2893. ret_val = e1000_copper_link_igp_setup(hw);
  2894. if (ret_val)
  2895. return ret_val;
  2896. } else if (hw->phy_type == e1000_phy_m88 ||
  2897. hw->phy_type == e1000_phy_igb) {
  2898. ret_val = e1000_copper_link_mgp_setup(hw);
  2899. if (ret_val)
  2900. return ret_val;
  2901. } else if (hw->phy_type == e1000_phy_gg82563) {
  2902. ret_val = e1000_copper_link_ggp_setup(hw);
  2903. if (ret_val)
  2904. return ret_val;
  2905. }
  2906. /* always auto */
  2907. /* Setup autoneg and flow control advertisement
  2908. * and perform autonegotiation */
  2909. ret_val = e1000_copper_link_autoneg(hw);
  2910. if (ret_val)
  2911. return ret_val;
  2912. /* Check link status. Wait up to 100 microseconds for link to become
  2913. * valid.
  2914. */
  2915. for (i = 0; i < 10; i++) {
  2916. ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
  2917. if (ret_val)
  2918. return ret_val;
  2919. ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
  2920. if (ret_val)
  2921. return ret_val;
  2922. if (phy_data & MII_SR_LINK_STATUS) {
  2923. /* Config the MAC and PHY after link is up */
  2924. ret_val = e1000_copper_link_postconfig(hw);
  2925. if (ret_val)
  2926. return ret_val;
  2927. DEBUGOUT("Valid link established!!!\n");
  2928. return E1000_SUCCESS;
  2929. }
  2930. udelay(10);
  2931. }
  2932. DEBUGOUT("Unable to establish link!!!\n");
  2933. return E1000_SUCCESS;
  2934. }
  2935. /******************************************************************************
  2936. * Configures PHY autoneg and flow control advertisement settings
  2937. *
  2938. * hw - Struct containing variables accessed by shared code
  2939. ******************************************************************************/
  2940. int32_t
  2941. e1000_phy_setup_autoneg(struct e1000_hw *hw)
  2942. {
  2943. int32_t ret_val;
  2944. uint16_t mii_autoneg_adv_reg;
  2945. uint16_t mii_1000t_ctrl_reg;
  2946. DEBUGFUNC();
  2947. /* Read the MII Auto-Neg Advertisement Register (Address 4). */
  2948. ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
  2949. if (ret_val)
  2950. return ret_val;
  2951. if (hw->phy_type != e1000_phy_ife) {
  2952. /* Read the MII 1000Base-T Control Register (Address 9). */
  2953. ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
  2954. &mii_1000t_ctrl_reg);
  2955. if (ret_val)
  2956. return ret_val;
  2957. } else
  2958. mii_1000t_ctrl_reg = 0;
  2959. /* Need to parse both autoneg_advertised and fc and set up
  2960. * the appropriate PHY registers. First we will parse for
  2961. * autoneg_advertised software override. Since we can advertise
  2962. * a plethora of combinations, we need to check each bit
  2963. * individually.
  2964. */
  2965. /* First we clear all the 10/100 mb speed bits in the Auto-Neg
  2966. * Advertisement Register (Address 4) and the 1000 mb speed bits in
  2967. * the 1000Base-T Control Register (Address 9).
  2968. */
  2969. mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
  2970. mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
  2971. DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised);
  2972. /* Do we want to advertise 10 Mb Half Duplex? */
  2973. if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
  2974. DEBUGOUT("Advertise 10mb Half duplex\n");
  2975. mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
  2976. }
  2977. /* Do we want to advertise 10 Mb Full Duplex? */
  2978. if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
  2979. DEBUGOUT("Advertise 10mb Full duplex\n");
  2980. mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
  2981. }
  2982. /* Do we want to advertise 100 Mb Half Duplex? */
  2983. if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
  2984. DEBUGOUT("Advertise 100mb Half duplex\n");
  2985. mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
  2986. }
  2987. /* Do we want to advertise 100 Mb Full Duplex? */
  2988. if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
  2989. DEBUGOUT("Advertise 100mb Full duplex\n");
  2990. mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
  2991. }
  2992. /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
  2993. if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
  2994. DEBUGOUT
  2995. ("Advertise 1000mb Half duplex requested, request denied!\n");
  2996. }
  2997. /* Do we want to advertise 1000 Mb Full Duplex? */
  2998. if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
  2999. DEBUGOUT("Advertise 1000mb Full duplex\n");
  3000. mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
  3001. }
  3002. /* Check for a software override of the flow control settings, and
  3003. * setup the PHY advertisement registers accordingly. If
  3004. * auto-negotiation is enabled, then software will have to set the
  3005. * "PAUSE" bits to the correct value in the Auto-Negotiation
  3006. * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
  3007. *
  3008. * The possible values of the "fc" parameter are:
  3009. * 0: Flow control is completely disabled
  3010. * 1: Rx flow control is enabled (we can receive pause frames
  3011. * but not send pause frames).
  3012. * 2: Tx flow control is enabled (we can send pause frames
  3013. * but we do not support receiving pause frames).
  3014. * 3: Both Rx and TX flow control (symmetric) are enabled.
  3015. * other: No software override. The flow control configuration
  3016. * in the EEPROM is used.
  3017. */
  3018. switch (hw->fc) {
  3019. case e1000_fc_none: /* 0 */
  3020. /* Flow control (RX & TX) is completely disabled by a
  3021. * software over-ride.
  3022. */
  3023. mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
  3024. break;
  3025. case e1000_fc_rx_pause: /* 1 */
  3026. /* RX Flow control is enabled, and TX Flow control is
  3027. * disabled, by a software over-ride.
  3028. */
  3029. /* Since there really isn't a way to advertise that we are
  3030. * capable of RX Pause ONLY, we will advertise that we
  3031. * support both symmetric and asymmetric RX PAUSE. Later
  3032. * (in e1000_config_fc_after_link_up) we will disable the
  3033. *hw's ability to send PAUSE frames.
  3034. */
  3035. mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
  3036. break;
  3037. case e1000_fc_tx_pause: /* 2 */
  3038. /* TX Flow control is enabled, and RX Flow control is
  3039. * disabled, by a software over-ride.
  3040. */
  3041. mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
  3042. mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
  3043. break;
  3044. case e1000_fc_full: /* 3 */
  3045. /* Flow control (both RX and TX) is enabled by a software
  3046. * over-ride.
  3047. */
  3048. mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
  3049. break;
  3050. default:
  3051. DEBUGOUT("Flow control param set incorrectly\n");
  3052. return -E1000_ERR_CONFIG;
  3053. }
  3054. ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
  3055. if (ret_val)
  3056. return ret_val;
  3057. DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
  3058. if (hw->phy_type != e1000_phy_ife) {
  3059. ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
  3060. mii_1000t_ctrl_reg);
  3061. if (ret_val)
  3062. return ret_val;
  3063. }
  3064. return E1000_SUCCESS;
  3065. }
  3066. /******************************************************************************
  3067. * Sets the collision distance in the Transmit Control register
  3068. *
  3069. * hw - Struct containing variables accessed by shared code
  3070. *
  3071. * Link should have been established previously. Reads the speed and duplex
  3072. * information from the Device Status register.
  3073. ******************************************************************************/
  3074. static void
  3075. e1000_config_collision_dist(struct e1000_hw *hw)
  3076. {
  3077. uint32_t tctl, coll_dist;
  3078. DEBUGFUNC();
  3079. if (hw->mac_type < e1000_82543)
  3080. coll_dist = E1000_COLLISION_DISTANCE_82542;
  3081. else
  3082. coll_dist = E1000_COLLISION_DISTANCE;
  3083. tctl = E1000_READ_REG(hw, TCTL);
  3084. tctl &= ~E1000_TCTL_COLD;
  3085. tctl |= coll_dist << E1000_COLD_SHIFT;
  3086. E1000_WRITE_REG(hw, TCTL, tctl);
  3087. E1000_WRITE_FLUSH(hw);
  3088. }
  3089. /******************************************************************************
  3090. * Sets MAC speed and duplex settings to reflect the those in the PHY
  3091. *
  3092. * hw - Struct containing variables accessed by shared code
  3093. * mii_reg - data to write to the MII control register
  3094. *
  3095. * The contents of the PHY register containing the needed information need to
  3096. * be passed in.
  3097. ******************************************************************************/
  3098. static int
  3099. e1000_config_mac_to_phy(struct e1000_hw *hw)
  3100. {
  3101. uint32_t ctrl;
  3102. uint16_t phy_data;
  3103. DEBUGFUNC();
  3104. /* Read the Device Control Register and set the bits to Force Speed
  3105. * and Duplex.
  3106. */
  3107. ctrl = E1000_READ_REG(hw, CTRL);
  3108. ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
  3109. ctrl &= ~(E1000_CTRL_ILOS);
  3110. ctrl |= (E1000_CTRL_SPD_SEL);
  3111. /* Set up duplex in the Device Control and Transmit Control
  3112. * registers depending on negotiated values.
  3113. */
  3114. if (e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data) < 0) {
  3115. DEBUGOUT("PHY Read Error\n");
  3116. return -E1000_ERR_PHY;
  3117. }
  3118. if (phy_data & M88E1000_PSSR_DPLX)
  3119. ctrl |= E1000_CTRL_FD;
  3120. else
  3121. ctrl &= ~E1000_CTRL_FD;
  3122. e1000_config_collision_dist(hw);
  3123. /* Set up speed in the Device Control register depending on
  3124. * negotiated values.
  3125. */
  3126. if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
  3127. ctrl |= E1000_CTRL_SPD_1000;
  3128. else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
  3129. ctrl |= E1000_CTRL_SPD_100;
  3130. /* Write the configured values back to the Device Control Reg. */
  3131. E1000_WRITE_REG(hw, CTRL, ctrl);
  3132. return 0;
  3133. }
  3134. /******************************************************************************
  3135. * Forces the MAC's flow control settings.
  3136. *
  3137. * hw - Struct containing variables accessed by shared code
  3138. *
  3139. * Sets the TFCE and RFCE bits in the device control register to reflect
  3140. * the adapter settings. TFCE and RFCE need to be explicitly set by
  3141. * software when a Copper PHY is used because autonegotiation is managed
  3142. * by the PHY rather than the MAC. Software must also configure these
  3143. * bits when link is forced on a fiber connection.
  3144. *****************************************************************************/
  3145. static int
  3146. e1000_force_mac_fc(struct e1000_hw *hw)
  3147. {
  3148. uint32_t ctrl;
  3149. DEBUGFUNC();
  3150. /* Get the current configuration of the Device Control Register */
  3151. ctrl = E1000_READ_REG(hw, CTRL);
  3152. /* Because we didn't get link via the internal auto-negotiation
  3153. * mechanism (we either forced link or we got link via PHY
  3154. * auto-neg), we have to manually enable/disable transmit an
  3155. * receive flow control.
  3156. *
  3157. * The "Case" statement below enables/disable flow control
  3158. * according to the "hw->fc" parameter.
  3159. *
  3160. * The possible values of the "fc" parameter are:
  3161. * 0: Flow control is completely disabled
  3162. * 1: Rx flow control is enabled (we can receive pause
  3163. * frames but not send pause frames).
  3164. * 2: Tx flow control is enabled (we can send pause frames
  3165. * frames but we do not receive pause frames).
  3166. * 3: Both Rx and TX flow control (symmetric) is enabled.
  3167. * other: No other values should be possible at this point.
  3168. */
  3169. switch (hw->fc) {
  3170. case e1000_fc_none:
  3171. ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
  3172. break;
  3173. case e1000_fc_rx_pause:
  3174. ctrl &= (~E1000_CTRL_TFCE);
  3175. ctrl |= E1000_CTRL_RFCE;
  3176. break;
  3177. case e1000_fc_tx_pause:
  3178. ctrl &= (~E1000_CTRL_RFCE);
  3179. ctrl |= E1000_CTRL_TFCE;
  3180. break;
  3181. case e1000_fc_full:
  3182. ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
  3183. break;
  3184. default:
  3185. DEBUGOUT("Flow control param set incorrectly\n");
  3186. return -E1000_ERR_CONFIG;
  3187. }
  3188. /* Disable TX Flow Control for 82542 (rev 2.0) */
  3189. if (hw->mac_type == e1000_82542_rev2_0)
  3190. ctrl &= (~E1000_CTRL_TFCE);
  3191. E1000_WRITE_REG(hw, CTRL, ctrl);
  3192. return 0;
  3193. }
  3194. /******************************************************************************
  3195. * Configures flow control settings after link is established
  3196. *
  3197. * hw - Struct containing variables accessed by shared code
  3198. *
  3199. * Should be called immediately after a valid link has been established.
  3200. * Forces MAC flow control settings if link was forced. When in MII/GMII mode
  3201. * and autonegotiation is enabled, the MAC flow control settings will be set
  3202. * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
  3203. * and RFCE bits will be automaticaly set to the negotiated flow control mode.
  3204. *****************************************************************************/
  3205. static int32_t
  3206. e1000_config_fc_after_link_up(struct e1000_hw *hw)
  3207. {
  3208. int32_t ret_val;
  3209. uint16_t mii_status_reg;
  3210. uint16_t mii_nway_adv_reg;
  3211. uint16_t mii_nway_lp_ability_reg;
  3212. uint16_t speed;
  3213. uint16_t duplex;
  3214. DEBUGFUNC();
  3215. /* Check for the case where we have fiber media and auto-neg failed
  3216. * so we had to force link. In this case, we need to force the
  3217. * configuration of the MAC to match the "fc" parameter.
  3218. */
  3219. if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed))
  3220. || ((hw->media_type == e1000_media_type_internal_serdes)
  3221. && (hw->autoneg_failed))
  3222. || ((hw->media_type == e1000_media_type_copper)
  3223. && (!hw->autoneg))) {
  3224. ret_val = e1000_force_mac_fc(hw);
  3225. if (ret_val < 0) {
  3226. DEBUGOUT("Error forcing flow control settings\n");
  3227. return ret_val;
  3228. }
  3229. }
  3230. /* Check for the case where we have copper media and auto-neg is
  3231. * enabled. In this case, we need to check and see if Auto-Neg
  3232. * has completed, and if so, how the PHY and link partner has
  3233. * flow control configured.
  3234. */
  3235. if (hw->media_type == e1000_media_type_copper) {
  3236. /* Read the MII Status Register and check to see if AutoNeg
  3237. * has completed. We read this twice because this reg has
  3238. * some "sticky" (latched) bits.
  3239. */
  3240. if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
  3241. DEBUGOUT("PHY Read Error\n");
  3242. return -E1000_ERR_PHY;
  3243. }
  3244. if (e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg) < 0) {
  3245. DEBUGOUT("PHY Read Error\n");
  3246. return -E1000_ERR_PHY;
  3247. }
  3248. if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
  3249. /* The AutoNeg process has completed, so we now need to
  3250. * read both the Auto Negotiation Advertisement Register
  3251. * (Address 4) and the Auto_Negotiation Base Page Ability
  3252. * Register (Address 5) to determine how flow control was
  3253. * negotiated.
  3254. */
  3255. if (e1000_read_phy_reg
  3256. (hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg) < 0) {
  3257. DEBUGOUT("PHY Read Error\n");
  3258. return -E1000_ERR_PHY;
  3259. }
  3260. if (e1000_read_phy_reg
  3261. (hw, PHY_LP_ABILITY,
  3262. &mii_nway_lp_ability_reg) < 0) {
  3263. DEBUGOUT("PHY Read Error\n");
  3264. return -E1000_ERR_PHY;
  3265. }
  3266. /* Two bits in the Auto Negotiation Advertisement Register
  3267. * (Address 4) and two bits in the Auto Negotiation Base
  3268. * Page Ability Register (Address 5) determine flow control
  3269. * for both the PHY and the link partner. The following
  3270. * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
  3271. * 1999, describes these PAUSE resolution bits and how flow
  3272. * control is determined based upon these settings.
  3273. * NOTE: DC = Don't Care
  3274. *
  3275. * LOCAL DEVICE | LINK PARTNER
  3276. * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
  3277. *-------|---------|-------|---------|--------------------
  3278. * 0 | 0 | DC | DC | e1000_fc_none
  3279. * 0 | 1 | 0 | DC | e1000_fc_none
  3280. * 0 | 1 | 1 | 0 | e1000_fc_none
  3281. * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
  3282. * 1 | 0 | 0 | DC | e1000_fc_none
  3283. * 1 | DC | 1 | DC | e1000_fc_full
  3284. * 1 | 1 | 0 | 0 | e1000_fc_none
  3285. * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
  3286. *
  3287. */
  3288. /* Are both PAUSE bits set to 1? If so, this implies
  3289. * Symmetric Flow Control is enabled at both ends. The
  3290. * ASM_DIR bits are irrelevant per the spec.
  3291. *
  3292. * For Symmetric Flow Control:
  3293. *
  3294. * LOCAL DEVICE | LINK PARTNER
  3295. * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
  3296. *-------|---------|-------|---------|--------------------
  3297. * 1 | DC | 1 | DC | e1000_fc_full
  3298. *
  3299. */
  3300. if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
  3301. (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
  3302. /* Now we need to check if the user selected RX ONLY
  3303. * of pause frames. In this case, we had to advertise
  3304. * FULL flow control because we could not advertise RX
  3305. * ONLY. Hence, we must now check to see if we need to
  3306. * turn OFF the TRANSMISSION of PAUSE frames.
  3307. */
  3308. if (hw->original_fc == e1000_fc_full) {
  3309. hw->fc = e1000_fc_full;
  3310. DEBUGOUT("Flow Control = FULL.\r\n");
  3311. } else {
  3312. hw->fc = e1000_fc_rx_pause;
  3313. DEBUGOUT
  3314. ("Flow Control = RX PAUSE frames only.\r\n");
  3315. }
  3316. }
  3317. /* For receiving PAUSE frames ONLY.
  3318. *
  3319. * LOCAL DEVICE | LINK PARTNER
  3320. * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
  3321. *-------|---------|-------|---------|--------------------
  3322. * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
  3323. *
  3324. */
  3325. else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
  3326. (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
  3327. (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
  3328. (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
  3329. {
  3330. hw->fc = e1000_fc_tx_pause;
  3331. DEBUGOUT
  3332. ("Flow Control = TX PAUSE frames only.\r\n");
  3333. }
  3334. /* For transmitting PAUSE frames ONLY.
  3335. *
  3336. * LOCAL DEVICE | LINK PARTNER
  3337. * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
  3338. *-------|---------|-------|---------|--------------------
  3339. * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
  3340. *
  3341. */
  3342. else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
  3343. (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
  3344. !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
  3345. (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR))
  3346. {
  3347. hw->fc = e1000_fc_rx_pause;
  3348. DEBUGOUT
  3349. ("Flow Control = RX PAUSE frames only.\r\n");
  3350. }
  3351. /* Per the IEEE spec, at this point flow control should be
  3352. * disabled. However, we want to consider that we could
  3353. * be connected to a legacy switch that doesn't advertise
  3354. * desired flow control, but can be forced on the link
  3355. * partner. So if we advertised no flow control, that is
  3356. * what we will resolve to. If we advertised some kind of
  3357. * receive capability (Rx Pause Only or Full Flow Control)
  3358. * and the link partner advertised none, we will configure
  3359. * ourselves to enable Rx Flow Control only. We can do
  3360. * this safely for two reasons: If the link partner really
  3361. * didn't want flow control enabled, and we enable Rx, no
  3362. * harm done since we won't be receiving any PAUSE frames
  3363. * anyway. If the intent on the link partner was to have
  3364. * flow control enabled, then by us enabling RX only, we
  3365. * can at least receive pause frames and process them.
  3366. * This is a good idea because in most cases, since we are
  3367. * predominantly a server NIC, more times than not we will
  3368. * be asked to delay transmission of packets than asking
  3369. * our link partner to pause transmission of frames.
  3370. */
  3371. else if (hw->original_fc == e1000_fc_none ||
  3372. hw->original_fc == e1000_fc_tx_pause) {
  3373. hw->fc = e1000_fc_none;
  3374. DEBUGOUT("Flow Control = NONE.\r\n");
  3375. } else {
  3376. hw->fc = e1000_fc_rx_pause;
  3377. DEBUGOUT
  3378. ("Flow Control = RX PAUSE frames only.\r\n");
  3379. }
  3380. /* Now we need to do one last check... If we auto-
  3381. * negotiated to HALF DUPLEX, flow control should not be
  3382. * enabled per IEEE 802.3 spec.
  3383. */
  3384. e1000_get_speed_and_duplex(hw, &speed, &duplex);
  3385. if (duplex == HALF_DUPLEX)
  3386. hw->fc = e1000_fc_none;
  3387. /* Now we call a subroutine to actually force the MAC
  3388. * controller to use the correct flow control settings.
  3389. */
  3390. ret_val = e1000_force_mac_fc(hw);
  3391. if (ret_val < 0) {
  3392. DEBUGOUT
  3393. ("Error forcing flow control settings\n");
  3394. return ret_val;
  3395. }
  3396. } else {
  3397. DEBUGOUT
  3398. ("Copper PHY and Auto Neg has not completed.\r\n");
  3399. }
  3400. }
  3401. return E1000_SUCCESS;
  3402. }
  3403. /******************************************************************************
  3404. * Checks to see if the link status of the hardware has changed.
  3405. *
  3406. * hw - Struct containing variables accessed by shared code
  3407. *
  3408. * Called by any function that needs to check the link status of the adapter.
  3409. *****************************************************************************/
  3410. static int
  3411. e1000_check_for_link(struct e1000_hw *hw)
  3412. {
  3413. uint32_t rxcw;
  3414. uint32_t ctrl;
  3415. uint32_t status;
  3416. uint32_t rctl;
  3417. uint32_t signal;
  3418. int32_t ret_val;
  3419. uint16_t phy_data;
  3420. uint16_t lp_capability;
  3421. DEBUGFUNC();
  3422. /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be
  3423. * set when the optics detect a signal. On older adapters, it will be
  3424. * cleared when there is a signal
  3425. */
  3426. ctrl = E1000_READ_REG(hw, CTRL);
  3427. if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS))
  3428. signal = E1000_CTRL_SWDPIN1;
  3429. else
  3430. signal = 0;
  3431. status = E1000_READ_REG(hw, STATUS);
  3432. rxcw = E1000_READ_REG(hw, RXCW);
  3433. DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw);
  3434. /* If we have a copper PHY then we only want to go out to the PHY
  3435. * registers to see if Auto-Neg has completed and/or if our link
  3436. * status has changed. The get_link_status flag will be set if we
  3437. * receive a Link Status Change interrupt or we have Rx Sequence
  3438. * Errors.
  3439. */
  3440. if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
  3441. /* First we want to see if the MII Status Register reports
  3442. * link. If so, then we want to get the current speed/duplex
  3443. * of the PHY.
  3444. * Read the register twice since the link bit is sticky.
  3445. */
  3446. if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  3447. DEBUGOUT("PHY Read Error\n");
  3448. return -E1000_ERR_PHY;
  3449. }
  3450. if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  3451. DEBUGOUT("PHY Read Error\n");
  3452. return -E1000_ERR_PHY;
  3453. }
  3454. if (phy_data & MII_SR_LINK_STATUS) {
  3455. hw->get_link_status = false;
  3456. } else {
  3457. /* No link detected */
  3458. return -E1000_ERR_NOLINK;
  3459. }
  3460. /* We have a M88E1000 PHY and Auto-Neg is enabled. If we
  3461. * have Si on board that is 82544 or newer, Auto
  3462. * Speed Detection takes care of MAC speed/duplex
  3463. * configuration. So we only need to configure Collision
  3464. * Distance in the MAC. Otherwise, we need to force
  3465. * speed/duplex on the MAC to the current PHY speed/duplex
  3466. * settings.
  3467. */
  3468. if (hw->mac_type >= e1000_82544)
  3469. e1000_config_collision_dist(hw);
  3470. else {
  3471. ret_val = e1000_config_mac_to_phy(hw);
  3472. if (ret_val < 0) {
  3473. DEBUGOUT
  3474. ("Error configuring MAC to PHY settings\n");
  3475. return ret_val;
  3476. }
  3477. }
  3478. /* Configure Flow Control now that Auto-Neg has completed. First, we
  3479. * need to restore the desired flow control settings because we may
  3480. * have had to re-autoneg with a different link partner.
  3481. */
  3482. ret_val = e1000_config_fc_after_link_up(hw);
  3483. if (ret_val < 0) {
  3484. DEBUGOUT("Error configuring flow control\n");
  3485. return ret_val;
  3486. }
  3487. /* At this point we know that we are on copper and we have
  3488. * auto-negotiated link. These are conditions for checking the link
  3489. * parter capability register. We use the link partner capability to
  3490. * determine if TBI Compatibility needs to be turned on or off. If
  3491. * the link partner advertises any speed in addition to Gigabit, then
  3492. * we assume that they are GMII-based, and TBI compatibility is not
  3493. * needed. If no other speeds are advertised, we assume the link
  3494. * partner is TBI-based, and we turn on TBI Compatibility.
  3495. */
  3496. if (hw->tbi_compatibility_en) {
  3497. if (e1000_read_phy_reg
  3498. (hw, PHY_LP_ABILITY, &lp_capability) < 0) {
  3499. DEBUGOUT("PHY Read Error\n");
  3500. return -E1000_ERR_PHY;
  3501. }
  3502. if (lp_capability & (NWAY_LPAR_10T_HD_CAPS |
  3503. NWAY_LPAR_10T_FD_CAPS |
  3504. NWAY_LPAR_100TX_HD_CAPS |
  3505. NWAY_LPAR_100TX_FD_CAPS |
  3506. NWAY_LPAR_100T4_CAPS)) {
  3507. /* If our link partner advertises anything in addition to
  3508. * gigabit, we do not need to enable TBI compatibility.
  3509. */
  3510. if (hw->tbi_compatibility_on) {
  3511. /* If we previously were in the mode, turn it off. */
  3512. rctl = E1000_READ_REG(hw, RCTL);
  3513. rctl &= ~E1000_RCTL_SBP;
  3514. E1000_WRITE_REG(hw, RCTL, rctl);
  3515. hw->tbi_compatibility_on = false;
  3516. }
  3517. } else {
  3518. /* If TBI compatibility is was previously off, turn it on. For
  3519. * compatibility with a TBI link partner, we will store bad
  3520. * packets. Some frames have an additional byte on the end and
  3521. * will look like CRC errors to to the hardware.
  3522. */
  3523. if (!hw->tbi_compatibility_on) {
  3524. hw->tbi_compatibility_on = true;
  3525. rctl = E1000_READ_REG(hw, RCTL);
  3526. rctl |= E1000_RCTL_SBP;
  3527. E1000_WRITE_REG(hw, RCTL, rctl);
  3528. }
  3529. }
  3530. }
  3531. }
  3532. /* If we don't have link (auto-negotiation failed or link partner cannot
  3533. * auto-negotiate), the cable is plugged in (we have signal), and our
  3534. * link partner is not trying to auto-negotiate with us (we are receiving
  3535. * idles or data), we need to force link up. We also need to give
  3536. * auto-negotiation time to complete, in case the cable was just plugged
  3537. * in. The autoneg_failed flag does this.
  3538. */
  3539. else if ((hw->media_type == e1000_media_type_fiber) &&
  3540. (!(status & E1000_STATUS_LU)) &&
  3541. ((ctrl & E1000_CTRL_SWDPIN1) == signal) &&
  3542. (!(rxcw & E1000_RXCW_C))) {
  3543. if (hw->autoneg_failed == 0) {
  3544. hw->autoneg_failed = 1;
  3545. return 0;
  3546. }
  3547. DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
  3548. /* Disable auto-negotiation in the TXCW register */
  3549. E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
  3550. /* Force link-up and also force full-duplex. */
  3551. ctrl = E1000_READ_REG(hw, CTRL);
  3552. ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
  3553. E1000_WRITE_REG(hw, CTRL, ctrl);
  3554. /* Configure Flow Control after forcing link up. */
  3555. ret_val = e1000_config_fc_after_link_up(hw);
  3556. if (ret_val < 0) {
  3557. DEBUGOUT("Error configuring flow control\n");
  3558. return ret_val;
  3559. }
  3560. }
  3561. /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
  3562. * auto-negotiation in the TXCW register and disable forced link in the
  3563. * Device Control register in an attempt to auto-negotiate with our link
  3564. * partner.
  3565. */
  3566. else if ((hw->media_type == e1000_media_type_fiber) &&
  3567. (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
  3568. DEBUGOUT
  3569. ("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
  3570. E1000_WRITE_REG(hw, TXCW, hw->txcw);
  3571. E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
  3572. }
  3573. return 0;
  3574. }
  3575. /******************************************************************************
  3576. * Configure the MAC-to-PHY interface for 10/100Mbps
  3577. *
  3578. * hw - Struct containing variables accessed by shared code
  3579. ******************************************************************************/
  3580. static int32_t
  3581. e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
  3582. {
  3583. int32_t ret_val = E1000_SUCCESS;
  3584. uint32_t tipg;
  3585. uint16_t reg_data;
  3586. DEBUGFUNC();
  3587. reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
  3588. ret_val = e1000_write_kmrn_reg(hw,
  3589. E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
  3590. if (ret_val)
  3591. return ret_val;
  3592. /* Configure Transmit Inter-Packet Gap */
  3593. tipg = E1000_READ_REG(hw, TIPG);
  3594. tipg &= ~E1000_TIPG_IPGT_MASK;
  3595. tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
  3596. E1000_WRITE_REG(hw, TIPG, tipg);
  3597. ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
  3598. if (ret_val)
  3599. return ret_val;
  3600. if (duplex == HALF_DUPLEX)
  3601. reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
  3602. else
  3603. reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
  3604. ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
  3605. return ret_val;
  3606. }
  3607. static int32_t
  3608. e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
  3609. {
  3610. int32_t ret_val = E1000_SUCCESS;
  3611. uint16_t reg_data;
  3612. uint32_t tipg;
  3613. DEBUGFUNC();
  3614. reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
  3615. ret_val = e1000_write_kmrn_reg(hw,
  3616. E1000_KUMCTRLSTA_OFFSET_HD_CTRL, reg_data);
  3617. if (ret_val)
  3618. return ret_val;
  3619. /* Configure Transmit Inter-Packet Gap */
  3620. tipg = E1000_READ_REG(hw, TIPG);
  3621. tipg &= ~E1000_TIPG_IPGT_MASK;
  3622. tipg |= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
  3623. E1000_WRITE_REG(hw, TIPG, tipg);
  3624. ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
  3625. if (ret_val)
  3626. return ret_val;
  3627. reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
  3628. ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
  3629. return ret_val;
  3630. }
  3631. /******************************************************************************
  3632. * Detects the current speed and duplex settings of the hardware.
  3633. *
  3634. * hw - Struct containing variables accessed by shared code
  3635. * speed - Speed of the connection
  3636. * duplex - Duplex setting of the connection
  3637. *****************************************************************************/
  3638. static int
  3639. e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed,
  3640. uint16_t *duplex)
  3641. {
  3642. uint32_t status;
  3643. int32_t ret_val;
  3644. uint16_t phy_data;
  3645. DEBUGFUNC();
  3646. if (hw->mac_type >= e1000_82543) {
  3647. status = E1000_READ_REG(hw, STATUS);
  3648. if (status & E1000_STATUS_SPEED_1000) {
  3649. *speed = SPEED_1000;
  3650. DEBUGOUT("1000 Mbs, ");
  3651. } else if (status & E1000_STATUS_SPEED_100) {
  3652. *speed = SPEED_100;
  3653. DEBUGOUT("100 Mbs, ");
  3654. } else {
  3655. *speed = SPEED_10;
  3656. DEBUGOUT("10 Mbs, ");
  3657. }
  3658. if (status & E1000_STATUS_FD) {
  3659. *duplex = FULL_DUPLEX;
  3660. DEBUGOUT("Full Duplex\r\n");
  3661. } else {
  3662. *duplex = HALF_DUPLEX;
  3663. DEBUGOUT(" Half Duplex\r\n");
  3664. }
  3665. } else {
  3666. DEBUGOUT("1000 Mbs, Full Duplex\r\n");
  3667. *speed = SPEED_1000;
  3668. *duplex = FULL_DUPLEX;
  3669. }
  3670. /* IGP01 PHY may advertise full duplex operation after speed downgrade
  3671. * even if it is operating at half duplex. Here we set the duplex
  3672. * settings to match the duplex in the link partner's capabilities.
  3673. */
  3674. if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
  3675. ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
  3676. if (ret_val)
  3677. return ret_val;
  3678. if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
  3679. *duplex = HALF_DUPLEX;
  3680. else {
  3681. ret_val = e1000_read_phy_reg(hw,
  3682. PHY_LP_ABILITY, &phy_data);
  3683. if (ret_val)
  3684. return ret_val;
  3685. if ((*speed == SPEED_100 &&
  3686. !(phy_data & NWAY_LPAR_100TX_FD_CAPS))
  3687. || (*speed == SPEED_10
  3688. && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
  3689. *duplex = HALF_DUPLEX;
  3690. }
  3691. }
  3692. if ((hw->mac_type == e1000_80003es2lan) &&
  3693. (hw->media_type == e1000_media_type_copper)) {
  3694. if (*speed == SPEED_1000)
  3695. ret_val = e1000_configure_kmrn_for_1000(hw);
  3696. else
  3697. ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
  3698. if (ret_val)
  3699. return ret_val;
  3700. }
  3701. return E1000_SUCCESS;
  3702. }
  3703. /******************************************************************************
  3704. * Blocks until autoneg completes or times out (~4.5 seconds)
  3705. *
  3706. * hw - Struct containing variables accessed by shared code
  3707. ******************************************************************************/
  3708. static int
  3709. e1000_wait_autoneg(struct e1000_hw *hw)
  3710. {
  3711. uint16_t i;
  3712. uint16_t phy_data;
  3713. DEBUGFUNC();
  3714. DEBUGOUT("Waiting for Auto-Neg to complete.\n");
  3715. /* We will wait for autoneg to complete or timeout to expire. */
  3716. for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
  3717. /* Read the MII Status Register and wait for Auto-Neg
  3718. * Complete bit to be set.
  3719. */
  3720. if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  3721. DEBUGOUT("PHY Read Error\n");
  3722. return -E1000_ERR_PHY;
  3723. }
  3724. if (e1000_read_phy_reg(hw, PHY_STATUS, &phy_data) < 0) {
  3725. DEBUGOUT("PHY Read Error\n");
  3726. return -E1000_ERR_PHY;
  3727. }
  3728. if (phy_data & MII_SR_AUTONEG_COMPLETE) {
  3729. DEBUGOUT("Auto-Neg complete.\n");
  3730. return 0;
  3731. }
  3732. mdelay(100);
  3733. }
  3734. DEBUGOUT("Auto-Neg timedout.\n");
  3735. return -E1000_ERR_TIMEOUT;
  3736. }
  3737. /******************************************************************************
  3738. * Raises the Management Data Clock
  3739. *
  3740. * hw - Struct containing variables accessed by shared code
  3741. * ctrl - Device control register's current value
  3742. ******************************************************************************/
  3743. static void
  3744. e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
  3745. {
  3746. /* Raise the clock input to the Management Data Clock (by setting the MDC
  3747. * bit), and then delay 2 microseconds.
  3748. */
  3749. E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
  3750. E1000_WRITE_FLUSH(hw);
  3751. udelay(2);
  3752. }
  3753. /******************************************************************************
  3754. * Lowers the Management Data Clock
  3755. *
  3756. * hw - Struct containing variables accessed by shared code
  3757. * ctrl - Device control register's current value
  3758. ******************************************************************************/
  3759. static void
  3760. e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl)
  3761. {
  3762. /* Lower the clock input to the Management Data Clock (by clearing the MDC
  3763. * bit), and then delay 2 microseconds.
  3764. */
  3765. E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
  3766. E1000_WRITE_FLUSH(hw);
  3767. udelay(2);
  3768. }
  3769. /******************************************************************************
  3770. * Shifts data bits out to the PHY
  3771. *
  3772. * hw - Struct containing variables accessed by shared code
  3773. * data - Data to send out to the PHY
  3774. * count - Number of bits to shift out
  3775. *
  3776. * Bits are shifted out in MSB to LSB order.
  3777. ******************************************************************************/
  3778. static void
  3779. e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data, uint16_t count)
  3780. {
  3781. uint32_t ctrl;
  3782. uint32_t mask;
  3783. /* We need to shift "count" number of bits out to the PHY. So, the value
  3784. * in the "data" parameter will be shifted out to the PHY one bit at a
  3785. * time. In order to do this, "data" must be broken down into bits.
  3786. */
  3787. mask = 0x01;
  3788. mask <<= (count - 1);
  3789. ctrl = E1000_READ_REG(hw, CTRL);
  3790. /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
  3791. ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
  3792. while (mask) {
  3793. /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
  3794. * then raising and lowering the Management Data Clock. A "0" is
  3795. * shifted out to the PHY by setting the MDIO bit to "0" and then
  3796. * raising and lowering the clock.
  3797. */
  3798. if (data & mask)
  3799. ctrl |= E1000_CTRL_MDIO;
  3800. else
  3801. ctrl &= ~E1000_CTRL_MDIO;
  3802. E1000_WRITE_REG(hw, CTRL, ctrl);
  3803. E1000_WRITE_FLUSH(hw);
  3804. udelay(2);
  3805. e1000_raise_mdi_clk(hw, &ctrl);
  3806. e1000_lower_mdi_clk(hw, &ctrl);
  3807. mask = mask >> 1;
  3808. }
  3809. }
  3810. /******************************************************************************
  3811. * Shifts data bits in from the PHY
  3812. *
  3813. * hw - Struct containing variables accessed by shared code
  3814. *
  3815. * Bits are shifted in in MSB to LSB order.
  3816. ******************************************************************************/
  3817. static uint16_t
  3818. e1000_shift_in_mdi_bits(struct e1000_hw *hw)
  3819. {
  3820. uint32_t ctrl;
  3821. uint16_t data = 0;
  3822. uint8_t i;
  3823. /* In order to read a register from the PHY, we need to shift in a total
  3824. * of 18 bits from the PHY. The first two bit (turnaround) times are used
  3825. * to avoid contention on the MDIO pin when a read operation is performed.
  3826. * These two bits are ignored by us and thrown away. Bits are "shifted in"
  3827. * by raising the input to the Management Data Clock (setting the MDC bit),
  3828. * and then reading the value of the MDIO bit.
  3829. */
  3830. ctrl = E1000_READ_REG(hw, CTRL);
  3831. /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
  3832. ctrl &= ~E1000_CTRL_MDIO_DIR;
  3833. ctrl &= ~E1000_CTRL_MDIO;
  3834. E1000_WRITE_REG(hw, CTRL, ctrl);
  3835. E1000_WRITE_FLUSH(hw);
  3836. /* Raise and Lower the clock before reading in the data. This accounts for
  3837. * the turnaround bits. The first clock occurred when we clocked out the
  3838. * last bit of the Register Address.
  3839. */
  3840. e1000_raise_mdi_clk(hw, &ctrl);
  3841. e1000_lower_mdi_clk(hw, &ctrl);
  3842. for (data = 0, i = 0; i < 16; i++) {
  3843. data = data << 1;
  3844. e1000_raise_mdi_clk(hw, &ctrl);
  3845. ctrl = E1000_READ_REG(hw, CTRL);
  3846. /* Check to see if we shifted in a "1". */
  3847. if (ctrl & E1000_CTRL_MDIO)
  3848. data |= 1;
  3849. e1000_lower_mdi_clk(hw, &ctrl);
  3850. }
  3851. e1000_raise_mdi_clk(hw, &ctrl);
  3852. e1000_lower_mdi_clk(hw, &ctrl);
  3853. return data;
  3854. }
  3855. /*****************************************************************************
  3856. * Reads the value from a PHY register
  3857. *
  3858. * hw - Struct containing variables accessed by shared code
  3859. * reg_addr - address of the PHY register to read
  3860. ******************************************************************************/
  3861. static int
  3862. e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t * phy_data)
  3863. {
  3864. uint32_t i;
  3865. uint32_t mdic = 0;
  3866. const uint32_t phy_addr = 1;
  3867. if (reg_addr > MAX_PHY_REG_ADDRESS) {
  3868. DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
  3869. return -E1000_ERR_PARAM;
  3870. }
  3871. if (hw->mac_type > e1000_82543) {
  3872. /* Set up Op-code, Phy Address, and register address in the MDI
  3873. * Control register. The MAC will take care of interfacing with the
  3874. * PHY to retrieve the desired data.
  3875. */
  3876. mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
  3877. (phy_addr << E1000_MDIC_PHY_SHIFT) |
  3878. (E1000_MDIC_OP_READ));
  3879. E1000_WRITE_REG(hw, MDIC, mdic);
  3880. /* Poll the ready bit to see if the MDI read completed */
  3881. for (i = 0; i < 64; i++) {
  3882. udelay(10);
  3883. mdic = E1000_READ_REG(hw, MDIC);
  3884. if (mdic & E1000_MDIC_READY)
  3885. break;
  3886. }
  3887. if (!(mdic & E1000_MDIC_READY)) {
  3888. DEBUGOUT("MDI Read did not complete\n");
  3889. return -E1000_ERR_PHY;
  3890. }
  3891. if (mdic & E1000_MDIC_ERROR) {
  3892. DEBUGOUT("MDI Error\n");
  3893. return -E1000_ERR_PHY;
  3894. }
  3895. *phy_data = (uint16_t) mdic;
  3896. } else {
  3897. /* We must first send a preamble through the MDIO pin to signal the
  3898. * beginning of an MII instruction. This is done by sending 32
  3899. * consecutive "1" bits.
  3900. */
  3901. e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
  3902. /* Now combine the next few fields that are required for a read
  3903. * operation. We use this method instead of calling the
  3904. * e1000_shift_out_mdi_bits routine five different times. The format of
  3905. * a MII read instruction consists of a shift out of 14 bits and is
  3906. * defined as follows:
  3907. * <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
  3908. * followed by a shift in of 18 bits. This first two bits shifted in
  3909. * are TurnAround bits used to avoid contention on the MDIO pin when a
  3910. * READ operation is performed. These two bits are thrown away
  3911. * followed by a shift in of 16 bits which contains the desired data.
  3912. */
  3913. mdic = ((reg_addr) | (phy_addr << 5) |
  3914. (PHY_OP_READ << 10) | (PHY_SOF << 12));
  3915. e1000_shift_out_mdi_bits(hw, mdic, 14);
  3916. /* Now that we've shifted out the read command to the MII, we need to
  3917. * "shift in" the 16-bit value (18 total bits) of the requested PHY
  3918. * register address.
  3919. */
  3920. *phy_data = e1000_shift_in_mdi_bits(hw);
  3921. }
  3922. return 0;
  3923. }
  3924. /******************************************************************************
  3925. * Writes a value to a PHY register
  3926. *
  3927. * hw - Struct containing variables accessed by shared code
  3928. * reg_addr - address of the PHY register to write
  3929. * data - data to write to the PHY
  3930. ******************************************************************************/
  3931. static int
  3932. e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data)
  3933. {
  3934. uint32_t i;
  3935. uint32_t mdic = 0;
  3936. const uint32_t phy_addr = 1;
  3937. if (reg_addr > MAX_PHY_REG_ADDRESS) {
  3938. DEBUGOUT("PHY Address %d is out of range\n", reg_addr);
  3939. return -E1000_ERR_PARAM;
  3940. }
  3941. if (hw->mac_type > e1000_82543) {
  3942. /* Set up Op-code, Phy Address, register address, and data intended
  3943. * for the PHY register in the MDI Control register. The MAC will take
  3944. * care of interfacing with the PHY to send the desired data.
  3945. */
  3946. mdic = (((uint32_t) phy_data) |
  3947. (reg_addr << E1000_MDIC_REG_SHIFT) |
  3948. (phy_addr << E1000_MDIC_PHY_SHIFT) |
  3949. (E1000_MDIC_OP_WRITE));
  3950. E1000_WRITE_REG(hw, MDIC, mdic);
  3951. /* Poll the ready bit to see if the MDI read completed */
  3952. for (i = 0; i < 64; i++) {
  3953. udelay(10);
  3954. mdic = E1000_READ_REG(hw, MDIC);
  3955. if (mdic & E1000_MDIC_READY)
  3956. break;
  3957. }
  3958. if (!(mdic & E1000_MDIC_READY)) {
  3959. DEBUGOUT("MDI Write did not complete\n");
  3960. return -E1000_ERR_PHY;
  3961. }
  3962. } else {
  3963. /* We'll need to use the SW defined pins to shift the write command
  3964. * out to the PHY. We first send a preamble to the PHY to signal the
  3965. * beginning of the MII instruction. This is done by sending 32
  3966. * consecutive "1" bits.
  3967. */
  3968. e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
  3969. /* Now combine the remaining required fields that will indicate a
  3970. * write operation. We use this method instead of calling the
  3971. * e1000_shift_out_mdi_bits routine for each field in the command. The
  3972. * format of a MII write instruction is as follows:
  3973. * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
  3974. */
  3975. mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
  3976. (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
  3977. mdic <<= 16;
  3978. mdic |= (uint32_t) phy_data;
  3979. e1000_shift_out_mdi_bits(hw, mdic, 32);
  3980. }
  3981. return 0;
  3982. }
  3983. /******************************************************************************
  3984. * Checks if PHY reset is blocked due to SOL/IDER session, for example.
  3985. * Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
  3986. * the caller to figure out how to deal with it.
  3987. *
  3988. * hw - Struct containing variables accessed by shared code
  3989. *
  3990. * returns: - E1000_BLK_PHY_RESET
  3991. * E1000_SUCCESS
  3992. *
  3993. *****************************************************************************/
  3994. int32_t
  3995. e1000_check_phy_reset_block(struct e1000_hw *hw)
  3996. {
  3997. uint32_t manc = 0;
  3998. uint32_t fwsm = 0;
  3999. if (hw->mac_type == e1000_ich8lan) {
  4000. fwsm = E1000_READ_REG(hw, FWSM);
  4001. return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
  4002. : E1000_BLK_PHY_RESET;
  4003. }
  4004. if (hw->mac_type > e1000_82547_rev_2)
  4005. manc = E1000_READ_REG(hw, MANC);
  4006. return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
  4007. E1000_BLK_PHY_RESET : E1000_SUCCESS;
  4008. }
  4009. /***************************************************************************
  4010. * Checks if the PHY configuration is done
  4011. *
  4012. * hw: Struct containing variables accessed by shared code
  4013. *
  4014. * returns: - E1000_ERR_RESET if fail to reset MAC
  4015. * E1000_SUCCESS at any other case.
  4016. *
  4017. ***************************************************************************/
  4018. static int32_t
  4019. e1000_get_phy_cfg_done(struct e1000_hw *hw)
  4020. {
  4021. int32_t timeout = PHY_CFG_TIMEOUT;
  4022. uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
  4023. DEBUGFUNC();
  4024. switch (hw->mac_type) {
  4025. default:
  4026. mdelay(10);
  4027. break;
  4028. case e1000_80003es2lan:
  4029. /* Separate *_CFG_DONE_* bit for each port */
  4030. if (e1000_is_second_port(hw))
  4031. cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
  4032. /* Fall Through */
  4033. case e1000_82571:
  4034. case e1000_82572:
  4035. case e1000_igb:
  4036. while (timeout) {
  4037. if (hw->mac_type == e1000_igb) {
  4038. if (E1000_READ_REG(hw, I210_EEMNGCTL) & cfg_mask)
  4039. break;
  4040. } else {
  4041. if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
  4042. break;
  4043. }
  4044. mdelay(1);
  4045. timeout--;
  4046. }
  4047. if (!timeout) {
  4048. DEBUGOUT("MNG configuration cycle has not "
  4049. "completed.\n");
  4050. return -E1000_ERR_RESET;
  4051. }
  4052. break;
  4053. }
  4054. return E1000_SUCCESS;
  4055. }
  4056. /******************************************************************************
  4057. * Returns the PHY to the power-on reset state
  4058. *
  4059. * hw - Struct containing variables accessed by shared code
  4060. ******************************************************************************/
  4061. int32_t
  4062. e1000_phy_hw_reset(struct e1000_hw *hw)
  4063. {
  4064. uint16_t swfw = E1000_SWFW_PHY0_SM;
  4065. uint32_t ctrl, ctrl_ext;
  4066. uint32_t led_ctrl;
  4067. int32_t ret_val;
  4068. DEBUGFUNC();
  4069. /* In the case of the phy reset being blocked, it's not an error, we
  4070. * simply return success without performing the reset. */
  4071. ret_val = e1000_check_phy_reset_block(hw);
  4072. if (ret_val)
  4073. return E1000_SUCCESS;
  4074. DEBUGOUT("Resetting Phy...\n");
  4075. if (hw->mac_type > e1000_82543) {
  4076. if (e1000_is_second_port(hw))
  4077. swfw = E1000_SWFW_PHY1_SM;
  4078. if (e1000_swfw_sync_acquire(hw, swfw)) {
  4079. DEBUGOUT("Unable to acquire swfw sync\n");
  4080. return -E1000_ERR_SWFW_SYNC;
  4081. }
  4082. /* Read the device control register and assert the E1000_CTRL_PHY_RST
  4083. * bit. Then, take it out of reset.
  4084. */
  4085. ctrl = E1000_READ_REG(hw, CTRL);
  4086. E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
  4087. E1000_WRITE_FLUSH(hw);
  4088. if (hw->mac_type < e1000_82571)
  4089. udelay(10);
  4090. else
  4091. udelay(100);
  4092. E1000_WRITE_REG(hw, CTRL, ctrl);
  4093. E1000_WRITE_FLUSH(hw);
  4094. if (hw->mac_type >= e1000_82571)
  4095. mdelay(10);
  4096. } else {
  4097. /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
  4098. * bit to put the PHY into reset. Then, take it out of reset.
  4099. */
  4100. ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  4101. ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
  4102. ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
  4103. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  4104. E1000_WRITE_FLUSH(hw);
  4105. mdelay(10);
  4106. ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
  4107. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  4108. E1000_WRITE_FLUSH(hw);
  4109. }
  4110. udelay(150);
  4111. if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
  4112. /* Configure activity LED after PHY reset */
  4113. led_ctrl = E1000_READ_REG(hw, LEDCTL);
  4114. led_ctrl &= IGP_ACTIVITY_LED_MASK;
  4115. led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
  4116. E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
  4117. }
  4118. e1000_swfw_sync_release(hw, swfw);
  4119. /* Wait for FW to finish PHY configuration. */
  4120. ret_val = e1000_get_phy_cfg_done(hw);
  4121. if (ret_val != E1000_SUCCESS)
  4122. return ret_val;
  4123. return ret_val;
  4124. }
  4125. /******************************************************************************
  4126. * IGP phy init script - initializes the GbE PHY
  4127. *
  4128. * hw - Struct containing variables accessed by shared code
  4129. *****************************************************************************/
  4130. static void
  4131. e1000_phy_init_script(struct e1000_hw *hw)
  4132. {
  4133. uint32_t ret_val;
  4134. uint16_t phy_saved_data;
  4135. DEBUGFUNC();
  4136. if (hw->phy_init_script) {
  4137. mdelay(20);
  4138. /* Save off the current value of register 0x2F5B to be
  4139. * restored at the end of this routine. */
  4140. ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
  4141. /* Disabled the PHY transmitter */
  4142. e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
  4143. mdelay(20);
  4144. e1000_write_phy_reg(hw, 0x0000, 0x0140);
  4145. mdelay(5);
  4146. switch (hw->mac_type) {
  4147. case e1000_82541:
  4148. case e1000_82547:
  4149. e1000_write_phy_reg(hw, 0x1F95, 0x0001);
  4150. e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
  4151. e1000_write_phy_reg(hw, 0x1F79, 0x0018);
  4152. e1000_write_phy_reg(hw, 0x1F30, 0x1600);
  4153. e1000_write_phy_reg(hw, 0x1F31, 0x0014);
  4154. e1000_write_phy_reg(hw, 0x1F32, 0x161C);
  4155. e1000_write_phy_reg(hw, 0x1F94, 0x0003);
  4156. e1000_write_phy_reg(hw, 0x1F96, 0x003F);
  4157. e1000_write_phy_reg(hw, 0x2010, 0x0008);
  4158. break;
  4159. case e1000_82541_rev_2:
  4160. case e1000_82547_rev_2:
  4161. e1000_write_phy_reg(hw, 0x1F73, 0x0099);
  4162. break;
  4163. default:
  4164. break;
  4165. }
  4166. e1000_write_phy_reg(hw, 0x0000, 0x3300);
  4167. mdelay(20);
  4168. /* Now enable the transmitter */
  4169. if (!ret_val)
  4170. e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
  4171. if (hw->mac_type == e1000_82547) {
  4172. uint16_t fused, fine, coarse;
  4173. /* Move to analog registers page */
  4174. e1000_read_phy_reg(hw,
  4175. IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
  4176. if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
  4177. e1000_read_phy_reg(hw,
  4178. IGP01E1000_ANALOG_FUSE_STATUS, &fused);
  4179. fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
  4180. coarse = fused
  4181. & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
  4182. if (coarse >
  4183. IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
  4184. coarse -=
  4185. IGP01E1000_ANALOG_FUSE_COARSE_10;
  4186. fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
  4187. } else if (coarse
  4188. == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
  4189. fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
  4190. fused = (fused
  4191. & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
  4192. (fine
  4193. & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
  4194. (coarse
  4195. & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
  4196. e1000_write_phy_reg(hw,
  4197. IGP01E1000_ANALOG_FUSE_CONTROL, fused);
  4198. e1000_write_phy_reg(hw,
  4199. IGP01E1000_ANALOG_FUSE_BYPASS,
  4200. IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
  4201. }
  4202. }
  4203. }
  4204. }
  4205. /******************************************************************************
  4206. * Resets the PHY
  4207. *
  4208. * hw - Struct containing variables accessed by shared code
  4209. *
  4210. * Sets bit 15 of the MII Control register
  4211. ******************************************************************************/
  4212. int32_t
  4213. e1000_phy_reset(struct e1000_hw *hw)
  4214. {
  4215. int32_t ret_val;
  4216. uint16_t phy_data;
  4217. DEBUGFUNC();
  4218. /* In the case of the phy reset being blocked, it's not an error, we
  4219. * simply return success without performing the reset. */
  4220. ret_val = e1000_check_phy_reset_block(hw);
  4221. if (ret_val)
  4222. return E1000_SUCCESS;
  4223. switch (hw->phy_type) {
  4224. case e1000_phy_igp:
  4225. case e1000_phy_igp_2:
  4226. case e1000_phy_igp_3:
  4227. case e1000_phy_ife:
  4228. case e1000_phy_igb:
  4229. ret_val = e1000_phy_hw_reset(hw);
  4230. if (ret_val)
  4231. return ret_val;
  4232. break;
  4233. default:
  4234. ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
  4235. if (ret_val)
  4236. return ret_val;
  4237. phy_data |= MII_CR_RESET;
  4238. ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
  4239. if (ret_val)
  4240. return ret_val;
  4241. udelay(1);
  4242. break;
  4243. }
  4244. if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2)
  4245. e1000_phy_init_script(hw);
  4246. return E1000_SUCCESS;
  4247. }
  4248. static int e1000_set_phy_type (struct e1000_hw *hw)
  4249. {
  4250. DEBUGFUNC ();
  4251. if (hw->mac_type == e1000_undefined)
  4252. return -E1000_ERR_PHY_TYPE;
  4253. switch (hw->phy_id) {
  4254. case M88E1000_E_PHY_ID:
  4255. case M88E1000_I_PHY_ID:
  4256. case M88E1011_I_PHY_ID:
  4257. case M88E1111_I_PHY_ID:
  4258. hw->phy_type = e1000_phy_m88;
  4259. break;
  4260. case IGP01E1000_I_PHY_ID:
  4261. if (hw->mac_type == e1000_82541 ||
  4262. hw->mac_type == e1000_82541_rev_2 ||
  4263. hw->mac_type == e1000_82547 ||
  4264. hw->mac_type == e1000_82547_rev_2) {
  4265. hw->phy_type = e1000_phy_igp;
  4266. break;
  4267. }
  4268. case IGP03E1000_E_PHY_ID:
  4269. hw->phy_type = e1000_phy_igp_3;
  4270. break;
  4271. case IFE_E_PHY_ID:
  4272. case IFE_PLUS_E_PHY_ID:
  4273. case IFE_C_E_PHY_ID:
  4274. hw->phy_type = e1000_phy_ife;
  4275. break;
  4276. case GG82563_E_PHY_ID:
  4277. if (hw->mac_type == e1000_80003es2lan) {
  4278. hw->phy_type = e1000_phy_gg82563;
  4279. break;
  4280. }
  4281. case BME1000_E_PHY_ID:
  4282. hw->phy_type = e1000_phy_bm;
  4283. break;
  4284. case I210_I_PHY_ID:
  4285. hw->phy_type = e1000_phy_igb;
  4286. break;
  4287. /* Fall Through */
  4288. default:
  4289. /* Should never have loaded on this device */
  4290. hw->phy_type = e1000_phy_undefined;
  4291. return -E1000_ERR_PHY_TYPE;
  4292. }
  4293. return E1000_SUCCESS;
  4294. }
  4295. /******************************************************************************
  4296. * Probes the expected PHY address for known PHY IDs
  4297. *
  4298. * hw - Struct containing variables accessed by shared code
  4299. ******************************************************************************/
  4300. static int32_t
  4301. e1000_detect_gig_phy(struct e1000_hw *hw)
  4302. {
  4303. int32_t phy_init_status, ret_val;
  4304. uint16_t phy_id_high, phy_id_low;
  4305. bool match = false;
  4306. DEBUGFUNC();
  4307. /* The 82571 firmware may still be configuring the PHY. In this
  4308. * case, we cannot access the PHY until the configuration is done. So
  4309. * we explicitly set the PHY values. */
  4310. if (hw->mac_type == e1000_82571 ||
  4311. hw->mac_type == e1000_82572) {
  4312. hw->phy_id = IGP01E1000_I_PHY_ID;
  4313. hw->phy_type = e1000_phy_igp_2;
  4314. return E1000_SUCCESS;
  4315. }
  4316. /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a
  4317. * work- around that forces PHY page 0 to be set or the reads fail.
  4318. * The rest of the code in this routine uses e1000_read_phy_reg to
  4319. * read the PHY ID. So for ESB-2 we need to have this set so our
  4320. * reads won't fail. If the attached PHY is not a e1000_phy_gg82563,
  4321. * the routines below will figure this out as well. */
  4322. if (hw->mac_type == e1000_80003es2lan)
  4323. hw->phy_type = e1000_phy_gg82563;
  4324. /* Read the PHY ID Registers to identify which PHY is onboard. */
  4325. ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
  4326. if (ret_val)
  4327. return ret_val;
  4328. hw->phy_id = (uint32_t) (phy_id_high << 16);
  4329. udelay(20);
  4330. ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
  4331. if (ret_val)
  4332. return ret_val;
  4333. hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
  4334. hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
  4335. switch (hw->mac_type) {
  4336. case e1000_82543:
  4337. if (hw->phy_id == M88E1000_E_PHY_ID)
  4338. match = true;
  4339. break;
  4340. case e1000_82544:
  4341. if (hw->phy_id == M88E1000_I_PHY_ID)
  4342. match = true;
  4343. break;
  4344. case e1000_82540:
  4345. case e1000_82545:
  4346. case e1000_82545_rev_3:
  4347. case e1000_82546:
  4348. case e1000_82546_rev_3:
  4349. if (hw->phy_id == M88E1011_I_PHY_ID)
  4350. match = true;
  4351. break;
  4352. case e1000_82541:
  4353. case e1000_82541_rev_2:
  4354. case e1000_82547:
  4355. case e1000_82547_rev_2:
  4356. if(hw->phy_id == IGP01E1000_I_PHY_ID)
  4357. match = true;
  4358. break;
  4359. case e1000_82573:
  4360. if (hw->phy_id == M88E1111_I_PHY_ID)
  4361. match = true;
  4362. break;
  4363. case e1000_82574:
  4364. if (hw->phy_id == BME1000_E_PHY_ID)
  4365. match = true;
  4366. break;
  4367. case e1000_80003es2lan:
  4368. if (hw->phy_id == GG82563_E_PHY_ID)
  4369. match = true;
  4370. break;
  4371. case e1000_ich8lan:
  4372. if (hw->phy_id == IGP03E1000_E_PHY_ID)
  4373. match = true;
  4374. if (hw->phy_id == IFE_E_PHY_ID)
  4375. match = true;
  4376. if (hw->phy_id == IFE_PLUS_E_PHY_ID)
  4377. match = true;
  4378. if (hw->phy_id == IFE_C_E_PHY_ID)
  4379. match = true;
  4380. break;
  4381. case e1000_igb:
  4382. if (hw->phy_id == I210_I_PHY_ID)
  4383. match = true;
  4384. break;
  4385. default:
  4386. DEBUGOUT("Invalid MAC type %d\n", hw->mac_type);
  4387. return -E1000_ERR_CONFIG;
  4388. }
  4389. phy_init_status = e1000_set_phy_type(hw);
  4390. if ((match) && (phy_init_status == E1000_SUCCESS)) {
  4391. DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id);
  4392. return 0;
  4393. }
  4394. DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id);
  4395. return -E1000_ERR_PHY;
  4396. }
  4397. /*****************************************************************************
  4398. * Set media type and TBI compatibility.
  4399. *
  4400. * hw - Struct containing variables accessed by shared code
  4401. * **************************************************************************/
  4402. void
  4403. e1000_set_media_type(struct e1000_hw *hw)
  4404. {
  4405. uint32_t status;
  4406. DEBUGFUNC();
  4407. if (hw->mac_type != e1000_82543) {
  4408. /* tbi_compatibility is only valid on 82543 */
  4409. hw->tbi_compatibility_en = false;
  4410. }
  4411. switch (hw->device_id) {
  4412. case E1000_DEV_ID_82545GM_SERDES:
  4413. case E1000_DEV_ID_82546GB_SERDES:
  4414. case E1000_DEV_ID_82571EB_SERDES:
  4415. case E1000_DEV_ID_82571EB_SERDES_DUAL:
  4416. case E1000_DEV_ID_82571EB_SERDES_QUAD:
  4417. case E1000_DEV_ID_82572EI_SERDES:
  4418. case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
  4419. hw->media_type = e1000_media_type_internal_serdes;
  4420. break;
  4421. default:
  4422. switch (hw->mac_type) {
  4423. case e1000_82542_rev2_0:
  4424. case e1000_82542_rev2_1:
  4425. hw->media_type = e1000_media_type_fiber;
  4426. break;
  4427. case e1000_ich8lan:
  4428. case e1000_82573:
  4429. case e1000_82574:
  4430. case e1000_igb:
  4431. /* The STATUS_TBIMODE bit is reserved or reused
  4432. * for the this device.
  4433. */
  4434. hw->media_type = e1000_media_type_copper;
  4435. break;
  4436. default:
  4437. status = E1000_READ_REG(hw, STATUS);
  4438. if (status & E1000_STATUS_TBIMODE) {
  4439. hw->media_type = e1000_media_type_fiber;
  4440. /* tbi_compatibility not valid on fiber */
  4441. hw->tbi_compatibility_en = false;
  4442. } else {
  4443. hw->media_type = e1000_media_type_copper;
  4444. }
  4445. break;
  4446. }
  4447. }
  4448. }
  4449. /**
  4450. * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
  4451. *
  4452. * e1000_sw_init initializes the Adapter private data structure.
  4453. * Fields are initialized based on PCI device information and
  4454. * OS network device settings (MTU size).
  4455. **/
  4456. static int
  4457. e1000_sw_init(struct e1000_hw *hw)
  4458. {
  4459. int result;
  4460. /* PCI config space info */
  4461. #ifdef CONFIG_DM_ETH
  4462. dm_pci_read_config16(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
  4463. dm_pci_read_config16(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
  4464. dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
  4465. &hw->subsystem_vendor_id);
  4466. dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
  4467. dm_pci_read_config8(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
  4468. dm_pci_read_config16(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
  4469. #else
  4470. pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
  4471. pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
  4472. pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
  4473. &hw->subsystem_vendor_id);
  4474. pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
  4475. pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
  4476. pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
  4477. #endif
  4478. /* identify the MAC */
  4479. result = e1000_set_mac_type(hw);
  4480. if (result) {
  4481. E1000_ERR(hw, "Unknown MAC Type\n");
  4482. return result;
  4483. }
  4484. switch (hw->mac_type) {
  4485. default:
  4486. break;
  4487. case e1000_82541:
  4488. case e1000_82547:
  4489. case e1000_82541_rev_2:
  4490. case e1000_82547_rev_2:
  4491. hw->phy_init_script = 1;
  4492. break;
  4493. }
  4494. /* flow control settings */
  4495. hw->fc_high_water = E1000_FC_HIGH_THRESH;
  4496. hw->fc_low_water = E1000_FC_LOW_THRESH;
  4497. hw->fc_pause_time = E1000_FC_PAUSE_TIME;
  4498. hw->fc_send_xon = 1;
  4499. /* Media type - copper or fiber */
  4500. hw->tbi_compatibility_en = true;
  4501. e1000_set_media_type(hw);
  4502. if (hw->mac_type >= e1000_82543) {
  4503. uint32_t status = E1000_READ_REG(hw, STATUS);
  4504. if (status & E1000_STATUS_TBIMODE) {
  4505. DEBUGOUT("fiber interface\n");
  4506. hw->media_type = e1000_media_type_fiber;
  4507. } else {
  4508. DEBUGOUT("copper interface\n");
  4509. hw->media_type = e1000_media_type_copper;
  4510. }
  4511. } else {
  4512. hw->media_type = e1000_media_type_fiber;
  4513. }
  4514. hw->wait_autoneg_complete = true;
  4515. if (hw->mac_type < e1000_82543)
  4516. hw->report_tx_early = 0;
  4517. else
  4518. hw->report_tx_early = 1;
  4519. return E1000_SUCCESS;
  4520. }
  4521. void
  4522. fill_rx(struct e1000_hw *hw)
  4523. {
  4524. struct e1000_rx_desc *rd;
  4525. unsigned long flush_start, flush_end;
  4526. rx_last = rx_tail;
  4527. rd = rx_base + rx_tail;
  4528. rx_tail = (rx_tail + 1) % 8;
  4529. memset(rd, 0, 16);
  4530. rd->buffer_addr = cpu_to_le64((unsigned long)packet);
  4531. /*
  4532. * Make sure there are no stale data in WB over this area, which
  4533. * might get written into the memory while the e1000 also writes
  4534. * into the same memory area.
  4535. */
  4536. invalidate_dcache_range((unsigned long)packet,
  4537. (unsigned long)packet + 4096);
  4538. /* Dump the DMA descriptor into RAM. */
  4539. flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
  4540. flush_end = flush_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
  4541. flush_dcache_range(flush_start, flush_end);
  4542. E1000_WRITE_REG(hw, RDT, rx_tail);
  4543. }
  4544. /**
  4545. * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
  4546. * @adapter: board private structure
  4547. *
  4548. * Configure the Tx unit of the MAC after a reset.
  4549. **/
  4550. static void
  4551. e1000_configure_tx(struct e1000_hw *hw)
  4552. {
  4553. unsigned long tctl;
  4554. unsigned long tipg, tarc;
  4555. uint32_t ipgr1, ipgr2;
  4556. E1000_WRITE_REG(hw, TDBAL, lower_32_bits((unsigned long)tx_base));
  4557. E1000_WRITE_REG(hw, TDBAH, upper_32_bits((unsigned long)tx_base));
  4558. E1000_WRITE_REG(hw, TDLEN, 128);
  4559. /* Setup the HW Tx Head and Tail descriptor pointers */
  4560. E1000_WRITE_REG(hw, TDH, 0);
  4561. E1000_WRITE_REG(hw, TDT, 0);
  4562. tx_tail = 0;
  4563. /* Set the default values for the Tx Inter Packet Gap timer */
  4564. if (hw->mac_type <= e1000_82547_rev_2 &&
  4565. (hw->media_type == e1000_media_type_fiber ||
  4566. hw->media_type == e1000_media_type_internal_serdes))
  4567. tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
  4568. else
  4569. tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
  4570. /* Set the default values for the Tx Inter Packet Gap timer */
  4571. switch (hw->mac_type) {
  4572. case e1000_82542_rev2_0:
  4573. case e1000_82542_rev2_1:
  4574. tipg = DEFAULT_82542_TIPG_IPGT;
  4575. ipgr1 = DEFAULT_82542_TIPG_IPGR1;
  4576. ipgr2 = DEFAULT_82542_TIPG_IPGR2;
  4577. break;
  4578. case e1000_80003es2lan:
  4579. ipgr1 = DEFAULT_82543_TIPG_IPGR1;
  4580. ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2;
  4581. break;
  4582. default:
  4583. ipgr1 = DEFAULT_82543_TIPG_IPGR1;
  4584. ipgr2 = DEFAULT_82543_TIPG_IPGR2;
  4585. break;
  4586. }
  4587. tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
  4588. tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
  4589. E1000_WRITE_REG(hw, TIPG, tipg);
  4590. /* Program the Transmit Control Register */
  4591. tctl = E1000_READ_REG(hw, TCTL);
  4592. tctl &= ~E1000_TCTL_CT;
  4593. tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
  4594. (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
  4595. if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) {
  4596. tarc = E1000_READ_REG(hw, TARC0);
  4597. /* set the speed mode bit, we'll clear it if we're not at
  4598. * gigabit link later */
  4599. /* git bit can be set to 1*/
  4600. } else if (hw->mac_type == e1000_80003es2lan) {
  4601. tarc = E1000_READ_REG(hw, TARC0);
  4602. tarc |= 1;
  4603. E1000_WRITE_REG(hw, TARC0, tarc);
  4604. tarc = E1000_READ_REG(hw, TARC1);
  4605. tarc |= 1;
  4606. E1000_WRITE_REG(hw, TARC1, tarc);
  4607. }
  4608. e1000_config_collision_dist(hw);
  4609. /* Setup Transmit Descriptor Settings for eop descriptor */
  4610. hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
  4611. /* Need to set up RS bit */
  4612. if (hw->mac_type < e1000_82543)
  4613. hw->txd_cmd |= E1000_TXD_CMD_RPS;
  4614. else
  4615. hw->txd_cmd |= E1000_TXD_CMD_RS;
  4616. if (hw->mac_type == e1000_igb) {
  4617. E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10);
  4618. uint32_t reg_txdctl = E1000_READ_REG(hw, TXDCTL);
  4619. reg_txdctl |= 1 << 25;
  4620. E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
  4621. mdelay(20);
  4622. }
  4623. E1000_WRITE_REG(hw, TCTL, tctl);
  4624. }
  4625. /**
  4626. * e1000_setup_rctl - configure the receive control register
  4627. * @adapter: Board private structure
  4628. **/
  4629. static void
  4630. e1000_setup_rctl(struct e1000_hw *hw)
  4631. {
  4632. uint32_t rctl;
  4633. rctl = E1000_READ_REG(hw, RCTL);
  4634. rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
  4635. rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO
  4636. | E1000_RCTL_RDMTS_HALF; /* |
  4637. (hw.mc_filter_type << E1000_RCTL_MO_SHIFT); */
  4638. if (hw->tbi_compatibility_on == 1)
  4639. rctl |= E1000_RCTL_SBP;
  4640. else
  4641. rctl &= ~E1000_RCTL_SBP;
  4642. rctl &= ~(E1000_RCTL_SZ_4096);
  4643. rctl |= E1000_RCTL_SZ_2048;
  4644. rctl &= ~(E1000_RCTL_BSEX | E1000_RCTL_LPE);
  4645. E1000_WRITE_REG(hw, RCTL, rctl);
  4646. }
  4647. /**
  4648. * e1000_configure_rx - Configure 8254x Receive Unit after Reset
  4649. * @adapter: board private structure
  4650. *
  4651. * Configure the Rx unit of the MAC after a reset.
  4652. **/
  4653. static void
  4654. e1000_configure_rx(struct e1000_hw *hw)
  4655. {
  4656. unsigned long rctl, ctrl_ext;
  4657. rx_tail = 0;
  4658. /* make sure receives are disabled while setting up the descriptors */
  4659. rctl = E1000_READ_REG(hw, RCTL);
  4660. E1000_WRITE_REG(hw, RCTL, rctl & ~E1000_RCTL_EN);
  4661. if (hw->mac_type >= e1000_82540) {
  4662. /* Set the interrupt throttling rate. Value is calculated
  4663. * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
  4664. #define MAX_INTS_PER_SEC 8000
  4665. #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
  4666. E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
  4667. }
  4668. if (hw->mac_type >= e1000_82571) {
  4669. ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
  4670. /* Reset delay timers after every interrupt */
  4671. ctrl_ext |= E1000_CTRL_EXT_INT_TIMER_CLR;
  4672. E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
  4673. E1000_WRITE_FLUSH(hw);
  4674. }
  4675. /* Setup the Base and Length of the Rx Descriptor Ring */
  4676. E1000_WRITE_REG(hw, RDBAL, lower_32_bits((unsigned long)rx_base));
  4677. E1000_WRITE_REG(hw, RDBAH, upper_32_bits((unsigned long)rx_base));
  4678. E1000_WRITE_REG(hw, RDLEN, 128);
  4679. /* Setup the HW Rx Head and Tail Descriptor Pointers */
  4680. E1000_WRITE_REG(hw, RDH, 0);
  4681. E1000_WRITE_REG(hw, RDT, 0);
  4682. /* Enable Receives */
  4683. if (hw->mac_type == e1000_igb) {
  4684. uint32_t reg_rxdctl = E1000_READ_REG(hw, RXDCTL);
  4685. reg_rxdctl |= 1 << 25;
  4686. E1000_WRITE_REG(hw, RXDCTL, reg_rxdctl);
  4687. mdelay(20);
  4688. }
  4689. E1000_WRITE_REG(hw, RCTL, rctl);
  4690. fill_rx(hw);
  4691. }
  4692. /**************************************************************************
  4693. POLL - Wait for a frame
  4694. ***************************************************************************/
  4695. static int
  4696. _e1000_poll(struct e1000_hw *hw)
  4697. {
  4698. struct e1000_rx_desc *rd;
  4699. unsigned long inval_start, inval_end;
  4700. uint32_t len;
  4701. /* return true if there's an ethernet packet ready to read */
  4702. rd = rx_base + rx_last;
  4703. /* Re-load the descriptor from RAM. */
  4704. inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1);
  4705. inval_end = inval_start + roundup(sizeof(*rd), ARCH_DMA_MINALIGN);
  4706. invalidate_dcache_range(inval_start, inval_end);
  4707. if (!(rd->status & E1000_RXD_STAT_DD))
  4708. return 0;
  4709. /* DEBUGOUT("recv: packet len=%d\n", rd->length); */
  4710. /* Packet received, make sure the data are re-loaded from RAM. */
  4711. len = le16_to_cpu(rd->length);
  4712. invalidate_dcache_range((unsigned long)packet,
  4713. (unsigned long)packet +
  4714. roundup(len, ARCH_DMA_MINALIGN));
  4715. return len;
  4716. }
  4717. static int _e1000_transmit(struct e1000_hw *hw, void *txpacket, int length)
  4718. {
  4719. void *nv_packet = (void *)txpacket;
  4720. struct e1000_tx_desc *txp;
  4721. int i = 0;
  4722. unsigned long flush_start, flush_end;
  4723. txp = tx_base + tx_tail;
  4724. tx_tail = (tx_tail + 1) % 8;
  4725. txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet));
  4726. txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
  4727. txp->upper.data = 0;
  4728. /* Dump the packet into RAM so e1000 can pick them. */
  4729. flush_dcache_range((unsigned long)nv_packet,
  4730. (unsigned long)nv_packet +
  4731. roundup(length, ARCH_DMA_MINALIGN));
  4732. /* Dump the descriptor into RAM as well. */
  4733. flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1);
  4734. flush_end = flush_start + roundup(sizeof(*txp), ARCH_DMA_MINALIGN);
  4735. flush_dcache_range(flush_start, flush_end);
  4736. E1000_WRITE_REG(hw, TDT, tx_tail);
  4737. E1000_WRITE_FLUSH(hw);
  4738. while (1) {
  4739. invalidate_dcache_range(flush_start, flush_end);
  4740. if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD)
  4741. break;
  4742. if (i++ > TOUT_LOOP) {
  4743. DEBUGOUT("e1000: tx timeout\n");
  4744. return 0;
  4745. }
  4746. udelay(10); /* give the nic a chance to write to the register */
  4747. }
  4748. return 1;
  4749. }
  4750. static void
  4751. _e1000_disable(struct e1000_hw *hw)
  4752. {
  4753. /* Turn off the ethernet interface */
  4754. E1000_WRITE_REG(hw, RCTL, 0);
  4755. E1000_WRITE_REG(hw, TCTL, 0);
  4756. /* Clear the transmit ring */
  4757. E1000_WRITE_REG(hw, TDH, 0);
  4758. E1000_WRITE_REG(hw, TDT, 0);
  4759. /* Clear the receive ring */
  4760. E1000_WRITE_REG(hw, RDH, 0);
  4761. E1000_WRITE_REG(hw, RDT, 0);
  4762. mdelay(10);
  4763. }
  4764. /*reset function*/
  4765. static inline int
  4766. e1000_reset(struct e1000_hw *hw, unsigned char enetaddr[6])
  4767. {
  4768. e1000_reset_hw(hw);
  4769. if (hw->mac_type >= e1000_82544)
  4770. E1000_WRITE_REG(hw, WUC, 0);
  4771. return e1000_init_hw(hw, enetaddr);
  4772. }
  4773. static int
  4774. _e1000_init(struct e1000_hw *hw, unsigned char enetaddr[6])
  4775. {
  4776. int ret_val = 0;
  4777. ret_val = e1000_reset(hw, enetaddr);
  4778. if (ret_val < 0) {
  4779. if ((ret_val == -E1000_ERR_NOLINK) ||
  4780. (ret_val == -E1000_ERR_TIMEOUT)) {
  4781. E1000_ERR(hw, "Valid Link not detected: %d\n", ret_val);
  4782. } else {
  4783. E1000_ERR(hw, "Hardware Initialization Failed\n");
  4784. }
  4785. return ret_val;
  4786. }
  4787. e1000_configure_tx(hw);
  4788. e1000_setup_rctl(hw);
  4789. e1000_configure_rx(hw);
  4790. return 0;
  4791. }
  4792. /******************************************************************************
  4793. * Gets the current PCI bus type of hardware
  4794. *
  4795. * hw - Struct containing variables accessed by shared code
  4796. *****************************************************************************/
  4797. void e1000_get_bus_type(struct e1000_hw *hw)
  4798. {
  4799. uint32_t status;
  4800. switch (hw->mac_type) {
  4801. case e1000_82542_rev2_0:
  4802. case e1000_82542_rev2_1:
  4803. hw->bus_type = e1000_bus_type_pci;
  4804. break;
  4805. case e1000_82571:
  4806. case e1000_82572:
  4807. case e1000_82573:
  4808. case e1000_82574:
  4809. case e1000_80003es2lan:
  4810. case e1000_ich8lan:
  4811. case e1000_igb:
  4812. hw->bus_type = e1000_bus_type_pci_express;
  4813. break;
  4814. default:
  4815. status = E1000_READ_REG(hw, STATUS);
  4816. hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
  4817. e1000_bus_type_pcix : e1000_bus_type_pci;
  4818. break;
  4819. }
  4820. }
  4821. #ifndef CONFIG_DM_ETH
  4822. /* A list of all registered e1000 devices */
  4823. static LIST_HEAD(e1000_hw_list);
  4824. #endif
  4825. #ifdef CONFIG_DM_ETH
  4826. static int e1000_init_one(struct e1000_hw *hw, int cardnum,
  4827. struct udevice *devno, unsigned char enetaddr[6])
  4828. #else
  4829. static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno,
  4830. unsigned char enetaddr[6])
  4831. #endif
  4832. {
  4833. u32 val;
  4834. /* Assign the passed-in values */
  4835. #ifdef CONFIG_DM_ETH
  4836. hw->pdev = devno;
  4837. #else
  4838. hw->pdev = devno;
  4839. #endif
  4840. hw->cardnum = cardnum;
  4841. /* Print a debug message with the IO base address */
  4842. #ifdef CONFIG_DM_ETH
  4843. dm_pci_read_config32(devno, PCI_BASE_ADDRESS_0, &val);
  4844. #else
  4845. pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val);
  4846. #endif
  4847. E1000_DBG(hw, "iobase 0x%08x\n", val & 0xfffffff0);
  4848. /* Try to enable I/O accesses and bus-mastering */
  4849. val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
  4850. #ifdef CONFIG_DM_ETH
  4851. dm_pci_write_config32(devno, PCI_COMMAND, val);
  4852. #else
  4853. pci_write_config_dword(devno, PCI_COMMAND, val);
  4854. #endif
  4855. /* Make sure it worked */
  4856. #ifdef CONFIG_DM_ETH
  4857. dm_pci_read_config32(devno, PCI_COMMAND, &val);
  4858. #else
  4859. pci_read_config_dword(devno, PCI_COMMAND, &val);
  4860. #endif
  4861. if (!(val & PCI_COMMAND_MEMORY)) {
  4862. E1000_ERR(hw, "Can't enable I/O memory\n");
  4863. return -ENOSPC;
  4864. }
  4865. if (!(val & PCI_COMMAND_MASTER)) {
  4866. E1000_ERR(hw, "Can't enable bus-mastering\n");
  4867. return -EPERM;
  4868. }
  4869. /* Are these variables needed? */
  4870. hw->fc = e1000_fc_default;
  4871. hw->original_fc = e1000_fc_default;
  4872. hw->autoneg_failed = 0;
  4873. hw->autoneg = 1;
  4874. hw->get_link_status = true;
  4875. #ifndef CONFIG_E1000_NO_NVM
  4876. hw->eeprom_semaphore_present = true;
  4877. #endif
  4878. #ifdef CONFIG_DM_ETH
  4879. hw->hw_addr = dm_pci_map_bar(devno, PCI_BASE_ADDRESS_0,
  4880. PCI_REGION_MEM);
  4881. #else
  4882. hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
  4883. PCI_REGION_MEM);
  4884. #endif
  4885. hw->mac_type = e1000_undefined;
  4886. /* MAC and Phy settings */
  4887. if (e1000_sw_init(hw) < 0) {
  4888. E1000_ERR(hw, "Software init failed\n");
  4889. return -EIO;
  4890. }
  4891. if (e1000_check_phy_reset_block(hw))
  4892. E1000_ERR(hw, "PHY Reset is blocked!\n");
  4893. /* Basic init was OK, reset the hardware and allow SPI access */
  4894. e1000_reset_hw(hw);
  4895. #ifndef CONFIG_E1000_NO_NVM
  4896. /* Validate the EEPROM and get chipset information */
  4897. if (e1000_init_eeprom_params(hw)) {
  4898. E1000_ERR(hw, "EEPROM is invalid!\n");
  4899. return -EINVAL;
  4900. }
  4901. if ((E1000_READ_REG(hw, I210_EECD) & E1000_EECD_FLUPD) &&
  4902. e1000_validate_eeprom_checksum(hw))
  4903. return -ENXIO;
  4904. e1000_read_mac_addr(hw, enetaddr);
  4905. #endif
  4906. e1000_get_bus_type(hw);
  4907. #ifndef CONFIG_E1000_NO_NVM
  4908. printf("e1000: %02x:%02x:%02x:%02x:%02x:%02x\n ",
  4909. enetaddr[0], enetaddr[1], enetaddr[2],
  4910. enetaddr[3], enetaddr[4], enetaddr[5]);
  4911. #else
  4912. memset(enetaddr, 0, 6);
  4913. printf("e1000: no NVM\n");
  4914. #endif
  4915. return 0;
  4916. }
  4917. /* Put the name of a device in a string */
  4918. static void e1000_name(char *str, int cardnum)
  4919. {
  4920. sprintf(str, "e1000#%u", cardnum);
  4921. }
  4922. #ifndef CONFIG_DM_ETH
  4923. /**************************************************************************
  4924. TRANSMIT - Transmit a frame
  4925. ***************************************************************************/
  4926. static int e1000_transmit(struct eth_device *nic, void *txpacket, int length)
  4927. {
  4928. struct e1000_hw *hw = nic->priv;
  4929. return _e1000_transmit(hw, txpacket, length);
  4930. }
  4931. /**************************************************************************
  4932. DISABLE - Turn off ethernet interface
  4933. ***************************************************************************/
  4934. static void
  4935. e1000_disable(struct eth_device *nic)
  4936. {
  4937. struct e1000_hw *hw = nic->priv;
  4938. _e1000_disable(hw);
  4939. }
  4940. /**************************************************************************
  4941. INIT - set up ethernet interface(s)
  4942. ***************************************************************************/
  4943. static int
  4944. e1000_init(struct eth_device *nic, bd_t *bis)
  4945. {
  4946. struct e1000_hw *hw = nic->priv;
  4947. return _e1000_init(hw, nic->enetaddr);
  4948. }
  4949. static int
  4950. e1000_poll(struct eth_device *nic)
  4951. {
  4952. struct e1000_hw *hw = nic->priv;
  4953. int len;
  4954. len = _e1000_poll(hw);
  4955. if (len) {
  4956. net_process_received_packet((uchar *)packet, len);
  4957. fill_rx(hw);
  4958. }
  4959. return len ? 1 : 0;
  4960. }
  4961. static int e1000_write_hwaddr(struct eth_device *dev)
  4962. {
  4963. #ifndef CONFIG_E1000_NO_NVM
  4964. unsigned char *mac = dev->enetaddr;
  4965. unsigned char current_mac[6];
  4966. struct e1000_hw *hw = dev->priv;
  4967. uint16_t data[3];
  4968. int ret_val, i;
  4969. DEBUGOUT("%s: mac=%pM\n", __func__, mac);
  4970. memset(current_mac, 0, 6);
  4971. /* Read from EEPROM, not from registers, to make sure
  4972. * the address is persistently configured
  4973. */
  4974. ret_val = e1000_read_mac_addr_from_eeprom(hw, current_mac);
  4975. DEBUGOUT("%s: current mac=%pM\n", __func__, current_mac);
  4976. /* Only write to EEPROM if the given address is different or
  4977. * reading the current address failed
  4978. */
  4979. if (!ret_val && memcmp(current_mac, mac, 6) == 0)
  4980. return 0;
  4981. for (i = 0; i < 3; ++i)
  4982. data[i] = mac[i * 2 + 1] << 8 | mac[i * 2];
  4983. ret_val = e1000_write_eeprom_srwr(hw, 0x0, 3, data);
  4984. if (!ret_val)
  4985. ret_val = e1000_update_eeprom_checksum_i210(hw);
  4986. return ret_val;
  4987. #else
  4988. return 0;
  4989. #endif
  4990. }
  4991. /**************************************************************************
  4992. PROBE - Look for an adapter, this routine's visible to the outside
  4993. You should omit the last argument struct pci_device * for a non-PCI NIC
  4994. ***************************************************************************/
  4995. int
  4996. e1000_initialize(bd_t * bis)
  4997. {
  4998. unsigned int i;
  4999. pci_dev_t devno;
  5000. int ret;
  5001. DEBUGFUNC();
  5002. /* Find and probe all the matching PCI devices */
  5003. for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) {
  5004. /*
  5005. * These will never get freed due to errors, this allows us to
  5006. * perform SPI EEPROM programming from U-Boot, for example.
  5007. */
  5008. struct eth_device *nic = malloc(sizeof(*nic));
  5009. struct e1000_hw *hw = malloc(sizeof(*hw));
  5010. if (!nic || !hw) {
  5011. printf("e1000#%u: Out of Memory!\n", i);
  5012. free(nic);
  5013. free(hw);
  5014. continue;
  5015. }
  5016. /* Make sure all of the fields are initially zeroed */
  5017. memset(nic, 0, sizeof(*nic));
  5018. memset(hw, 0, sizeof(*hw));
  5019. nic->priv = hw;
  5020. /* Generate a card name */
  5021. e1000_name(nic->name, i);
  5022. hw->name = nic->name;
  5023. ret = e1000_init_one(hw, i, devno, nic->enetaddr);
  5024. if (ret)
  5025. continue;
  5026. list_add_tail(&hw->list_node, &e1000_hw_list);
  5027. hw->nic = nic;
  5028. /* Set up the function pointers and register the device */
  5029. nic->init = e1000_init;
  5030. nic->recv = e1000_poll;
  5031. nic->send = e1000_transmit;
  5032. nic->halt = e1000_disable;
  5033. nic->write_hwaddr = e1000_write_hwaddr;
  5034. eth_register(nic);
  5035. }
  5036. return i;
  5037. }
  5038. struct e1000_hw *e1000_find_card(unsigned int cardnum)
  5039. {
  5040. struct e1000_hw *hw;
  5041. list_for_each_entry(hw, &e1000_hw_list, list_node)
  5042. if (hw->cardnum == cardnum)
  5043. return hw;
  5044. return NULL;
  5045. }
  5046. #endif /* !CONFIG_DM_ETH */
  5047. #ifdef CONFIG_CMD_E1000
  5048. static int do_e1000(cmd_tbl_t *cmdtp, int flag,
  5049. int argc, char * const argv[])
  5050. {
  5051. unsigned char *mac = NULL;
  5052. #ifdef CONFIG_DM_ETH
  5053. struct eth_pdata *plat;
  5054. struct udevice *dev;
  5055. char name[30];
  5056. int ret;
  5057. #endif
  5058. #if !defined(CONFIG_DM_ETH) || defined(CONFIG_E1000_SPI)
  5059. struct e1000_hw *hw;
  5060. #endif
  5061. int cardnum;
  5062. if (argc < 3) {
  5063. cmd_usage(cmdtp);
  5064. return 1;
  5065. }
  5066. /* Make sure we can find the requested e1000 card */
  5067. cardnum = simple_strtoul(argv[1], NULL, 10);
  5068. #ifdef CONFIG_DM_ETH
  5069. e1000_name(name, cardnum);
  5070. ret = uclass_get_device_by_name(UCLASS_ETH, name, &dev);
  5071. if (!ret) {
  5072. plat = dev_get_platdata(dev);
  5073. mac = plat->enetaddr;
  5074. }
  5075. #else
  5076. hw = e1000_find_card(cardnum);
  5077. if (hw)
  5078. mac = hw->nic->enetaddr;
  5079. #endif
  5080. if (!mac) {
  5081. printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]);
  5082. return 1;
  5083. }
  5084. if (!strcmp(argv[2], "print-mac-address")) {
  5085. printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
  5086. mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
  5087. return 0;
  5088. }
  5089. #ifdef CONFIG_E1000_SPI
  5090. #ifdef CONFIG_DM_ETH
  5091. hw = dev_get_priv(dev);
  5092. #endif
  5093. /* Handle the "SPI" subcommand */
  5094. if (!strcmp(argv[2], "spi"))
  5095. return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3);
  5096. #endif
  5097. cmd_usage(cmdtp);
  5098. return 1;
  5099. }
  5100. U_BOOT_CMD(
  5101. e1000, 7, 0, do_e1000,
  5102. "Intel e1000 controller management",
  5103. /* */"<card#> print-mac-address\n"
  5104. #ifdef CONFIG_E1000_SPI
  5105. "e1000 <card#> spi show [<offset> [<length>]]\n"
  5106. "e1000 <card#> spi dump <addr> <offset> <length>\n"
  5107. "e1000 <card#> spi program <addr> <offset> <length>\n"
  5108. "e1000 <card#> spi checksum [update]\n"
  5109. #endif
  5110. " - Manage the Intel E1000 PCI device"
  5111. );
  5112. #endif /* not CONFIG_CMD_E1000 */
  5113. #ifdef CONFIG_DM_ETH
  5114. static int e1000_eth_start(struct udevice *dev)
  5115. {
  5116. struct eth_pdata *plat = dev_get_platdata(dev);
  5117. struct e1000_hw *hw = dev_get_priv(dev);
  5118. return _e1000_init(hw, plat->enetaddr);
  5119. }
  5120. static void e1000_eth_stop(struct udevice *dev)
  5121. {
  5122. struct e1000_hw *hw = dev_get_priv(dev);
  5123. _e1000_disable(hw);
  5124. }
  5125. static int e1000_eth_send(struct udevice *dev, void *packet, int length)
  5126. {
  5127. struct e1000_hw *hw = dev_get_priv(dev);
  5128. int ret;
  5129. ret = _e1000_transmit(hw, packet, length);
  5130. return ret ? 0 : -ETIMEDOUT;
  5131. }
  5132. static int e1000_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  5133. {
  5134. struct e1000_hw *hw = dev_get_priv(dev);
  5135. int len;
  5136. len = _e1000_poll(hw);
  5137. if (len)
  5138. *packetp = packet;
  5139. return len ? len : -EAGAIN;
  5140. }
  5141. static int e1000_free_pkt(struct udevice *dev, uchar *packet, int length)
  5142. {
  5143. struct e1000_hw *hw = dev_get_priv(dev);
  5144. fill_rx(hw);
  5145. return 0;
  5146. }
  5147. static int e1000_eth_probe(struct udevice *dev)
  5148. {
  5149. struct eth_pdata *plat = dev_get_platdata(dev);
  5150. struct e1000_hw *hw = dev_get_priv(dev);
  5151. int ret;
  5152. hw->name = dev->name;
  5153. ret = e1000_init_one(hw, trailing_strtol(dev->name),
  5154. dev, plat->enetaddr);
  5155. if (ret < 0) {
  5156. printf(pr_fmt("failed to initialize card: %d\n"), ret);
  5157. return ret;
  5158. }
  5159. return 0;
  5160. }
  5161. static int e1000_eth_bind(struct udevice *dev)
  5162. {
  5163. char name[20];
  5164. /*
  5165. * A simple way to number the devices. When device tree is used this
  5166. * is unnecessary, but when the device is just discovered on the PCI
  5167. * bus we need a name. We could instead have the uclass figure out
  5168. * which devices are different and number them.
  5169. */
  5170. e1000_name(name, num_cards++);
  5171. return device_set_name(dev, name);
  5172. }
  5173. static const struct eth_ops e1000_eth_ops = {
  5174. .start = e1000_eth_start,
  5175. .send = e1000_eth_send,
  5176. .recv = e1000_eth_recv,
  5177. .stop = e1000_eth_stop,
  5178. .free_pkt = e1000_free_pkt,
  5179. };
  5180. static const struct udevice_id e1000_eth_ids[] = {
  5181. { .compatible = "intel,e1000" },
  5182. { }
  5183. };
  5184. U_BOOT_DRIVER(eth_e1000) = {
  5185. .name = "eth_e1000",
  5186. .id = UCLASS_ETH,
  5187. .of_match = e1000_eth_ids,
  5188. .bind = e1000_eth_bind,
  5189. .probe = e1000_eth_probe,
  5190. .ops = &e1000_eth_ops,
  5191. .priv_auto_alloc_size = sizeof(struct e1000_hw),
  5192. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  5193. };
  5194. U_BOOT_PCI_DEVICE(eth_e1000, e1000_supported);
  5195. #endif