dwc_eth_qos.c 50 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2016, NVIDIA CORPORATION.
  4. *
  5. * Portions based on U-Boot's rtl8169.c.
  6. */
  7. /*
  8. * This driver supports the Synopsys Designware Ethernet QOS (Quality Of
  9. * Service) IP block. The IP supports multiple options for bus type, clocking/
  10. * reset structure, and feature list.
  11. *
  12. * The driver is written such that generic core logic is kept separate from
  13. * configuration-specific logic. Code that interacts with configuration-
  14. * specific resources is split out into separate functions to avoid polluting
  15. * common code. If/when this driver is enhanced to support multiple
  16. * configurations, the core code should be adapted to call all configuration-
  17. * specific functions through function pointers, with the definition of those
  18. * function pointers being supplied by struct udevice_id eqos_ids[]'s .data
  19. * field.
  20. *
  21. * The following configurations are currently supported:
  22. * tegra186:
  23. * NVIDIA's Tegra186 chip. This configuration uses an AXI master/DMA bus, an
  24. * AHB slave/register bus, contains the DMA, MTL, and MAC sub-blocks, and
  25. * supports a single RGMII PHY. This configuration also has SW control over
  26. * all clock and reset signals to the HW block.
  27. */
  28. #include <common.h>
  29. #include <clk.h>
  30. #include <cpu_func.h>
  31. #include <dm.h>
  32. #include <errno.h>
  33. #include <memalign.h>
  34. #include <miiphy.h>
  35. #include <net.h>
  36. #include <netdev.h>
  37. #include <phy.h>
  38. #include <reset.h>
  39. #include <wait_bit.h>
  40. #include <asm/gpio.h>
  41. #include <asm/io.h>
  42. /* Core registers */
  43. #define EQOS_MAC_REGS_BASE 0x000
  44. struct eqos_mac_regs {
  45. uint32_t configuration; /* 0x000 */
  46. uint32_t unused_004[(0x070 - 0x004) / 4]; /* 0x004 */
  47. uint32_t q0_tx_flow_ctrl; /* 0x070 */
  48. uint32_t unused_070[(0x090 - 0x074) / 4]; /* 0x074 */
  49. uint32_t rx_flow_ctrl; /* 0x090 */
  50. uint32_t unused_094; /* 0x094 */
  51. uint32_t txq_prty_map0; /* 0x098 */
  52. uint32_t unused_09c; /* 0x09c */
  53. uint32_t rxq_ctrl0; /* 0x0a0 */
  54. uint32_t unused_0a4; /* 0x0a4 */
  55. uint32_t rxq_ctrl2; /* 0x0a8 */
  56. uint32_t unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */
  57. uint32_t us_tic_counter; /* 0x0dc */
  58. uint32_t unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */
  59. uint32_t hw_feature0; /* 0x11c */
  60. uint32_t hw_feature1; /* 0x120 */
  61. uint32_t hw_feature2; /* 0x124 */
  62. uint32_t unused_128[(0x200 - 0x128) / 4]; /* 0x128 */
  63. uint32_t mdio_address; /* 0x200 */
  64. uint32_t mdio_data; /* 0x204 */
  65. uint32_t unused_208[(0x300 - 0x208) / 4]; /* 0x208 */
  66. uint32_t address0_high; /* 0x300 */
  67. uint32_t address0_low; /* 0x304 */
  68. };
  69. #define EQOS_MAC_CONFIGURATION_GPSLCE BIT(23)
  70. #define EQOS_MAC_CONFIGURATION_CST BIT(21)
  71. #define EQOS_MAC_CONFIGURATION_ACS BIT(20)
  72. #define EQOS_MAC_CONFIGURATION_WD BIT(19)
  73. #define EQOS_MAC_CONFIGURATION_JD BIT(17)
  74. #define EQOS_MAC_CONFIGURATION_JE BIT(16)
  75. #define EQOS_MAC_CONFIGURATION_PS BIT(15)
  76. #define EQOS_MAC_CONFIGURATION_FES BIT(14)
  77. #define EQOS_MAC_CONFIGURATION_DM BIT(13)
  78. #define EQOS_MAC_CONFIGURATION_TE BIT(1)
  79. #define EQOS_MAC_CONFIGURATION_RE BIT(0)
  80. #define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16
  81. #define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_MASK 0xffff
  82. #define EQOS_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1)
  83. #define EQOS_MAC_RX_FLOW_CTRL_RFE BIT(0)
  84. #define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT 0
  85. #define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK 0xff
  86. #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0
  87. #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3
  88. #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0
  89. #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
  90. #define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1
  91. #define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0
  92. #define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff
  93. #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6
  94. #define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK 0x1f
  95. #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0
  96. #define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK 0x1f
  97. #define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21
  98. #define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16
  99. #define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
  100. #define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
  101. #define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5
  102. #define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4)
  103. #define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT 2
  104. #define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3
  105. #define EQOS_MAC_MDIO_ADDRESS_GOC_WRITE 1
  106. #define EQOS_MAC_MDIO_ADDRESS_C45E BIT(1)
  107. #define EQOS_MAC_MDIO_ADDRESS_GB BIT(0)
  108. #define EQOS_MAC_MDIO_DATA_GD_MASK 0xffff
  109. #define EQOS_MTL_REGS_BASE 0xd00
  110. struct eqos_mtl_regs {
  111. uint32_t txq0_operation_mode; /* 0xd00 */
  112. uint32_t unused_d04; /* 0xd04 */
  113. uint32_t txq0_debug; /* 0xd08 */
  114. uint32_t unused_d0c[(0xd18 - 0xd0c) / 4]; /* 0xd0c */
  115. uint32_t txq0_quantum_weight; /* 0xd18 */
  116. uint32_t unused_d1c[(0xd30 - 0xd1c) / 4]; /* 0xd1c */
  117. uint32_t rxq0_operation_mode; /* 0xd30 */
  118. uint32_t unused_d34; /* 0xd34 */
  119. uint32_t rxq0_debug; /* 0xd38 */
  120. };
  121. #define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16
  122. #define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK 0x1ff
  123. #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2
  124. #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK 3
  125. #define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED 2
  126. #define EQOS_MTL_TXQ0_OPERATION_MODE_TSF BIT(1)
  127. #define EQOS_MTL_TXQ0_OPERATION_MODE_FTQ BIT(0)
  128. #define EQOS_MTL_TXQ0_DEBUG_TXQSTS BIT(4)
  129. #define EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT 1
  130. #define EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK 3
  131. #define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 20
  132. #define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK 0x3ff
  133. #define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT 14
  134. #define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK 0x3f
  135. #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT 8
  136. #define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK 0x3f
  137. #define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7)
  138. #define EQOS_MTL_RXQ0_OPERATION_MODE_RSF BIT(5)
  139. #define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16
  140. #define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK 0x7fff
  141. #define EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT 4
  142. #define EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK 3
  143. #define EQOS_DMA_REGS_BASE 0x1000
  144. struct eqos_dma_regs {
  145. uint32_t mode; /* 0x1000 */
  146. uint32_t sysbus_mode; /* 0x1004 */
  147. uint32_t unused_1008[(0x1100 - 0x1008) / 4]; /* 0x1008 */
  148. uint32_t ch0_control; /* 0x1100 */
  149. uint32_t ch0_tx_control; /* 0x1104 */
  150. uint32_t ch0_rx_control; /* 0x1108 */
  151. uint32_t unused_110c; /* 0x110c */
  152. uint32_t ch0_txdesc_list_haddress; /* 0x1110 */
  153. uint32_t ch0_txdesc_list_address; /* 0x1114 */
  154. uint32_t ch0_rxdesc_list_haddress; /* 0x1118 */
  155. uint32_t ch0_rxdesc_list_address; /* 0x111c */
  156. uint32_t ch0_txdesc_tail_pointer; /* 0x1120 */
  157. uint32_t unused_1124; /* 0x1124 */
  158. uint32_t ch0_rxdesc_tail_pointer; /* 0x1128 */
  159. uint32_t ch0_txdesc_ring_length; /* 0x112c */
  160. uint32_t ch0_rxdesc_ring_length; /* 0x1130 */
  161. };
  162. #define EQOS_DMA_MODE_SWR BIT(0)
  163. #define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16
  164. #define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK 0xf
  165. #define EQOS_DMA_SYSBUS_MODE_EAME BIT(11)
  166. #define EQOS_DMA_SYSBUS_MODE_BLEN16 BIT(3)
  167. #define EQOS_DMA_SYSBUS_MODE_BLEN8 BIT(2)
  168. #define EQOS_DMA_SYSBUS_MODE_BLEN4 BIT(1)
  169. #define EQOS_DMA_CH0_CONTROL_PBLX8 BIT(16)
  170. #define EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16
  171. #define EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK 0x3f
  172. #define EQOS_DMA_CH0_TX_CONTROL_OSP BIT(4)
  173. #define EQOS_DMA_CH0_TX_CONTROL_ST BIT(0)
  174. #define EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16
  175. #define EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK 0x3f
  176. #define EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT 1
  177. #define EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK 0x3fff
  178. #define EQOS_DMA_CH0_RX_CONTROL_SR BIT(0)
  179. /* These registers are Tegra186-specific */
  180. #define EQOS_TEGRA186_REGS_BASE 0x8800
  181. struct eqos_tegra186_regs {
  182. uint32_t sdmemcomppadctrl; /* 0x8800 */
  183. uint32_t auto_cal_config; /* 0x8804 */
  184. uint32_t unused_8808; /* 0x8808 */
  185. uint32_t auto_cal_status; /* 0x880c */
  186. };
  187. #define EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD BIT(31)
  188. #define EQOS_AUTO_CAL_CONFIG_START BIT(31)
  189. #define EQOS_AUTO_CAL_CONFIG_ENABLE BIT(29)
  190. #define EQOS_AUTO_CAL_STATUS_ACTIVE BIT(31)
  191. /* Descriptors */
  192. #define EQOS_DESCRIPTOR_WORDS 4
  193. #define EQOS_DESCRIPTOR_SIZE (EQOS_DESCRIPTOR_WORDS * 4)
  194. /* We assume ARCH_DMA_MINALIGN >= 16; 16 is the EQOS HW minimum */
  195. #define EQOS_DESCRIPTOR_ALIGN ARCH_DMA_MINALIGN
  196. #define EQOS_DESCRIPTORS_TX 4
  197. #define EQOS_DESCRIPTORS_RX 4
  198. #define EQOS_DESCRIPTORS_NUM (EQOS_DESCRIPTORS_TX + EQOS_DESCRIPTORS_RX)
  199. #define EQOS_DESCRIPTORS_SIZE ALIGN(EQOS_DESCRIPTORS_NUM * \
  200. EQOS_DESCRIPTOR_SIZE, ARCH_DMA_MINALIGN)
  201. #define EQOS_BUFFER_ALIGN ARCH_DMA_MINALIGN
  202. #define EQOS_MAX_PACKET_SIZE ALIGN(1568, ARCH_DMA_MINALIGN)
  203. #define EQOS_RX_BUFFER_SIZE (EQOS_DESCRIPTORS_RX * EQOS_MAX_PACKET_SIZE)
  204. /*
  205. * Warn if the cache-line size is larger than the descriptor size. In such
  206. * cases the driver will likely fail because the CPU needs to flush the cache
  207. * when requeuing RX buffers, therefore descriptors written by the hardware
  208. * may be discarded. Architectures with full IO coherence, such as x86, do not
  209. * experience this issue, and hence are excluded from this condition.
  210. *
  211. * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
  212. * the driver to allocate descriptors from a pool of non-cached memory.
  213. */
  214. #if EQOS_DESCRIPTOR_SIZE < ARCH_DMA_MINALIGN
  215. #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
  216. !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
  217. #warning Cache line size is larger than descriptor size
  218. #endif
  219. #endif
  220. struct eqos_desc {
  221. u32 des0;
  222. u32 des1;
  223. u32 des2;
  224. u32 des3;
  225. };
  226. #define EQOS_DESC3_OWN BIT(31)
  227. #define EQOS_DESC3_FD BIT(29)
  228. #define EQOS_DESC3_LD BIT(28)
  229. #define EQOS_DESC3_BUF1V BIT(24)
  230. struct eqos_config {
  231. bool reg_access_always_ok;
  232. int mdio_wait;
  233. int swr_wait;
  234. int config_mac;
  235. int config_mac_mdio;
  236. phy_interface_t (*interface)(struct udevice *dev);
  237. struct eqos_ops *ops;
  238. };
  239. struct eqos_ops {
  240. void (*eqos_inval_desc)(void *desc);
  241. void (*eqos_flush_desc)(void *desc);
  242. void (*eqos_inval_buffer)(void *buf, size_t size);
  243. void (*eqos_flush_buffer)(void *buf, size_t size);
  244. int (*eqos_probe_resources)(struct udevice *dev);
  245. int (*eqos_remove_resources)(struct udevice *dev);
  246. int (*eqos_stop_resets)(struct udevice *dev);
  247. int (*eqos_start_resets)(struct udevice *dev);
  248. void (*eqos_stop_clks)(struct udevice *dev);
  249. int (*eqos_start_clks)(struct udevice *dev);
  250. int (*eqos_calibrate_pads)(struct udevice *dev);
  251. int (*eqos_disable_calibration)(struct udevice *dev);
  252. int (*eqos_set_tx_clk_speed)(struct udevice *dev);
  253. ulong (*eqos_get_tick_clk_rate)(struct udevice *dev);
  254. };
  255. struct eqos_priv {
  256. struct udevice *dev;
  257. const struct eqos_config *config;
  258. fdt_addr_t regs;
  259. struct eqos_mac_regs *mac_regs;
  260. struct eqos_mtl_regs *mtl_regs;
  261. struct eqos_dma_regs *dma_regs;
  262. struct eqos_tegra186_regs *tegra186_regs;
  263. struct reset_ctl reset_ctl;
  264. struct gpio_desc phy_reset_gpio;
  265. struct clk clk_master_bus;
  266. struct clk clk_rx;
  267. struct clk clk_ptp_ref;
  268. struct clk clk_tx;
  269. struct clk clk_ck;
  270. struct clk clk_slave_bus;
  271. struct mii_dev *mii;
  272. struct phy_device *phy;
  273. void *descs;
  274. struct eqos_desc *tx_descs;
  275. struct eqos_desc *rx_descs;
  276. int tx_desc_idx, rx_desc_idx;
  277. void *tx_dma_buf;
  278. void *rx_dma_buf;
  279. void *rx_pkt;
  280. bool started;
  281. bool reg_access_ok;
  282. };
  283. /*
  284. * TX and RX descriptors are 16 bytes. This causes problems with the cache
  285. * maintenance on CPUs where the cache-line size exceeds the size of these
  286. * descriptors. What will happen is that when the driver receives a packet
  287. * it will be immediately requeued for the hardware to reuse. The CPU will
  288. * therefore need to flush the cache-line containing the descriptor, which
  289. * will cause all other descriptors in the same cache-line to be flushed
  290. * along with it. If one of those descriptors had been written to by the
  291. * device those changes (and the associated packet) will be lost.
  292. *
  293. * To work around this, we make use of non-cached memory if available. If
  294. * descriptors are mapped uncached there's no need to manually flush them
  295. * or invalidate them.
  296. *
  297. * Note that this only applies to descriptors. The packet data buffers do
  298. * not have the same constraints since they are 1536 bytes large, so they
  299. * are unlikely to share cache-lines.
  300. */
  301. static void *eqos_alloc_descs(unsigned int num)
  302. {
  303. #ifdef CONFIG_SYS_NONCACHED_MEMORY
  304. return (void *)noncached_alloc(EQOS_DESCRIPTORS_SIZE,
  305. EQOS_DESCRIPTOR_ALIGN);
  306. #else
  307. return memalign(EQOS_DESCRIPTOR_ALIGN, EQOS_DESCRIPTORS_SIZE);
  308. #endif
  309. }
  310. static void eqos_free_descs(void *descs)
  311. {
  312. #ifdef CONFIG_SYS_NONCACHED_MEMORY
  313. /* FIXME: noncached_alloc() has no opposite */
  314. #else
  315. free(descs);
  316. #endif
  317. }
  318. static void eqos_inval_desc_tegra186(void *desc)
  319. {
  320. #ifndef CONFIG_SYS_NONCACHED_MEMORY
  321. unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
  322. unsigned long end = ALIGN(start + EQOS_DESCRIPTOR_SIZE,
  323. ARCH_DMA_MINALIGN);
  324. invalidate_dcache_range(start, end);
  325. #endif
  326. }
  327. static void eqos_inval_desc_stm32(void *desc)
  328. {
  329. #ifndef CONFIG_SYS_NONCACHED_MEMORY
  330. unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN);
  331. unsigned long end = roundup((unsigned long)desc + EQOS_DESCRIPTOR_SIZE,
  332. ARCH_DMA_MINALIGN);
  333. invalidate_dcache_range(start, end);
  334. #endif
  335. }
  336. static void eqos_flush_desc_tegra186(void *desc)
  337. {
  338. #ifndef CONFIG_SYS_NONCACHED_MEMORY
  339. flush_cache((unsigned long)desc, EQOS_DESCRIPTOR_SIZE);
  340. #endif
  341. }
  342. static void eqos_flush_desc_stm32(void *desc)
  343. {
  344. #ifndef CONFIG_SYS_NONCACHED_MEMORY
  345. unsigned long start = rounddown((unsigned long)desc, ARCH_DMA_MINALIGN);
  346. unsigned long end = roundup((unsigned long)desc + EQOS_DESCRIPTOR_SIZE,
  347. ARCH_DMA_MINALIGN);
  348. flush_dcache_range(start, end);
  349. #endif
  350. }
  351. static void eqos_inval_buffer_tegra186(void *buf, size_t size)
  352. {
  353. unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
  354. unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
  355. invalidate_dcache_range(start, end);
  356. }
  357. static void eqos_inval_buffer_stm32(void *buf, size_t size)
  358. {
  359. unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
  360. unsigned long end = roundup((unsigned long)buf + size,
  361. ARCH_DMA_MINALIGN);
  362. invalidate_dcache_range(start, end);
  363. }
  364. static void eqos_flush_buffer_tegra186(void *buf, size_t size)
  365. {
  366. flush_cache((unsigned long)buf, size);
  367. }
  368. static void eqos_flush_buffer_stm32(void *buf, size_t size)
  369. {
  370. unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
  371. unsigned long end = roundup((unsigned long)buf + size,
  372. ARCH_DMA_MINALIGN);
  373. flush_dcache_range(start, end);
  374. }
  375. static int eqos_mdio_wait_idle(struct eqos_priv *eqos)
  376. {
  377. return wait_for_bit_le32(&eqos->mac_regs->mdio_address,
  378. EQOS_MAC_MDIO_ADDRESS_GB, false,
  379. 1000000, true);
  380. }
  381. static int eqos_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad,
  382. int mdio_reg)
  383. {
  384. struct eqos_priv *eqos = bus->priv;
  385. u32 val;
  386. int ret;
  387. debug("%s(dev=%p, addr=%x, reg=%d):\n", __func__, eqos->dev, mdio_addr,
  388. mdio_reg);
  389. ret = eqos_mdio_wait_idle(eqos);
  390. if (ret) {
  391. pr_err("MDIO not idle at entry");
  392. return ret;
  393. }
  394. val = readl(&eqos->mac_regs->mdio_address);
  395. val &= EQOS_MAC_MDIO_ADDRESS_SKAP |
  396. EQOS_MAC_MDIO_ADDRESS_C45E;
  397. val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) |
  398. (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) |
  399. (eqos->config->config_mac_mdio <<
  400. EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) |
  401. (EQOS_MAC_MDIO_ADDRESS_GOC_READ <<
  402. EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) |
  403. EQOS_MAC_MDIO_ADDRESS_GB;
  404. writel(val, &eqos->mac_regs->mdio_address);
  405. udelay(eqos->config->mdio_wait);
  406. ret = eqos_mdio_wait_idle(eqos);
  407. if (ret) {
  408. pr_err("MDIO read didn't complete");
  409. return ret;
  410. }
  411. val = readl(&eqos->mac_regs->mdio_data);
  412. val &= EQOS_MAC_MDIO_DATA_GD_MASK;
  413. debug("%s: val=%x\n", __func__, val);
  414. return val;
  415. }
  416. static int eqos_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad,
  417. int mdio_reg, u16 mdio_val)
  418. {
  419. struct eqos_priv *eqos = bus->priv;
  420. u32 val;
  421. int ret;
  422. debug("%s(dev=%p, addr=%x, reg=%d, val=%x):\n", __func__, eqos->dev,
  423. mdio_addr, mdio_reg, mdio_val);
  424. ret = eqos_mdio_wait_idle(eqos);
  425. if (ret) {
  426. pr_err("MDIO not idle at entry");
  427. return ret;
  428. }
  429. writel(mdio_val, &eqos->mac_regs->mdio_data);
  430. val = readl(&eqos->mac_regs->mdio_address);
  431. val &= EQOS_MAC_MDIO_ADDRESS_SKAP |
  432. EQOS_MAC_MDIO_ADDRESS_C45E;
  433. val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) |
  434. (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) |
  435. (eqos->config->config_mac_mdio <<
  436. EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) |
  437. (EQOS_MAC_MDIO_ADDRESS_GOC_WRITE <<
  438. EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) |
  439. EQOS_MAC_MDIO_ADDRESS_GB;
  440. writel(val, &eqos->mac_regs->mdio_address);
  441. udelay(eqos->config->mdio_wait);
  442. ret = eqos_mdio_wait_idle(eqos);
  443. if (ret) {
  444. pr_err("MDIO read didn't complete");
  445. return ret;
  446. }
  447. return 0;
  448. }
  449. static int eqos_start_clks_tegra186(struct udevice *dev)
  450. {
  451. struct eqos_priv *eqos = dev_get_priv(dev);
  452. int ret;
  453. debug("%s(dev=%p):\n", __func__, dev);
  454. ret = clk_enable(&eqos->clk_slave_bus);
  455. if (ret < 0) {
  456. pr_err("clk_enable(clk_slave_bus) failed: %d", ret);
  457. goto err;
  458. }
  459. ret = clk_enable(&eqos->clk_master_bus);
  460. if (ret < 0) {
  461. pr_err("clk_enable(clk_master_bus) failed: %d", ret);
  462. goto err_disable_clk_slave_bus;
  463. }
  464. ret = clk_enable(&eqos->clk_rx);
  465. if (ret < 0) {
  466. pr_err("clk_enable(clk_rx) failed: %d", ret);
  467. goto err_disable_clk_master_bus;
  468. }
  469. ret = clk_enable(&eqos->clk_ptp_ref);
  470. if (ret < 0) {
  471. pr_err("clk_enable(clk_ptp_ref) failed: %d", ret);
  472. goto err_disable_clk_rx;
  473. }
  474. ret = clk_set_rate(&eqos->clk_ptp_ref, 125 * 1000 * 1000);
  475. if (ret < 0) {
  476. pr_err("clk_set_rate(clk_ptp_ref) failed: %d", ret);
  477. goto err_disable_clk_ptp_ref;
  478. }
  479. ret = clk_enable(&eqos->clk_tx);
  480. if (ret < 0) {
  481. pr_err("clk_enable(clk_tx) failed: %d", ret);
  482. goto err_disable_clk_ptp_ref;
  483. }
  484. debug("%s: OK\n", __func__);
  485. return 0;
  486. err_disable_clk_ptp_ref:
  487. clk_disable(&eqos->clk_ptp_ref);
  488. err_disable_clk_rx:
  489. clk_disable(&eqos->clk_rx);
  490. err_disable_clk_master_bus:
  491. clk_disable(&eqos->clk_master_bus);
  492. err_disable_clk_slave_bus:
  493. clk_disable(&eqos->clk_slave_bus);
  494. err:
  495. debug("%s: FAILED: %d\n", __func__, ret);
  496. return ret;
  497. }
  498. static int eqos_start_clks_stm32(struct udevice *dev)
  499. {
  500. struct eqos_priv *eqos = dev_get_priv(dev);
  501. int ret;
  502. debug("%s(dev=%p):\n", __func__, dev);
  503. ret = clk_enable(&eqos->clk_master_bus);
  504. if (ret < 0) {
  505. pr_err("clk_enable(clk_master_bus) failed: %d", ret);
  506. goto err;
  507. }
  508. ret = clk_enable(&eqos->clk_rx);
  509. if (ret < 0) {
  510. pr_err("clk_enable(clk_rx) failed: %d", ret);
  511. goto err_disable_clk_master_bus;
  512. }
  513. ret = clk_enable(&eqos->clk_tx);
  514. if (ret < 0) {
  515. pr_err("clk_enable(clk_tx) failed: %d", ret);
  516. goto err_disable_clk_rx;
  517. }
  518. if (clk_valid(&eqos->clk_ck)) {
  519. ret = clk_enable(&eqos->clk_ck);
  520. if (ret < 0) {
  521. pr_err("clk_enable(clk_ck) failed: %d", ret);
  522. goto err_disable_clk_tx;
  523. }
  524. }
  525. debug("%s: OK\n", __func__);
  526. return 0;
  527. err_disable_clk_tx:
  528. clk_disable(&eqos->clk_tx);
  529. err_disable_clk_rx:
  530. clk_disable(&eqos->clk_rx);
  531. err_disable_clk_master_bus:
  532. clk_disable(&eqos->clk_master_bus);
  533. err:
  534. debug("%s: FAILED: %d\n", __func__, ret);
  535. return ret;
  536. }
  537. static void eqos_stop_clks_tegra186(struct udevice *dev)
  538. {
  539. struct eqos_priv *eqos = dev_get_priv(dev);
  540. debug("%s(dev=%p):\n", __func__, dev);
  541. clk_disable(&eqos->clk_tx);
  542. clk_disable(&eqos->clk_ptp_ref);
  543. clk_disable(&eqos->clk_rx);
  544. clk_disable(&eqos->clk_master_bus);
  545. clk_disable(&eqos->clk_slave_bus);
  546. debug("%s: OK\n", __func__);
  547. }
  548. static void eqos_stop_clks_stm32(struct udevice *dev)
  549. {
  550. struct eqos_priv *eqos = dev_get_priv(dev);
  551. debug("%s(dev=%p):\n", __func__, dev);
  552. clk_disable(&eqos->clk_tx);
  553. clk_disable(&eqos->clk_rx);
  554. clk_disable(&eqos->clk_master_bus);
  555. if (clk_valid(&eqos->clk_ck))
  556. clk_disable(&eqos->clk_ck);
  557. debug("%s: OK\n", __func__);
  558. }
  559. static int eqos_start_resets_tegra186(struct udevice *dev)
  560. {
  561. struct eqos_priv *eqos = dev_get_priv(dev);
  562. int ret;
  563. debug("%s(dev=%p):\n", __func__, dev);
  564. ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
  565. if (ret < 0) {
  566. pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d", ret);
  567. return ret;
  568. }
  569. udelay(2);
  570. ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
  571. if (ret < 0) {
  572. pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", ret);
  573. return ret;
  574. }
  575. ret = reset_assert(&eqos->reset_ctl);
  576. if (ret < 0) {
  577. pr_err("reset_assert() failed: %d", ret);
  578. return ret;
  579. }
  580. udelay(2);
  581. ret = reset_deassert(&eqos->reset_ctl);
  582. if (ret < 0) {
  583. pr_err("reset_deassert() failed: %d", ret);
  584. return ret;
  585. }
  586. debug("%s: OK\n", __func__);
  587. return 0;
  588. }
  589. static int eqos_start_resets_stm32(struct udevice *dev)
  590. {
  591. return 0;
  592. }
  593. static int eqos_stop_resets_tegra186(struct udevice *dev)
  594. {
  595. struct eqos_priv *eqos = dev_get_priv(dev);
  596. reset_assert(&eqos->reset_ctl);
  597. dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
  598. return 0;
  599. }
  600. static int eqos_stop_resets_stm32(struct udevice *dev)
  601. {
  602. return 0;
  603. }
  604. static int eqos_calibrate_pads_tegra186(struct udevice *dev)
  605. {
  606. struct eqos_priv *eqos = dev_get_priv(dev);
  607. int ret;
  608. debug("%s(dev=%p):\n", __func__, dev);
  609. setbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl,
  610. EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD);
  611. udelay(1);
  612. setbits_le32(&eqos->tegra186_regs->auto_cal_config,
  613. EQOS_AUTO_CAL_CONFIG_START | EQOS_AUTO_CAL_CONFIG_ENABLE);
  614. ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
  615. EQOS_AUTO_CAL_STATUS_ACTIVE, true, 10, false);
  616. if (ret) {
  617. pr_err("calibrate didn't start");
  618. goto failed;
  619. }
  620. ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
  621. EQOS_AUTO_CAL_STATUS_ACTIVE, false, 10, false);
  622. if (ret) {
  623. pr_err("calibrate didn't finish");
  624. goto failed;
  625. }
  626. ret = 0;
  627. failed:
  628. clrbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl,
  629. EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD);
  630. debug("%s: returns %d\n", __func__, ret);
  631. return ret;
  632. }
  633. static int eqos_disable_calibration_tegra186(struct udevice *dev)
  634. {
  635. struct eqos_priv *eqos = dev_get_priv(dev);
  636. debug("%s(dev=%p):\n", __func__, dev);
  637. clrbits_le32(&eqos->tegra186_regs->auto_cal_config,
  638. EQOS_AUTO_CAL_CONFIG_ENABLE);
  639. return 0;
  640. }
  641. static ulong eqos_get_tick_clk_rate_tegra186(struct udevice *dev)
  642. {
  643. struct eqos_priv *eqos = dev_get_priv(dev);
  644. return clk_get_rate(&eqos->clk_slave_bus);
  645. }
  646. static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev)
  647. {
  648. struct eqos_priv *eqos = dev_get_priv(dev);
  649. return clk_get_rate(&eqos->clk_master_bus);
  650. }
  651. static int eqos_calibrate_pads_stm32(struct udevice *dev)
  652. {
  653. return 0;
  654. }
  655. static int eqos_disable_calibration_stm32(struct udevice *dev)
  656. {
  657. return 0;
  658. }
  659. static int eqos_set_full_duplex(struct udevice *dev)
  660. {
  661. struct eqos_priv *eqos = dev_get_priv(dev);
  662. debug("%s(dev=%p):\n", __func__, dev);
  663. setbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM);
  664. return 0;
  665. }
  666. static int eqos_set_half_duplex(struct udevice *dev)
  667. {
  668. struct eqos_priv *eqos = dev_get_priv(dev);
  669. debug("%s(dev=%p):\n", __func__, dev);
  670. clrbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM);
  671. /* WAR: Flush TX queue when switching to half-duplex */
  672. setbits_le32(&eqos->mtl_regs->txq0_operation_mode,
  673. EQOS_MTL_TXQ0_OPERATION_MODE_FTQ);
  674. return 0;
  675. }
  676. static int eqos_set_gmii_speed(struct udevice *dev)
  677. {
  678. struct eqos_priv *eqos = dev_get_priv(dev);
  679. debug("%s(dev=%p):\n", __func__, dev);
  680. clrbits_le32(&eqos->mac_regs->configuration,
  681. EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES);
  682. return 0;
  683. }
  684. static int eqos_set_mii_speed_100(struct udevice *dev)
  685. {
  686. struct eqos_priv *eqos = dev_get_priv(dev);
  687. debug("%s(dev=%p):\n", __func__, dev);
  688. setbits_le32(&eqos->mac_regs->configuration,
  689. EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES);
  690. return 0;
  691. }
  692. static int eqos_set_mii_speed_10(struct udevice *dev)
  693. {
  694. struct eqos_priv *eqos = dev_get_priv(dev);
  695. debug("%s(dev=%p):\n", __func__, dev);
  696. clrsetbits_le32(&eqos->mac_regs->configuration,
  697. EQOS_MAC_CONFIGURATION_FES, EQOS_MAC_CONFIGURATION_PS);
  698. return 0;
  699. }
  700. static int eqos_set_tx_clk_speed_tegra186(struct udevice *dev)
  701. {
  702. struct eqos_priv *eqos = dev_get_priv(dev);
  703. ulong rate;
  704. int ret;
  705. debug("%s(dev=%p):\n", __func__, dev);
  706. switch (eqos->phy->speed) {
  707. case SPEED_1000:
  708. rate = 125 * 1000 * 1000;
  709. break;
  710. case SPEED_100:
  711. rate = 25 * 1000 * 1000;
  712. break;
  713. case SPEED_10:
  714. rate = 2.5 * 1000 * 1000;
  715. break;
  716. default:
  717. pr_err("invalid speed %d", eqos->phy->speed);
  718. return -EINVAL;
  719. }
  720. ret = clk_set_rate(&eqos->clk_tx, rate);
  721. if (ret < 0) {
  722. pr_err("clk_set_rate(tx_clk, %lu) failed: %d", rate, ret);
  723. return ret;
  724. }
  725. return 0;
  726. }
  727. static int eqos_set_tx_clk_speed_stm32(struct udevice *dev)
  728. {
  729. return 0;
  730. }
  731. static int eqos_adjust_link(struct udevice *dev)
  732. {
  733. struct eqos_priv *eqos = dev_get_priv(dev);
  734. int ret;
  735. bool en_calibration;
  736. debug("%s(dev=%p):\n", __func__, dev);
  737. if (eqos->phy->duplex)
  738. ret = eqos_set_full_duplex(dev);
  739. else
  740. ret = eqos_set_half_duplex(dev);
  741. if (ret < 0) {
  742. pr_err("eqos_set_*_duplex() failed: %d", ret);
  743. return ret;
  744. }
  745. switch (eqos->phy->speed) {
  746. case SPEED_1000:
  747. en_calibration = true;
  748. ret = eqos_set_gmii_speed(dev);
  749. break;
  750. case SPEED_100:
  751. en_calibration = true;
  752. ret = eqos_set_mii_speed_100(dev);
  753. break;
  754. case SPEED_10:
  755. en_calibration = false;
  756. ret = eqos_set_mii_speed_10(dev);
  757. break;
  758. default:
  759. pr_err("invalid speed %d", eqos->phy->speed);
  760. return -EINVAL;
  761. }
  762. if (ret < 0) {
  763. pr_err("eqos_set_*mii_speed*() failed: %d", ret);
  764. return ret;
  765. }
  766. if (en_calibration) {
  767. ret = eqos->config->ops->eqos_calibrate_pads(dev);
  768. if (ret < 0) {
  769. pr_err("eqos_calibrate_pads() failed: %d",
  770. ret);
  771. return ret;
  772. }
  773. } else {
  774. ret = eqos->config->ops->eqos_disable_calibration(dev);
  775. if (ret < 0) {
  776. pr_err("eqos_disable_calibration() failed: %d",
  777. ret);
  778. return ret;
  779. }
  780. }
  781. ret = eqos->config->ops->eqos_set_tx_clk_speed(dev);
  782. if (ret < 0) {
  783. pr_err("eqos_set_tx_clk_speed() failed: %d", ret);
  784. return ret;
  785. }
  786. return 0;
  787. }
  788. static int eqos_write_hwaddr(struct udevice *dev)
  789. {
  790. struct eth_pdata *plat = dev_get_platdata(dev);
  791. struct eqos_priv *eqos = dev_get_priv(dev);
  792. uint32_t val;
  793. /*
  794. * This function may be called before start() or after stop(). At that
  795. * time, on at least some configurations of the EQoS HW, all clocks to
  796. * the EQoS HW block will be stopped, and a reset signal applied. If
  797. * any register access is attempted in this state, bus timeouts or CPU
  798. * hangs may occur. This check prevents that.
  799. *
  800. * A simple solution to this problem would be to not implement
  801. * write_hwaddr(), since start() always writes the MAC address into HW
  802. * anyway. However, it is desirable to implement write_hwaddr() to
  803. * support the case of SW that runs subsequent to U-Boot which expects
  804. * the MAC address to already be programmed into the EQoS registers,
  805. * which must happen irrespective of whether the U-Boot user (or
  806. * scripts) actually made use of the EQoS device, and hence
  807. * irrespective of whether start() was ever called.
  808. *
  809. * Note that this requirement by subsequent SW is not valid for
  810. * Tegra186, and is likely not valid for any non-PCI instantiation of
  811. * the EQoS HW block. This function is implemented solely as
  812. * future-proofing with the expectation the driver will eventually be
  813. * ported to some system where the expectation above is true.
  814. */
  815. if (!eqos->config->reg_access_always_ok && !eqos->reg_access_ok)
  816. return 0;
  817. /* Update the MAC address */
  818. val = (plat->enetaddr[5] << 8) |
  819. (plat->enetaddr[4]);
  820. writel(val, &eqos->mac_regs->address0_high);
  821. val = (plat->enetaddr[3] << 24) |
  822. (plat->enetaddr[2] << 16) |
  823. (plat->enetaddr[1] << 8) |
  824. (plat->enetaddr[0]);
  825. writel(val, &eqos->mac_regs->address0_low);
  826. return 0;
  827. }
  828. static int eqos_start(struct udevice *dev)
  829. {
  830. struct eqos_priv *eqos = dev_get_priv(dev);
  831. int ret, i;
  832. ulong rate;
  833. u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
  834. ulong last_rx_desc;
  835. debug("%s(dev=%p):\n", __func__, dev);
  836. eqos->tx_desc_idx = 0;
  837. eqos->rx_desc_idx = 0;
  838. ret = eqos->config->ops->eqos_start_clks(dev);
  839. if (ret < 0) {
  840. pr_err("eqos_start_clks() failed: %d", ret);
  841. goto err;
  842. }
  843. ret = eqos->config->ops->eqos_start_resets(dev);
  844. if (ret < 0) {
  845. pr_err("eqos_start_resets() failed: %d", ret);
  846. goto err_stop_clks;
  847. }
  848. udelay(10);
  849. eqos->reg_access_ok = true;
  850. ret = wait_for_bit_le32(&eqos->dma_regs->mode,
  851. EQOS_DMA_MODE_SWR, false,
  852. eqos->config->swr_wait, false);
  853. if (ret) {
  854. pr_err("EQOS_DMA_MODE_SWR stuck");
  855. goto err_stop_resets;
  856. }
  857. ret = eqos->config->ops->eqos_calibrate_pads(dev);
  858. if (ret < 0) {
  859. pr_err("eqos_calibrate_pads() failed: %d", ret);
  860. goto err_stop_resets;
  861. }
  862. rate = eqos->config->ops->eqos_get_tick_clk_rate(dev);
  863. val = (rate / 1000000) - 1;
  864. writel(val, &eqos->mac_regs->us_tic_counter);
  865. /*
  866. * if PHY was already connected and configured,
  867. * don't need to reconnect/reconfigure again
  868. */
  869. if (!eqos->phy) {
  870. eqos->phy = phy_connect(eqos->mii, -1, dev,
  871. eqos->config->interface(dev));
  872. if (!eqos->phy) {
  873. pr_err("phy_connect() failed");
  874. goto err_stop_resets;
  875. }
  876. ret = phy_config(eqos->phy);
  877. if (ret < 0) {
  878. pr_err("phy_config() failed: %d", ret);
  879. goto err_shutdown_phy;
  880. }
  881. }
  882. ret = phy_startup(eqos->phy);
  883. if (ret < 0) {
  884. pr_err("phy_startup() failed: %d", ret);
  885. goto err_shutdown_phy;
  886. }
  887. if (!eqos->phy->link) {
  888. pr_err("No link");
  889. goto err_shutdown_phy;
  890. }
  891. ret = eqos_adjust_link(dev);
  892. if (ret < 0) {
  893. pr_err("eqos_adjust_link() failed: %d", ret);
  894. goto err_shutdown_phy;
  895. }
  896. /* Configure MTL */
  897. /* Enable Store and Forward mode for TX */
  898. /* Program Tx operating mode */
  899. setbits_le32(&eqos->mtl_regs->txq0_operation_mode,
  900. EQOS_MTL_TXQ0_OPERATION_MODE_TSF |
  901. (EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED <<
  902. EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT));
  903. /* Transmit Queue weight */
  904. writel(0x10, &eqos->mtl_regs->txq0_quantum_weight);
  905. /* Enable Store and Forward mode for RX, since no jumbo frame */
  906. setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
  907. EQOS_MTL_RXQ0_OPERATION_MODE_RSF);
  908. /* Transmit/Receive queue fifo size; use all RAM for 1 queue */
  909. val = readl(&eqos->mac_regs->hw_feature1);
  910. tx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) &
  911. EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK;
  912. rx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) &
  913. EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK;
  914. /*
  915. * r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting.
  916. * r/tqs is encoded as (n / 256) - 1.
  917. */
  918. tqs = (128 << tx_fifo_sz) / 256 - 1;
  919. rqs = (128 << rx_fifo_sz) / 256 - 1;
  920. clrsetbits_le32(&eqos->mtl_regs->txq0_operation_mode,
  921. EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK <<
  922. EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT,
  923. tqs << EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT);
  924. clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
  925. EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK <<
  926. EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT,
  927. rqs << EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT);
  928. /* Flow control used only if each channel gets 4KB or more FIFO */
  929. if (rqs >= ((4096 / 256) - 1)) {
  930. u32 rfd, rfa;
  931. setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
  932. EQOS_MTL_RXQ0_OPERATION_MODE_EHFC);
  933. /*
  934. * Set Threshold for Activating Flow Contol space for min 2
  935. * frames ie, (1500 * 1) = 1500 bytes.
  936. *
  937. * Set Threshold for Deactivating Flow Contol for space of
  938. * min 1 frame (frame size 1500bytes) in receive fifo
  939. */
  940. if (rqs == ((4096 / 256) - 1)) {
  941. /*
  942. * This violates the above formula because of FIFO size
  943. * limit therefore overflow may occur inspite of this.
  944. */
  945. rfd = 0x3; /* Full-3K */
  946. rfa = 0x1; /* Full-1.5K */
  947. } else if (rqs == ((8192 / 256) - 1)) {
  948. rfd = 0x6; /* Full-4K */
  949. rfa = 0xa; /* Full-6K */
  950. } else if (rqs == ((16384 / 256) - 1)) {
  951. rfd = 0x6; /* Full-4K */
  952. rfa = 0x12; /* Full-10K */
  953. } else {
  954. rfd = 0x6; /* Full-4K */
  955. rfa = 0x1E; /* Full-16K */
  956. }
  957. clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
  958. (EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK <<
  959. EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) |
  960. (EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK <<
  961. EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT),
  962. (rfd <<
  963. EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) |
  964. (rfa <<
  965. EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT));
  966. }
  967. /* Configure MAC */
  968. clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0,
  969. EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK <<
  970. EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT,
  971. eqos->config->config_mac <<
  972. EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
  973. /* Set TX flow control parameters */
  974. /* Set Pause Time */
  975. setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl,
  976. 0xffff << EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT);
  977. /* Assign priority for TX flow control */
  978. clrbits_le32(&eqos->mac_regs->txq_prty_map0,
  979. EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK <<
  980. EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT);
  981. /* Assign priority for RX flow control */
  982. clrbits_le32(&eqos->mac_regs->rxq_ctrl2,
  983. EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK <<
  984. EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT);
  985. /* Enable flow control */
  986. setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl,
  987. EQOS_MAC_Q0_TX_FLOW_CTRL_TFE);
  988. setbits_le32(&eqos->mac_regs->rx_flow_ctrl,
  989. EQOS_MAC_RX_FLOW_CTRL_RFE);
  990. clrsetbits_le32(&eqos->mac_regs->configuration,
  991. EQOS_MAC_CONFIGURATION_GPSLCE |
  992. EQOS_MAC_CONFIGURATION_WD |
  993. EQOS_MAC_CONFIGURATION_JD |
  994. EQOS_MAC_CONFIGURATION_JE,
  995. EQOS_MAC_CONFIGURATION_CST |
  996. EQOS_MAC_CONFIGURATION_ACS);
  997. eqos_write_hwaddr(dev);
  998. /* Configure DMA */
  999. /* Enable OSP mode */
  1000. setbits_le32(&eqos->dma_regs->ch0_tx_control,
  1001. EQOS_DMA_CH0_TX_CONTROL_OSP);
  1002. /* RX buffer size. Must be a multiple of bus width */
  1003. clrsetbits_le32(&eqos->dma_regs->ch0_rx_control,
  1004. EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK <<
  1005. EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT,
  1006. EQOS_MAX_PACKET_SIZE <<
  1007. EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT);
  1008. setbits_le32(&eqos->dma_regs->ch0_control,
  1009. EQOS_DMA_CH0_CONTROL_PBLX8);
  1010. /*
  1011. * Burst length must be < 1/2 FIFO size.
  1012. * FIFO size in tqs is encoded as (n / 256) - 1.
  1013. * Each burst is n * 8 (PBLX8) * 16 (AXI width) == 128 bytes.
  1014. * Half of n * 256 is n * 128, so pbl == tqs, modulo the -1.
  1015. */
  1016. pbl = tqs + 1;
  1017. if (pbl > 32)
  1018. pbl = 32;
  1019. clrsetbits_le32(&eqos->dma_regs->ch0_tx_control,
  1020. EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK <<
  1021. EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT,
  1022. pbl << EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT);
  1023. clrsetbits_le32(&eqos->dma_regs->ch0_rx_control,
  1024. EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK <<
  1025. EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT,
  1026. 8 << EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT);
  1027. /* DMA performance configuration */
  1028. val = (2 << EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT) |
  1029. EQOS_DMA_SYSBUS_MODE_EAME | EQOS_DMA_SYSBUS_MODE_BLEN16 |
  1030. EQOS_DMA_SYSBUS_MODE_BLEN8 | EQOS_DMA_SYSBUS_MODE_BLEN4;
  1031. writel(val, &eqos->dma_regs->sysbus_mode);
  1032. /* Set up descriptors */
  1033. memset(eqos->descs, 0, EQOS_DESCRIPTORS_SIZE);
  1034. for (i = 0; i < EQOS_DESCRIPTORS_RX; i++) {
  1035. struct eqos_desc *rx_desc = &(eqos->rx_descs[i]);
  1036. rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf +
  1037. (i * EQOS_MAX_PACKET_SIZE));
  1038. rx_desc->des3 |= EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
  1039. }
  1040. eqos->config->ops->eqos_flush_desc(eqos->descs);
  1041. writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress);
  1042. writel((ulong)eqos->tx_descs, &eqos->dma_regs->ch0_txdesc_list_address);
  1043. writel(EQOS_DESCRIPTORS_TX - 1,
  1044. &eqos->dma_regs->ch0_txdesc_ring_length);
  1045. writel(0, &eqos->dma_regs->ch0_rxdesc_list_haddress);
  1046. writel((ulong)eqos->rx_descs, &eqos->dma_regs->ch0_rxdesc_list_address);
  1047. writel(EQOS_DESCRIPTORS_RX - 1,
  1048. &eqos->dma_regs->ch0_rxdesc_ring_length);
  1049. /* Enable everything */
  1050. setbits_le32(&eqos->mac_regs->configuration,
  1051. EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE);
  1052. setbits_le32(&eqos->dma_regs->ch0_tx_control,
  1053. EQOS_DMA_CH0_TX_CONTROL_ST);
  1054. setbits_le32(&eqos->dma_regs->ch0_rx_control,
  1055. EQOS_DMA_CH0_RX_CONTROL_SR);
  1056. /* TX tail pointer not written until we need to TX a packet */
  1057. /*
  1058. * Point RX tail pointer at last descriptor. Ideally, we'd point at the
  1059. * first descriptor, implying all descriptors were available. However,
  1060. * that's not distinguishable from none of the descriptors being
  1061. * available.
  1062. */
  1063. last_rx_desc = (ulong)&(eqos->rx_descs[(EQOS_DESCRIPTORS_RX - 1)]);
  1064. writel(last_rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);
  1065. eqos->started = true;
  1066. debug("%s: OK\n", __func__);
  1067. return 0;
  1068. err_shutdown_phy:
  1069. phy_shutdown(eqos->phy);
  1070. err_stop_resets:
  1071. eqos->config->ops->eqos_stop_resets(dev);
  1072. err_stop_clks:
  1073. eqos->config->ops->eqos_stop_clks(dev);
  1074. err:
  1075. pr_err("FAILED: %d", ret);
  1076. return ret;
  1077. }
  1078. static void eqos_stop(struct udevice *dev)
  1079. {
  1080. struct eqos_priv *eqos = dev_get_priv(dev);
  1081. int i;
  1082. debug("%s(dev=%p):\n", __func__, dev);
  1083. if (!eqos->started)
  1084. return;
  1085. eqos->started = false;
  1086. eqos->reg_access_ok = false;
  1087. /* Disable TX DMA */
  1088. clrbits_le32(&eqos->dma_regs->ch0_tx_control,
  1089. EQOS_DMA_CH0_TX_CONTROL_ST);
  1090. /* Wait for TX all packets to drain out of MTL */
  1091. for (i = 0; i < 1000000; i++) {
  1092. u32 val = readl(&eqos->mtl_regs->txq0_debug);
  1093. u32 trcsts = (val >> EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT) &
  1094. EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK;
  1095. u32 txqsts = val & EQOS_MTL_TXQ0_DEBUG_TXQSTS;
  1096. if ((trcsts != 1) && (!txqsts))
  1097. break;
  1098. }
  1099. /* Turn off MAC TX and RX */
  1100. clrbits_le32(&eqos->mac_regs->configuration,
  1101. EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE);
  1102. /* Wait for all RX packets to drain out of MTL */
  1103. for (i = 0; i < 1000000; i++) {
  1104. u32 val = readl(&eqos->mtl_regs->rxq0_debug);
  1105. u32 prxq = (val >> EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT) &
  1106. EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK;
  1107. u32 rxqsts = (val >> EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) &
  1108. EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK;
  1109. if ((!prxq) && (!rxqsts))
  1110. break;
  1111. }
  1112. /* Turn off RX DMA */
  1113. clrbits_le32(&eqos->dma_regs->ch0_rx_control,
  1114. EQOS_DMA_CH0_RX_CONTROL_SR);
  1115. if (eqos->phy) {
  1116. phy_shutdown(eqos->phy);
  1117. }
  1118. eqos->config->ops->eqos_stop_resets(dev);
  1119. eqos->config->ops->eqos_stop_clks(dev);
  1120. debug("%s: OK\n", __func__);
  1121. }
  1122. static int eqos_send(struct udevice *dev, void *packet, int length)
  1123. {
  1124. struct eqos_priv *eqos = dev_get_priv(dev);
  1125. struct eqos_desc *tx_desc;
  1126. int i;
  1127. debug("%s(dev=%p, packet=%p, length=%d):\n", __func__, dev, packet,
  1128. length);
  1129. memcpy(eqos->tx_dma_buf, packet, length);
  1130. eqos->config->ops->eqos_flush_buffer(eqos->tx_dma_buf, length);
  1131. tx_desc = &(eqos->tx_descs[eqos->tx_desc_idx]);
  1132. eqos->tx_desc_idx++;
  1133. eqos->tx_desc_idx %= EQOS_DESCRIPTORS_TX;
  1134. tx_desc->des0 = (ulong)eqos->tx_dma_buf;
  1135. tx_desc->des1 = 0;
  1136. tx_desc->des2 = length;
  1137. /*
  1138. * Make sure that if HW sees the _OWN write below, it will see all the
  1139. * writes to the rest of the descriptor too.
  1140. */
  1141. mb();
  1142. tx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_FD | EQOS_DESC3_LD | length;
  1143. eqos->config->ops->eqos_flush_desc(tx_desc);
  1144. writel((ulong)(tx_desc + 1), &eqos->dma_regs->ch0_txdesc_tail_pointer);
  1145. for (i = 0; i < 1000000; i++) {
  1146. eqos->config->ops->eqos_inval_desc(tx_desc);
  1147. if (!(readl(&tx_desc->des3) & EQOS_DESC3_OWN))
  1148. return 0;
  1149. udelay(1);
  1150. }
  1151. debug("%s: TX timeout\n", __func__);
  1152. return -ETIMEDOUT;
  1153. }
  1154. static int eqos_recv(struct udevice *dev, int flags, uchar **packetp)
  1155. {
  1156. struct eqos_priv *eqos = dev_get_priv(dev);
  1157. struct eqos_desc *rx_desc;
  1158. int length;
  1159. debug("%s(dev=%p, flags=%x):\n", __func__, dev, flags);
  1160. rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]);
  1161. if (rx_desc->des3 & EQOS_DESC3_OWN) {
  1162. debug("%s: RX packet not available\n", __func__);
  1163. return -EAGAIN;
  1164. }
  1165. *packetp = eqos->rx_dma_buf +
  1166. (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE);
  1167. length = rx_desc->des3 & 0x7fff;
  1168. debug("%s: *packetp=%p, length=%d\n", __func__, *packetp, length);
  1169. eqos->config->ops->eqos_inval_buffer(*packetp, length);
  1170. return length;
  1171. }
  1172. static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length)
  1173. {
  1174. struct eqos_priv *eqos = dev_get_priv(dev);
  1175. uchar *packet_expected;
  1176. struct eqos_desc *rx_desc;
  1177. debug("%s(packet=%p, length=%d)\n", __func__, packet, length);
  1178. packet_expected = eqos->rx_dma_buf +
  1179. (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE);
  1180. if (packet != packet_expected) {
  1181. debug("%s: Unexpected packet (expected %p)\n", __func__,
  1182. packet_expected);
  1183. return -EINVAL;
  1184. }
  1185. rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]);
  1186. rx_desc->des0 = (u32)(ulong)packet;
  1187. rx_desc->des1 = 0;
  1188. rx_desc->des2 = 0;
  1189. /*
  1190. * Make sure that if HW sees the _OWN write below, it will see all the
  1191. * writes to the rest of the descriptor too.
  1192. */
  1193. mb();
  1194. rx_desc->des3 |= EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
  1195. eqos->config->ops->eqos_flush_desc(rx_desc);
  1196. writel((ulong)rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);
  1197. eqos->rx_desc_idx++;
  1198. eqos->rx_desc_idx %= EQOS_DESCRIPTORS_RX;
  1199. return 0;
  1200. }
  1201. static int eqos_probe_resources_core(struct udevice *dev)
  1202. {
  1203. struct eqos_priv *eqos = dev_get_priv(dev);
  1204. int ret;
  1205. debug("%s(dev=%p):\n", __func__, dev);
  1206. eqos->descs = eqos_alloc_descs(EQOS_DESCRIPTORS_TX +
  1207. EQOS_DESCRIPTORS_RX);
  1208. if (!eqos->descs) {
  1209. debug("%s: eqos_alloc_descs() failed\n", __func__);
  1210. ret = -ENOMEM;
  1211. goto err;
  1212. }
  1213. eqos->tx_descs = (struct eqos_desc *)eqos->descs;
  1214. eqos->rx_descs = (eqos->tx_descs + EQOS_DESCRIPTORS_TX);
  1215. debug("%s: tx_descs=%p, rx_descs=%p\n", __func__, eqos->tx_descs,
  1216. eqos->rx_descs);
  1217. eqos->tx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_MAX_PACKET_SIZE);
  1218. if (!eqos->tx_dma_buf) {
  1219. debug("%s: memalign(tx_dma_buf) failed\n", __func__);
  1220. ret = -ENOMEM;
  1221. goto err_free_descs;
  1222. }
  1223. debug("%s: tx_dma_buf=%p\n", __func__, eqos->tx_dma_buf);
  1224. eqos->rx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_RX_BUFFER_SIZE);
  1225. if (!eqos->rx_dma_buf) {
  1226. debug("%s: memalign(rx_dma_buf) failed\n", __func__);
  1227. ret = -ENOMEM;
  1228. goto err_free_tx_dma_buf;
  1229. }
  1230. debug("%s: rx_dma_buf=%p\n", __func__, eqos->rx_dma_buf);
  1231. eqos->rx_pkt = malloc(EQOS_MAX_PACKET_SIZE);
  1232. if (!eqos->rx_pkt) {
  1233. debug("%s: malloc(rx_pkt) failed\n", __func__);
  1234. ret = -ENOMEM;
  1235. goto err_free_rx_dma_buf;
  1236. }
  1237. debug("%s: rx_pkt=%p\n", __func__, eqos->rx_pkt);
  1238. debug("%s: OK\n", __func__);
  1239. return 0;
  1240. err_free_rx_dma_buf:
  1241. free(eqos->rx_dma_buf);
  1242. err_free_tx_dma_buf:
  1243. free(eqos->tx_dma_buf);
  1244. err_free_descs:
  1245. eqos_free_descs(eqos->descs);
  1246. err:
  1247. debug("%s: returns %d\n", __func__, ret);
  1248. return ret;
  1249. }
  1250. static int eqos_remove_resources_core(struct udevice *dev)
  1251. {
  1252. struct eqos_priv *eqos = dev_get_priv(dev);
  1253. debug("%s(dev=%p):\n", __func__, dev);
  1254. free(eqos->rx_pkt);
  1255. free(eqos->rx_dma_buf);
  1256. free(eqos->tx_dma_buf);
  1257. eqos_free_descs(eqos->descs);
  1258. debug("%s: OK\n", __func__);
  1259. return 0;
  1260. }
  1261. static int eqos_probe_resources_tegra186(struct udevice *dev)
  1262. {
  1263. struct eqos_priv *eqos = dev_get_priv(dev);
  1264. int ret;
  1265. debug("%s(dev=%p):\n", __func__, dev);
  1266. ret = reset_get_by_name(dev, "eqos", &eqos->reset_ctl);
  1267. if (ret) {
  1268. pr_err("reset_get_by_name(rst) failed: %d", ret);
  1269. return ret;
  1270. }
  1271. ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
  1272. &eqos->phy_reset_gpio,
  1273. GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
  1274. if (ret) {
  1275. pr_err("gpio_request_by_name(phy reset) failed: %d", ret);
  1276. goto err_free_reset_eqos;
  1277. }
  1278. ret = clk_get_by_name(dev, "slave_bus", &eqos->clk_slave_bus);
  1279. if (ret) {
  1280. pr_err("clk_get_by_name(slave_bus) failed: %d", ret);
  1281. goto err_free_gpio_phy_reset;
  1282. }
  1283. ret = clk_get_by_name(dev, "master_bus", &eqos->clk_master_bus);
  1284. if (ret) {
  1285. pr_err("clk_get_by_name(master_bus) failed: %d", ret);
  1286. goto err_free_clk_slave_bus;
  1287. }
  1288. ret = clk_get_by_name(dev, "rx", &eqos->clk_rx);
  1289. if (ret) {
  1290. pr_err("clk_get_by_name(rx) failed: %d", ret);
  1291. goto err_free_clk_master_bus;
  1292. }
  1293. ret = clk_get_by_name(dev, "ptp_ref", &eqos->clk_ptp_ref);
  1294. if (ret) {
  1295. pr_err("clk_get_by_name(ptp_ref) failed: %d", ret);
  1296. goto err_free_clk_rx;
  1297. return ret;
  1298. }
  1299. ret = clk_get_by_name(dev, "tx", &eqos->clk_tx);
  1300. if (ret) {
  1301. pr_err("clk_get_by_name(tx) failed: %d", ret);
  1302. goto err_free_clk_ptp_ref;
  1303. }
  1304. debug("%s: OK\n", __func__);
  1305. return 0;
  1306. err_free_clk_ptp_ref:
  1307. clk_free(&eqos->clk_ptp_ref);
  1308. err_free_clk_rx:
  1309. clk_free(&eqos->clk_rx);
  1310. err_free_clk_master_bus:
  1311. clk_free(&eqos->clk_master_bus);
  1312. err_free_clk_slave_bus:
  1313. clk_free(&eqos->clk_slave_bus);
  1314. err_free_gpio_phy_reset:
  1315. dm_gpio_free(dev, &eqos->phy_reset_gpio);
  1316. err_free_reset_eqos:
  1317. reset_free(&eqos->reset_ctl);
  1318. debug("%s: returns %d\n", __func__, ret);
  1319. return ret;
  1320. }
  1321. /* board-specific Ethernet Interface initializations. */
  1322. __weak int board_interface_eth_init(struct udevice *dev,
  1323. phy_interface_t interface_type)
  1324. {
  1325. return 0;
  1326. }
  1327. static int eqos_probe_resources_stm32(struct udevice *dev)
  1328. {
  1329. struct eqos_priv *eqos = dev_get_priv(dev);
  1330. int ret;
  1331. phy_interface_t interface;
  1332. debug("%s(dev=%p):\n", __func__, dev);
  1333. interface = eqos->config->interface(dev);
  1334. if (interface == PHY_INTERFACE_MODE_NONE) {
  1335. pr_err("Invalid PHY interface\n");
  1336. return -EINVAL;
  1337. }
  1338. ret = board_interface_eth_init(dev, interface);
  1339. if (ret)
  1340. return -EINVAL;
  1341. ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
  1342. if (ret) {
  1343. pr_err("clk_get_by_name(master_bus) failed: %d", ret);
  1344. goto err_probe;
  1345. }
  1346. ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx);
  1347. if (ret) {
  1348. pr_err("clk_get_by_name(rx) failed: %d", ret);
  1349. goto err_free_clk_master_bus;
  1350. }
  1351. ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx);
  1352. if (ret) {
  1353. pr_err("clk_get_by_name(tx) failed: %d", ret);
  1354. goto err_free_clk_rx;
  1355. }
  1356. /* Get ETH_CLK clocks (optional) */
  1357. ret = clk_get_by_name(dev, "eth-ck", &eqos->clk_ck);
  1358. if (ret)
  1359. pr_warn("No phy clock provided %d", ret);
  1360. debug("%s: OK\n", __func__);
  1361. return 0;
  1362. err_free_clk_rx:
  1363. clk_free(&eqos->clk_rx);
  1364. err_free_clk_master_bus:
  1365. clk_free(&eqos->clk_master_bus);
  1366. err_probe:
  1367. debug("%s: returns %d\n", __func__, ret);
  1368. return ret;
  1369. }
  1370. static phy_interface_t eqos_get_interface_stm32(struct udevice *dev)
  1371. {
  1372. const char *phy_mode;
  1373. phy_interface_t interface = PHY_INTERFACE_MODE_NONE;
  1374. debug("%s(dev=%p):\n", __func__, dev);
  1375. phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
  1376. NULL);
  1377. if (phy_mode)
  1378. interface = phy_get_interface_by_name(phy_mode);
  1379. return interface;
  1380. }
  1381. static phy_interface_t eqos_get_interface_tegra186(struct udevice *dev)
  1382. {
  1383. return PHY_INTERFACE_MODE_MII;
  1384. }
  1385. static int eqos_remove_resources_tegra186(struct udevice *dev)
  1386. {
  1387. struct eqos_priv *eqos = dev_get_priv(dev);
  1388. debug("%s(dev=%p):\n", __func__, dev);
  1389. clk_free(&eqos->clk_tx);
  1390. clk_free(&eqos->clk_ptp_ref);
  1391. clk_free(&eqos->clk_rx);
  1392. clk_free(&eqos->clk_slave_bus);
  1393. clk_free(&eqos->clk_master_bus);
  1394. dm_gpio_free(dev, &eqos->phy_reset_gpio);
  1395. reset_free(&eqos->reset_ctl);
  1396. debug("%s: OK\n", __func__);
  1397. return 0;
  1398. }
  1399. static int eqos_remove_resources_stm32(struct udevice *dev)
  1400. {
  1401. struct eqos_priv *eqos = dev_get_priv(dev);
  1402. debug("%s(dev=%p):\n", __func__, dev);
  1403. clk_free(&eqos->clk_tx);
  1404. clk_free(&eqos->clk_rx);
  1405. clk_free(&eqos->clk_master_bus);
  1406. if (clk_valid(&eqos->clk_ck))
  1407. clk_free(&eqos->clk_ck);
  1408. debug("%s: OK\n", __func__);
  1409. return 0;
  1410. }
  1411. static int eqos_probe(struct udevice *dev)
  1412. {
  1413. struct eqos_priv *eqos = dev_get_priv(dev);
  1414. int ret;
  1415. debug("%s(dev=%p):\n", __func__, dev);
  1416. eqos->dev = dev;
  1417. eqos->config = (void *)dev_get_driver_data(dev);
  1418. eqos->regs = devfdt_get_addr(dev);
  1419. if (eqos->regs == FDT_ADDR_T_NONE) {
  1420. pr_err("devfdt_get_addr() failed");
  1421. return -ENODEV;
  1422. }
  1423. eqos->mac_regs = (void *)(eqos->regs + EQOS_MAC_REGS_BASE);
  1424. eqos->mtl_regs = (void *)(eqos->regs + EQOS_MTL_REGS_BASE);
  1425. eqos->dma_regs = (void *)(eqos->regs + EQOS_DMA_REGS_BASE);
  1426. eqos->tegra186_regs = (void *)(eqos->regs + EQOS_TEGRA186_REGS_BASE);
  1427. ret = eqos_probe_resources_core(dev);
  1428. if (ret < 0) {
  1429. pr_err("eqos_probe_resources_core() failed: %d", ret);
  1430. return ret;
  1431. }
  1432. ret = eqos->config->ops->eqos_probe_resources(dev);
  1433. if (ret < 0) {
  1434. pr_err("eqos_probe_resources() failed: %d", ret);
  1435. goto err_remove_resources_core;
  1436. }
  1437. eqos->mii = mdio_alloc();
  1438. if (!eqos->mii) {
  1439. pr_err("mdio_alloc() failed");
  1440. ret = -ENOMEM;
  1441. goto err_remove_resources_tegra;
  1442. }
  1443. eqos->mii->read = eqos_mdio_read;
  1444. eqos->mii->write = eqos_mdio_write;
  1445. eqos->mii->priv = eqos;
  1446. strcpy(eqos->mii->name, dev->name);
  1447. ret = mdio_register(eqos->mii);
  1448. if (ret < 0) {
  1449. pr_err("mdio_register() failed: %d", ret);
  1450. goto err_free_mdio;
  1451. }
  1452. debug("%s: OK\n", __func__);
  1453. return 0;
  1454. err_free_mdio:
  1455. mdio_free(eqos->mii);
  1456. err_remove_resources_tegra:
  1457. eqos->config->ops->eqos_remove_resources(dev);
  1458. err_remove_resources_core:
  1459. eqos_remove_resources_core(dev);
  1460. debug("%s: returns %d\n", __func__, ret);
  1461. return ret;
  1462. }
  1463. static int eqos_remove(struct udevice *dev)
  1464. {
  1465. struct eqos_priv *eqos = dev_get_priv(dev);
  1466. debug("%s(dev=%p):\n", __func__, dev);
  1467. mdio_unregister(eqos->mii);
  1468. mdio_free(eqos->mii);
  1469. eqos->config->ops->eqos_remove_resources(dev);
  1470. eqos_probe_resources_core(dev);
  1471. debug("%s: OK\n", __func__);
  1472. return 0;
  1473. }
  1474. static const struct eth_ops eqos_ops = {
  1475. .start = eqos_start,
  1476. .stop = eqos_stop,
  1477. .send = eqos_send,
  1478. .recv = eqos_recv,
  1479. .free_pkt = eqos_free_pkt,
  1480. .write_hwaddr = eqos_write_hwaddr,
  1481. };
  1482. static struct eqos_ops eqos_tegra186_ops = {
  1483. .eqos_inval_desc = eqos_inval_desc_tegra186,
  1484. .eqos_flush_desc = eqos_flush_desc_tegra186,
  1485. .eqos_inval_buffer = eqos_inval_buffer_tegra186,
  1486. .eqos_flush_buffer = eqos_flush_buffer_tegra186,
  1487. .eqos_probe_resources = eqos_probe_resources_tegra186,
  1488. .eqos_remove_resources = eqos_remove_resources_tegra186,
  1489. .eqos_stop_resets = eqos_stop_resets_tegra186,
  1490. .eqos_start_resets = eqos_start_resets_tegra186,
  1491. .eqos_stop_clks = eqos_stop_clks_tegra186,
  1492. .eqos_start_clks = eqos_start_clks_tegra186,
  1493. .eqos_calibrate_pads = eqos_calibrate_pads_tegra186,
  1494. .eqos_disable_calibration = eqos_disable_calibration_tegra186,
  1495. .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_tegra186,
  1496. .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_tegra186
  1497. };
  1498. static const struct eqos_config eqos_tegra186_config = {
  1499. .reg_access_always_ok = false,
  1500. .mdio_wait = 10,
  1501. .swr_wait = 10,
  1502. .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
  1503. .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_20_35,
  1504. .interface = eqos_get_interface_tegra186,
  1505. .ops = &eqos_tegra186_ops
  1506. };
  1507. static struct eqos_ops eqos_stm32_ops = {
  1508. .eqos_inval_desc = eqos_inval_desc_stm32,
  1509. .eqos_flush_desc = eqos_flush_desc_stm32,
  1510. .eqos_inval_buffer = eqos_inval_buffer_stm32,
  1511. .eqos_flush_buffer = eqos_flush_buffer_stm32,
  1512. .eqos_probe_resources = eqos_probe_resources_stm32,
  1513. .eqos_remove_resources = eqos_remove_resources_stm32,
  1514. .eqos_stop_resets = eqos_stop_resets_stm32,
  1515. .eqos_start_resets = eqos_start_resets_stm32,
  1516. .eqos_stop_clks = eqos_stop_clks_stm32,
  1517. .eqos_start_clks = eqos_start_clks_stm32,
  1518. .eqos_calibrate_pads = eqos_calibrate_pads_stm32,
  1519. .eqos_disable_calibration = eqos_disable_calibration_stm32,
  1520. .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_stm32,
  1521. .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32
  1522. };
  1523. static const struct eqos_config eqos_stm32_config = {
  1524. .reg_access_always_ok = false,
  1525. .mdio_wait = 10000,
  1526. .swr_wait = 50,
  1527. .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV,
  1528. .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
  1529. .interface = eqos_get_interface_stm32,
  1530. .ops = &eqos_stm32_ops
  1531. };
  1532. static const struct udevice_id eqos_ids[] = {
  1533. {
  1534. .compatible = "nvidia,tegra186-eqos",
  1535. .data = (ulong)&eqos_tegra186_config
  1536. },
  1537. {
  1538. .compatible = "snps,dwmac-4.20a",
  1539. .data = (ulong)&eqos_stm32_config
  1540. },
  1541. { }
  1542. };
  1543. U_BOOT_DRIVER(eth_eqos) = {
  1544. .name = "eth_eqos",
  1545. .id = UCLASS_ETH,
  1546. .of_match = eqos_ids,
  1547. .probe = eqos_probe,
  1548. .remove = eqos_remove,
  1549. .ops = &eqos_ops,
  1550. .priv_auto_alloc_size = sizeof(struct eqos_priv),
  1551. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  1552. };