omap3_spi.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Jagan Teki <jteki@openedev.com>
  4. * Christophe Ricard <christophe.ricard@gmail.com>
  5. *
  6. * Copyright (C) 2010 Dirk Behme <dirk.behme@googlemail.com>
  7. *
  8. * Driver for McSPI controller on OMAP3. Based on davinci_spi.c
  9. * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
  10. *
  11. * Copyright (C) 2007 Atmel Corporation
  12. *
  13. * Parts taken from linux/drivers/spi/omap2_mcspi.c
  14. * Copyright (C) 2005, 2006 Nokia Corporation
  15. *
  16. * Modified by Ruslan Araslanov <ruslan.araslanov@vitecmm.com>
  17. */
  18. #include <common.h>
  19. #include <dm.h>
  20. #include <spi.h>
  21. #include <malloc.h>
  22. #include <asm/io.h>
  23. #include <linux/bitops.h>
  24. #include <omap3_spi.h>
  25. DECLARE_GLOBAL_DATA_PTR;
  26. struct omap2_mcspi_platform_config {
  27. unsigned int regs_offset;
  28. };
  29. struct omap3_spi_priv {
  30. struct mcspi *regs;
  31. unsigned int cs;
  32. unsigned int freq;
  33. unsigned int mode;
  34. unsigned int wordlen;
  35. unsigned int pin_dir:1;
  36. };
  37. static void omap3_spi_write_chconf(struct omap3_spi_priv *priv, int val)
  38. {
  39. writel(val, &priv->regs->channel[priv->cs].chconf);
  40. /* Flash post writes to make immediate effect */
  41. readl(&priv->regs->channel[priv->cs].chconf);
  42. }
  43. static void omap3_spi_set_enable(struct omap3_spi_priv *priv, int enable)
  44. {
  45. writel(enable, &priv->regs->channel[priv->cs].chctrl);
  46. /* Flash post writes to make immediate effect */
  47. readl(&priv->regs->channel[priv->cs].chctrl);
  48. }
  49. static int omap3_spi_write(struct omap3_spi_priv *priv, unsigned int len,
  50. const void *txp, unsigned long flags)
  51. {
  52. ulong start;
  53. int i, chconf;
  54. chconf = readl(&priv->regs->channel[priv->cs].chconf);
  55. /* Enable the channel */
  56. omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN);
  57. chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
  58. chconf |= (priv->wordlen - 1) << 7;
  59. chconf |= OMAP3_MCSPI_CHCONF_TRM_TX_ONLY;
  60. chconf |= OMAP3_MCSPI_CHCONF_FORCE;
  61. omap3_spi_write_chconf(priv, chconf);
  62. for (i = 0; i < len; i++) {
  63. /* wait till TX register is empty (TXS == 1) */
  64. start = get_timer(0);
  65. while (!(readl(&priv->regs->channel[priv->cs].chstat) &
  66. OMAP3_MCSPI_CHSTAT_TXS)) {
  67. if (get_timer(start) > SPI_WAIT_TIMEOUT) {
  68. printf("SPI TXS timed out, status=0x%08x\n",
  69. readl(&priv->regs->channel[priv->cs].chstat));
  70. return -1;
  71. }
  72. }
  73. /* Write the data */
  74. unsigned int *tx = &priv->regs->channel[priv->cs].tx;
  75. if (priv->wordlen > 16)
  76. writel(((u32 *)txp)[i], tx);
  77. else if (priv->wordlen > 8)
  78. writel(((u16 *)txp)[i], tx);
  79. else
  80. writel(((u8 *)txp)[i], tx);
  81. }
  82. /* wait to finish of transfer */
  83. while ((readl(&priv->regs->channel[priv->cs].chstat) &
  84. (OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS)) !=
  85. (OMAP3_MCSPI_CHSTAT_EOT | OMAP3_MCSPI_CHSTAT_TXS))
  86. ;
  87. /* Disable the channel otherwise the next immediate RX will get affected */
  88. omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS);
  89. if (flags & SPI_XFER_END) {
  90. chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
  91. omap3_spi_write_chconf(priv, chconf);
  92. }
  93. return 0;
  94. }
  95. static int omap3_spi_read(struct omap3_spi_priv *priv, unsigned int len,
  96. void *rxp, unsigned long flags)
  97. {
  98. int i, chconf;
  99. ulong start;
  100. chconf = readl(&priv->regs->channel[priv->cs].chconf);
  101. /* Enable the channel */
  102. omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN);
  103. chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
  104. chconf |= (priv->wordlen - 1) << 7;
  105. chconf |= OMAP3_MCSPI_CHCONF_TRM_RX_ONLY;
  106. chconf |= OMAP3_MCSPI_CHCONF_FORCE;
  107. omap3_spi_write_chconf(priv, chconf);
  108. writel(0, &priv->regs->channel[priv->cs].tx);
  109. for (i = 0; i < len; i++) {
  110. start = get_timer(0);
  111. /* Wait till RX register contains data (RXS == 1) */
  112. while (!(readl(&priv->regs->channel[priv->cs].chstat) &
  113. OMAP3_MCSPI_CHSTAT_RXS)) {
  114. if (get_timer(start) > SPI_WAIT_TIMEOUT) {
  115. printf("SPI RXS timed out, status=0x%08x\n",
  116. readl(&priv->regs->channel[priv->cs].chstat));
  117. return -1;
  118. }
  119. }
  120. /* Disable the channel to prevent furher receiving */
  121. if (i == (len - 1))
  122. omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS);
  123. /* Read the data */
  124. unsigned int *rx = &priv->regs->channel[priv->cs].rx;
  125. if (priv->wordlen > 16)
  126. ((u32 *)rxp)[i] = readl(rx);
  127. else if (priv->wordlen > 8)
  128. ((u16 *)rxp)[i] = (u16)readl(rx);
  129. else
  130. ((u8 *)rxp)[i] = (u8)readl(rx);
  131. }
  132. if (flags & SPI_XFER_END) {
  133. chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
  134. omap3_spi_write_chconf(priv, chconf);
  135. }
  136. return 0;
  137. }
  138. /*McSPI Transmit Receive Mode*/
  139. static int omap3_spi_txrx(struct omap3_spi_priv *priv, unsigned int len,
  140. const void *txp, void *rxp, unsigned long flags)
  141. {
  142. ulong start;
  143. int chconf, i = 0;
  144. chconf = readl(&priv->regs->channel[priv->cs].chconf);
  145. /*Enable SPI channel*/
  146. omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN);
  147. /*set TRANSMIT-RECEIVE Mode*/
  148. chconf &= ~(OMAP3_MCSPI_CHCONF_TRM_MASK | OMAP3_MCSPI_CHCONF_WL_MASK);
  149. chconf |= (priv->wordlen - 1) << 7;
  150. chconf |= OMAP3_MCSPI_CHCONF_FORCE;
  151. omap3_spi_write_chconf(priv, chconf);
  152. /*Shift in and out 1 byte at time*/
  153. for (i=0; i < len; i++){
  154. /* Write: wait for TX empty (TXS == 1)*/
  155. start = get_timer(0);
  156. while (!(readl(&priv->regs->channel[priv->cs].chstat) &
  157. OMAP3_MCSPI_CHSTAT_TXS)) {
  158. if (get_timer(start) > SPI_WAIT_TIMEOUT) {
  159. printf("SPI TXS timed out, status=0x%08x\n",
  160. readl(&priv->regs->channel[priv->cs].chstat));
  161. return -1;
  162. }
  163. }
  164. /* Write the data */
  165. unsigned int *tx = &priv->regs->channel[priv->cs].tx;
  166. if (priv->wordlen > 16)
  167. writel(((u32 *)txp)[i], tx);
  168. else if (priv->wordlen > 8)
  169. writel(((u16 *)txp)[i], tx);
  170. else
  171. writel(((u8 *)txp)[i], tx);
  172. /*Read: wait for RX containing data (RXS == 1)*/
  173. start = get_timer(0);
  174. while (!(readl(&priv->regs->channel[priv->cs].chstat) &
  175. OMAP3_MCSPI_CHSTAT_RXS)) {
  176. if (get_timer(start) > SPI_WAIT_TIMEOUT) {
  177. printf("SPI RXS timed out, status=0x%08x\n",
  178. readl(&priv->regs->channel[priv->cs].chstat));
  179. return -1;
  180. }
  181. }
  182. /* Read the data */
  183. unsigned int *rx = &priv->regs->channel[priv->cs].rx;
  184. if (priv->wordlen > 16)
  185. ((u32 *)rxp)[i] = readl(rx);
  186. else if (priv->wordlen > 8)
  187. ((u16 *)rxp)[i] = (u16)readl(rx);
  188. else
  189. ((u8 *)rxp)[i] = (u8)readl(rx);
  190. }
  191. /* Disable the channel */
  192. omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS);
  193. /*if transfer must be terminated disable the channel*/
  194. if (flags & SPI_XFER_END) {
  195. chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
  196. omap3_spi_write_chconf(priv, chconf);
  197. }
  198. return 0;
  199. }
  200. static int _spi_xfer(struct omap3_spi_priv *priv, unsigned int bitlen,
  201. const void *dout, void *din, unsigned long flags)
  202. {
  203. unsigned int len;
  204. int ret = -1;
  205. if (priv->wordlen < 4 || priv->wordlen > 32) {
  206. printf("omap3_spi: invalid wordlen %d\n", priv->wordlen);
  207. return -1;
  208. }
  209. if (bitlen % priv->wordlen)
  210. return -1;
  211. len = bitlen / priv->wordlen;
  212. if (bitlen == 0) { /* only change CS */
  213. int chconf = readl(&priv->regs->channel[priv->cs].chconf);
  214. if (flags & SPI_XFER_BEGIN) {
  215. omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_EN);
  216. chconf |= OMAP3_MCSPI_CHCONF_FORCE;
  217. omap3_spi_write_chconf(priv, chconf);
  218. }
  219. if (flags & SPI_XFER_END) {
  220. chconf &= ~OMAP3_MCSPI_CHCONF_FORCE;
  221. omap3_spi_write_chconf(priv, chconf);
  222. omap3_spi_set_enable(priv, OMAP3_MCSPI_CHCTRL_DIS);
  223. }
  224. ret = 0;
  225. } else {
  226. if (dout != NULL && din != NULL)
  227. ret = omap3_spi_txrx(priv, len, dout, din, flags);
  228. else if (dout != NULL)
  229. ret = omap3_spi_write(priv, len, dout, flags);
  230. else if (din != NULL)
  231. ret = omap3_spi_read(priv, len, din, flags);
  232. }
  233. return ret;
  234. }
  235. static void _omap3_spi_set_speed(struct omap3_spi_priv *priv)
  236. {
  237. uint32_t confr, div = 0;
  238. confr = readl(&priv->regs->channel[priv->cs].chconf);
  239. /* Calculate clock divisor. Valid range: 0x0 - 0xC ( /1 - /4096 ) */
  240. if (priv->freq) {
  241. while (div <= 0xC && (OMAP3_MCSPI_MAX_FREQ / (1 << div))
  242. > priv->freq)
  243. div++;
  244. } else {
  245. div = 0xC;
  246. }
  247. /* set clock divisor */
  248. confr &= ~OMAP3_MCSPI_CHCONF_CLKD_MASK;
  249. confr |= div << 2;
  250. omap3_spi_write_chconf(priv, confr);
  251. }
  252. static void _omap3_spi_set_mode(struct omap3_spi_priv *priv)
  253. {
  254. uint32_t confr;
  255. confr = readl(&priv->regs->channel[priv->cs].chconf);
  256. /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
  257. * REVISIT: this controller could support SPI_3WIRE mode.
  258. */
  259. if (priv->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
  260. confr &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
  261. confr |= OMAP3_MCSPI_CHCONF_DPE0;
  262. } else {
  263. confr &= ~OMAP3_MCSPI_CHCONF_DPE0;
  264. confr |= OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1;
  265. }
  266. /* set SPI mode 0..3 */
  267. confr &= ~(OMAP3_MCSPI_CHCONF_POL | OMAP3_MCSPI_CHCONF_PHA);
  268. if (priv->mode & SPI_CPHA)
  269. confr |= OMAP3_MCSPI_CHCONF_PHA;
  270. if (priv->mode & SPI_CPOL)
  271. confr |= OMAP3_MCSPI_CHCONF_POL;
  272. /* set chipselect polarity; manage with FORCE */
  273. if (!(priv->mode & SPI_CS_HIGH))
  274. confr |= OMAP3_MCSPI_CHCONF_EPOL; /* active-low; normal */
  275. else
  276. confr &= ~OMAP3_MCSPI_CHCONF_EPOL;
  277. /* Transmit & receive mode */
  278. confr &= ~OMAP3_MCSPI_CHCONF_TRM_MASK;
  279. omap3_spi_write_chconf(priv, confr);
  280. }
  281. static void _omap3_spi_set_wordlen(struct omap3_spi_priv *priv)
  282. {
  283. unsigned int confr;
  284. /* McSPI individual channel configuration */
  285. confr = readl(&priv->regs->channel[priv->cs].chconf);
  286. /* wordlength */
  287. confr &= ~OMAP3_MCSPI_CHCONF_WL_MASK;
  288. confr |= (priv->wordlen - 1) << 7;
  289. omap3_spi_write_chconf(priv, confr);
  290. }
  291. static void spi_reset(struct mcspi *regs)
  292. {
  293. unsigned int tmp;
  294. writel(OMAP3_MCSPI_SYSCONFIG_SOFTRESET, &regs->sysconfig);
  295. do {
  296. tmp = readl(&regs->sysstatus);
  297. } while (!(tmp & OMAP3_MCSPI_SYSSTATUS_RESETDONE));
  298. writel(OMAP3_MCSPI_SYSCONFIG_AUTOIDLE |
  299. OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP |
  300. OMAP3_MCSPI_SYSCONFIG_SMARTIDLE, &regs->sysconfig);
  301. writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, &regs->wakeupenable);
  302. }
  303. static void _omap3_spi_claim_bus(struct omap3_spi_priv *priv)
  304. {
  305. unsigned int conf;
  306. /*
  307. * setup when switching from (reset default) slave mode
  308. * to single-channel master mode
  309. */
  310. conf = readl(&priv->regs->modulctrl);
  311. conf &= ~(OMAP3_MCSPI_MODULCTRL_STEST | OMAP3_MCSPI_MODULCTRL_MS);
  312. conf |= OMAP3_MCSPI_MODULCTRL_SINGLE;
  313. writel(conf, &priv->regs->modulctrl);
  314. }
  315. static int omap3_spi_claim_bus(struct udevice *dev)
  316. {
  317. struct udevice *bus = dev->parent;
  318. struct omap3_spi_priv *priv = dev_get_priv(bus);
  319. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  320. priv->cs = slave_plat->cs;
  321. priv->freq = slave_plat->max_hz;
  322. _omap3_spi_claim_bus(priv);
  323. return 0;
  324. }
  325. static int omap3_spi_release_bus(struct udevice *dev)
  326. {
  327. struct udevice *bus = dev->parent;
  328. struct omap3_spi_priv *priv = dev_get_priv(bus);
  329. writel(OMAP3_MCSPI_MODULCTRL_MS, &priv->regs->modulctrl);
  330. return 0;
  331. }
  332. static int omap3_spi_set_wordlen(struct udevice *dev, unsigned int wordlen)
  333. {
  334. struct udevice *bus = dev->parent;
  335. struct omap3_spi_priv *priv = dev_get_priv(bus);
  336. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  337. priv->cs = slave_plat->cs;
  338. priv->wordlen = wordlen;
  339. _omap3_spi_set_wordlen(priv);
  340. return 0;
  341. }
  342. static int omap3_spi_probe(struct udevice *dev)
  343. {
  344. struct omap3_spi_priv *priv = dev_get_priv(dev);
  345. const void *blob = gd->fdt_blob;
  346. int node = dev_of_offset(dev);
  347. struct omap2_mcspi_platform_config* data =
  348. (struct omap2_mcspi_platform_config*)dev_get_driver_data(dev);
  349. priv->regs = (struct mcspi *)(dev_read_addr(dev) + data->regs_offset);
  350. if (fdtdec_get_bool(blob, node, "ti,pindir-d0-out-d1-in"))
  351. priv->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
  352. else
  353. priv->pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT;
  354. priv->wordlen = SPI_DEFAULT_WORDLEN;
  355. spi_reset(priv->regs);
  356. return 0;
  357. }
  358. static int omap3_spi_xfer(struct udevice *dev, unsigned int bitlen,
  359. const void *dout, void *din, unsigned long flags)
  360. {
  361. struct udevice *bus = dev->parent;
  362. struct omap3_spi_priv *priv = dev_get_priv(bus);
  363. return _spi_xfer(priv, bitlen, dout, din, flags);
  364. }
  365. static int omap3_spi_set_speed(struct udevice *dev, unsigned int speed)
  366. {
  367. struct omap3_spi_priv *priv = dev_get_priv(dev);
  368. priv->freq = speed;
  369. _omap3_spi_set_speed(priv);
  370. return 0;
  371. }
  372. static int omap3_spi_set_mode(struct udevice *dev, uint mode)
  373. {
  374. struct omap3_spi_priv *priv = dev_get_priv(dev);
  375. priv->mode = mode;
  376. _omap3_spi_set_mode(priv);
  377. return 0;
  378. }
  379. static const struct dm_spi_ops omap3_spi_ops = {
  380. .claim_bus = omap3_spi_claim_bus,
  381. .release_bus = omap3_spi_release_bus,
  382. .set_wordlen = omap3_spi_set_wordlen,
  383. .xfer = omap3_spi_xfer,
  384. .set_speed = omap3_spi_set_speed,
  385. .set_mode = omap3_spi_set_mode,
  386. /*
  387. * cs_info is not needed, since we require all chip selects to be
  388. * in the device tree explicitly
  389. */
  390. };
  391. static struct omap2_mcspi_platform_config omap2_pdata = {
  392. .regs_offset = 0,
  393. };
  394. static struct omap2_mcspi_platform_config omap4_pdata = {
  395. .regs_offset = OMAP4_MCSPI_REG_OFFSET,
  396. };
  397. static const struct udevice_id omap3_spi_ids[] = {
  398. { .compatible = "ti,omap2-mcspi", .data = (ulong)&omap2_pdata },
  399. { .compatible = "ti,omap4-mcspi", .data = (ulong)&omap4_pdata },
  400. { }
  401. };
  402. U_BOOT_DRIVER(omap3_spi) = {
  403. .name = "omap3_spi",
  404. .id = UCLASS_SPI,
  405. .of_match = omap3_spi_ids,
  406. .probe = omap3_spi_probe,
  407. .ops = &omap3_spi_ops,
  408. .priv_auto_alloc_size = sizeof(struct omap3_spi_priv),
  409. };