imxdi.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009-2012 ADVANSEE
  4. * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
  5. *
  6. * Based on the Linux rtc-imxdi.c driver, which is:
  7. * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
  8. * Copyright 2010 Orex Computed Radiography
  9. */
  10. /*
  11. * Date & Time support for Freescale i.MX DryIce RTC
  12. */
  13. #include <common.h>
  14. #include <command.h>
  15. #include <linux/compat.h>
  16. #include <rtc.h>
  17. #include <asm/io.h>
  18. #include <asm/arch/imx-regs.h>
  19. /* DryIce Register Definitions */
  20. struct imxdi_regs {
  21. u32 dtcmr; /* Time Counter MSB Reg */
  22. u32 dtclr; /* Time Counter LSB Reg */
  23. u32 dcamr; /* Clock Alarm MSB Reg */
  24. u32 dcalr; /* Clock Alarm LSB Reg */
  25. u32 dcr; /* Control Reg */
  26. u32 dsr; /* Status Reg */
  27. u32 dier; /* Interrupt Enable Reg */
  28. };
  29. #define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */
  30. #define DCR_TCE (1 << 3) /* Time Counter Enable */
  31. #define DSR_WBF (1 << 10) /* Write Busy Flag */
  32. #define DSR_WNF (1 << 9) /* Write Next Flag */
  33. #define DSR_WCF (1 << 8) /* Write Complete Flag */
  34. #define DSR_WEF (1 << 7) /* Write Error Flag */
  35. #define DSR_CAF (1 << 4) /* Clock Alarm Flag */
  36. #define DSR_NVF (1 << 1) /* Non-Valid Flag */
  37. #define DSR_SVF (1 << 0) /* Security Violation Flag */
  38. #define DIER_WNIE (1 << 9) /* Write Next Interrupt Enable */
  39. #define DIER_WCIE (1 << 8) /* Write Complete Interrupt Enable */
  40. #define DIER_WEIE (1 << 7) /* Write Error Interrupt Enable */
  41. #define DIER_CAIE (1 << 4) /* Clock Alarm Interrupt Enable */
  42. /* Driver Private Data */
  43. struct imxdi_data {
  44. struct imxdi_regs __iomem *regs;
  45. int init_done;
  46. };
  47. static struct imxdi_data data;
  48. /*
  49. * This function attempts to clear the dryice write-error flag.
  50. *
  51. * A dryice write error is similar to a bus fault and should not occur in
  52. * normal operation. Clearing the flag requires another write, so the root
  53. * cause of the problem may need to be fixed before the flag can be cleared.
  54. */
  55. static void clear_write_error(void)
  56. {
  57. int cnt;
  58. puts("### Warning: RTC - Register write error!\n");
  59. /* clear the write error flag */
  60. __raw_writel(DSR_WEF, &data.regs->dsr);
  61. /* wait for it to take effect */
  62. for (cnt = 0; cnt < 1000; cnt++) {
  63. if ((__raw_readl(&data.regs->dsr) & DSR_WEF) == 0)
  64. return;
  65. udelay(10);
  66. }
  67. puts("### Error: RTC - Cannot clear write-error flag!\n");
  68. }
  69. /*
  70. * Write a dryice register and wait until it completes.
  71. *
  72. * Use interrupt flags to determine when the write has completed.
  73. */
  74. #define DI_WRITE_WAIT(val, reg) \
  75. ( \
  76. /* do the register write */ \
  77. __raw_writel((val), &data.regs->reg), \
  78. \
  79. di_write_wait((val), #reg) \
  80. )
  81. static int di_write_wait(u32 val, const char *reg)
  82. {
  83. int cnt;
  84. int ret = 0;
  85. int rc = 0;
  86. /* wait for the write to finish */
  87. for (cnt = 0; cnt < 100; cnt++) {
  88. if ((__raw_readl(&data.regs->dsr) & (DSR_WCF | DSR_WEF)) != 0) {
  89. ret = 1;
  90. break;
  91. }
  92. udelay(10);
  93. }
  94. if (ret == 0)
  95. printf("### Warning: RTC - Write-wait timeout "
  96. "val = 0x%.8x reg = %s\n", val, reg);
  97. /* check for write error */
  98. if (__raw_readl(&data.regs->dsr) & DSR_WEF) {
  99. clear_write_error();
  100. rc = -1;
  101. }
  102. return rc;
  103. }
  104. /*
  105. * Initialize dryice hardware
  106. */
  107. static int di_init(void)
  108. {
  109. int rc = 0;
  110. data.regs = (struct imxdi_regs __iomem *)IMX_DRYICE_BASE;
  111. /* mask all interrupts */
  112. __raw_writel(0, &data.regs->dier);
  113. /* put dryice into valid state */
  114. if (__raw_readl(&data.regs->dsr) & DSR_NVF) {
  115. rc = DI_WRITE_WAIT(DSR_NVF | DSR_SVF, dsr);
  116. if (rc)
  117. goto err;
  118. }
  119. /* initialize alarm */
  120. rc = DI_WRITE_WAIT(DCAMR_UNSET, dcamr);
  121. if (rc)
  122. goto err;
  123. rc = DI_WRITE_WAIT(0, dcalr);
  124. if (rc)
  125. goto err;
  126. /* clear alarm flag */
  127. if (__raw_readl(&data.regs->dsr) & DSR_CAF) {
  128. rc = DI_WRITE_WAIT(DSR_CAF, dsr);
  129. if (rc)
  130. goto err;
  131. }
  132. /* the timer won't count if it has never been written to */
  133. if (__raw_readl(&data.regs->dtcmr) == 0) {
  134. rc = DI_WRITE_WAIT(0, dtcmr);
  135. if (rc)
  136. goto err;
  137. }
  138. /* start keeping time */
  139. if (!(__raw_readl(&data.regs->dcr) & DCR_TCE)) {
  140. rc = DI_WRITE_WAIT(__raw_readl(&data.regs->dcr) | DCR_TCE, dcr);
  141. if (rc)
  142. goto err;
  143. }
  144. data.init_done = 1;
  145. return 0;
  146. err:
  147. return rc;
  148. }
  149. int rtc_get(struct rtc_time *tmp)
  150. {
  151. unsigned long now;
  152. int rc = 0;
  153. if (!data.init_done) {
  154. rc = di_init();
  155. if (rc)
  156. goto err;
  157. }
  158. now = __raw_readl(&data.regs->dtcmr);
  159. rtc_to_tm(now, tmp);
  160. err:
  161. return rc;
  162. }
  163. int rtc_set(struct rtc_time *tmp)
  164. {
  165. unsigned long now;
  166. int rc;
  167. if (!data.init_done) {
  168. rc = di_init();
  169. if (rc)
  170. goto err;
  171. }
  172. now = rtc_mktime(tmp);
  173. /* zero the fractional part first */
  174. rc = DI_WRITE_WAIT(0, dtclr);
  175. if (rc == 0)
  176. rc = DI_WRITE_WAIT(now, dtcmr);
  177. err:
  178. return rc;
  179. }
  180. void rtc_reset(void)
  181. {
  182. di_init();
  183. }