ds1337.c 5.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2001-2008
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. * Keith Outwater, keith_outwater@mvis.com`
  6. */
  7. /*
  8. * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
  9. * DS1337 Real Time Clock (RTC).
  10. */
  11. #include <common.h>
  12. #include <command.h>
  13. #include <rtc.h>
  14. #include <i2c.h>
  15. /*
  16. * RTC register addresses
  17. */
  18. #if defined CONFIG_RTC_DS1337
  19. #define RTC_SEC_REG_ADDR 0x0
  20. #define RTC_MIN_REG_ADDR 0x1
  21. #define RTC_HR_REG_ADDR 0x2
  22. #define RTC_DAY_REG_ADDR 0x3
  23. #define RTC_DATE_REG_ADDR 0x4
  24. #define RTC_MON_REG_ADDR 0x5
  25. #define RTC_YR_REG_ADDR 0x6
  26. #define RTC_CTL_REG_ADDR 0x0e
  27. #define RTC_STAT_REG_ADDR 0x0f
  28. #define RTC_TC_REG_ADDR 0x10
  29. #elif defined CONFIG_RTC_DS1388
  30. #define RTC_SEC_REG_ADDR 0x1
  31. #define RTC_MIN_REG_ADDR 0x2
  32. #define RTC_HR_REG_ADDR 0x3
  33. #define RTC_DAY_REG_ADDR 0x4
  34. #define RTC_DATE_REG_ADDR 0x5
  35. #define RTC_MON_REG_ADDR 0x6
  36. #define RTC_YR_REG_ADDR 0x7
  37. #define RTC_CTL_REG_ADDR 0x0c
  38. #define RTC_STAT_REG_ADDR 0x0b
  39. #define RTC_TC_REG_ADDR 0x0a
  40. #endif
  41. /*
  42. * RTC control register bits
  43. */
  44. #define RTC_CTL_BIT_A1IE 0x1 /* Alarm 1 interrupt enable */
  45. #define RTC_CTL_BIT_A2IE 0x2 /* Alarm 2 interrupt enable */
  46. #define RTC_CTL_BIT_INTCN 0x4 /* Interrupt control */
  47. #define RTC_CTL_BIT_RS1 0x8 /* Rate select 1 */
  48. #define RTC_CTL_BIT_RS2 0x10 /* Rate select 2 */
  49. #define RTC_CTL_BIT_DOSC 0x80 /* Disable Oscillator */
  50. /*
  51. * RTC status register bits
  52. */
  53. #define RTC_STAT_BIT_A1F 0x1 /* Alarm 1 flag */
  54. #define RTC_STAT_BIT_A2F 0x2 /* Alarm 2 flag */
  55. #define RTC_STAT_BIT_OSF 0x80 /* Oscillator stop flag */
  56. static uchar rtc_read (uchar reg);
  57. static void rtc_write (uchar reg, uchar val);
  58. /*
  59. * Get the current time from the RTC
  60. */
  61. int rtc_get (struct rtc_time *tmp)
  62. {
  63. int rel = 0;
  64. uchar sec, min, hour, mday, wday, mon_cent, year, control, status;
  65. control = rtc_read (RTC_CTL_REG_ADDR);
  66. status = rtc_read (RTC_STAT_REG_ADDR);
  67. sec = rtc_read (RTC_SEC_REG_ADDR);
  68. min = rtc_read (RTC_MIN_REG_ADDR);
  69. hour = rtc_read (RTC_HR_REG_ADDR);
  70. wday = rtc_read (RTC_DAY_REG_ADDR);
  71. mday = rtc_read (RTC_DATE_REG_ADDR);
  72. mon_cent = rtc_read (RTC_MON_REG_ADDR);
  73. year = rtc_read (RTC_YR_REG_ADDR);
  74. /* No century bit, assume year 2000 */
  75. #ifdef CONFIG_RTC_DS1388
  76. mon_cent |= 0x80;
  77. #endif
  78. debug("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
  79. "hr: %02x min: %02x sec: %02x control: %02x status: %02x\n",
  80. year, mon_cent, mday, wday, hour, min, sec, control, status);
  81. if (status & RTC_STAT_BIT_OSF) {
  82. printf ("### Warning: RTC oscillator has stopped\n");
  83. /* clear the OSF flag */
  84. rtc_write (RTC_STAT_REG_ADDR,
  85. rtc_read (RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF);
  86. rel = -1;
  87. }
  88. tmp->tm_sec = bcd2bin (sec & 0x7F);
  89. tmp->tm_min = bcd2bin (min & 0x7F);
  90. tmp->tm_hour = bcd2bin (hour & 0x3F);
  91. tmp->tm_mday = bcd2bin (mday & 0x3F);
  92. tmp->tm_mon = bcd2bin (mon_cent & 0x1F);
  93. tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 2000 : 1900);
  94. tmp->tm_wday = bcd2bin ((wday - 1) & 0x07);
  95. tmp->tm_yday = 0;
  96. tmp->tm_isdst= 0;
  97. debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
  98. tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
  99. tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
  100. return rel;
  101. }
  102. /*
  103. * Set the RTC
  104. */
  105. int rtc_set (struct rtc_time *tmp)
  106. {
  107. uchar century;
  108. debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
  109. tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
  110. tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
  111. rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
  112. century = (tmp->tm_year >= 2000) ? 0x80 : 0;
  113. rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon) | century);
  114. rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1));
  115. rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
  116. rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
  117. rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
  118. rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
  119. return 0;
  120. }
  121. /*
  122. * Reset the RTC. We also enable the oscillator output on the
  123. * SQW/INTB* pin and program it for 32,768 Hz output. Note that
  124. * according to the datasheet, turning on the square wave output
  125. * increases the current drain on the backup battery from about
  126. * 600 nA to 2uA. Define CONFIG_RTC_DS1337_NOOSC if you wish to turn
  127. * off the OSC output.
  128. */
  129. #ifdef CONFIG_RTC_DS1337_NOOSC
  130. #define RTC_DS1337_RESET_VAL \
  131. (RTC_CTL_BIT_INTCN | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2)
  132. #else
  133. #define RTC_DS1337_RESET_VAL (RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2)
  134. #endif
  135. void rtc_reset (void)
  136. {
  137. #ifdef CONFIG_RTC_DS1337
  138. rtc_write (RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL);
  139. #elif defined CONFIG_RTC_DS1388
  140. rtc_write(RTC_CTL_REG_ADDR, 0x0); /* hw default */
  141. #endif
  142. #ifdef CONFIG_RTC_DS1339_TCR_VAL
  143. rtc_write (RTC_TC_REG_ADDR, CONFIG_RTC_DS1339_TCR_VAL);
  144. #endif
  145. #ifdef CONFIG_RTC_DS1388_TCR_VAL
  146. rtc_write(RTC_TC_REG_ADDR, CONFIG_RTC_DS1388_TCR_VAL);
  147. #endif
  148. }
  149. /*
  150. * Helper functions
  151. */
  152. static
  153. uchar rtc_read (uchar reg)
  154. {
  155. return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
  156. }
  157. static void rtc_write (uchar reg, uchar val)
  158. {
  159. i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
  160. }