fsl_sata.c 22 KB

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  1. /*
  2. * Copyright (C) 2008,2010 Freescale Semiconductor, Inc.
  3. * Dave Liu <daveliu@freescale.com>
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #include <common.h>
  8. #include <command.h>
  9. #include <console.h>
  10. #include <asm/io.h>
  11. #include <asm/processor.h>
  12. #include <asm/fsl_serdes.h>
  13. #include <malloc.h>
  14. #include <libata.h>
  15. #include <fis.h>
  16. #include <sata.h>
  17. #include "fsl_sata.h"
  18. #ifndef CONFIG_SYS_SATA1_FLAGS
  19. #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  20. #endif
  21. #ifndef CONFIG_SYS_SATA2_FLAGS
  22. #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  23. #endif
  24. static struct fsl_sata_info fsl_sata_info[] = {
  25. #ifdef CONFIG_SATA1
  26. {CONFIG_SYS_SATA1, CONFIG_SYS_SATA1_FLAGS},
  27. #else
  28. {0, 0},
  29. #endif
  30. #ifdef CONFIG_SATA2
  31. {CONFIG_SYS_SATA2, CONFIG_SYS_SATA2_FLAGS},
  32. #else
  33. {0, 0},
  34. #endif
  35. };
  36. static inline void sdelay(unsigned long sec)
  37. {
  38. unsigned long i;
  39. for (i = 0; i < sec; i++)
  40. mdelay(1000);
  41. }
  42. static void fsl_sata_dump_sfis(struct sata_fis_d2h *s)
  43. {
  44. printf("Status FIS dump:\n\r");
  45. printf("fis_type: %02x\n\r", s->fis_type);
  46. printf("pm_port_i: %02x\n\r", s->pm_port_i);
  47. printf("status: %02x\n\r", s->status);
  48. printf("error: %02x\n\r", s->error);
  49. printf("lba_low: %02x\n\r", s->lba_low);
  50. printf("lba_mid: %02x\n\r", s->lba_mid);
  51. printf("lba_high: %02x\n\r", s->lba_high);
  52. printf("device: %02x\n\r", s->device);
  53. printf("lba_low_exp: %02x\n\r", s->lba_low_exp);
  54. printf("lba_mid_exp: %02x\n\r", s->lba_mid_exp);
  55. printf("lba_high_exp: %02x\n\r", s->lba_high_exp);
  56. printf("res1: %02x\n\r", s->res1);
  57. printf("sector_count: %02x\n\r", s->sector_count);
  58. printf("sector_count_exp: %02x\n\r", s->sector_count_exp);
  59. }
  60. static int ata_wait_register(unsigned __iomem *addr, u32 mask,
  61. u32 val, u32 timeout_msec)
  62. {
  63. int i;
  64. u32 temp;
  65. for (i = 0; (((temp = in_le32(addr)) & mask) != val)
  66. && i < timeout_msec; i++)
  67. mdelay(1);
  68. return (i < timeout_msec) ? 0 : -1;
  69. }
  70. int init_sata(int dev)
  71. {
  72. u32 length, align;
  73. cmd_hdr_tbl_t *cmd_hdr;
  74. u32 cda;
  75. u32 val32;
  76. fsl_sata_reg_t __iomem *reg;
  77. u32 sig;
  78. int i;
  79. fsl_sata_t *sata;
  80. if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
  81. printf("the sata index %d is out of ranges\n\r", dev);
  82. return -1;
  83. }
  84. #ifdef CONFIG_MPC85xx
  85. if ((dev == 0) && (!is_serdes_configured(SATA1))) {
  86. printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev);
  87. return -1;
  88. }
  89. if ((dev == 1) && (!is_serdes_configured(SATA2))) {
  90. printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev);
  91. return -1;
  92. }
  93. #endif
  94. /* Allocate SATA device driver struct */
  95. sata = (fsl_sata_t *)malloc(sizeof(fsl_sata_t));
  96. if (!sata) {
  97. printf("alloc the sata device struct failed\n\r");
  98. return -1;
  99. }
  100. /* Zero all of the device driver struct */
  101. memset((void *)sata, 0, sizeof(fsl_sata_t));
  102. /* Save the private struct to block device struct */
  103. sata_dev_desc[dev].priv = (void *)sata;
  104. snprintf(sata->name, 12, "SATA%d", dev);
  105. /* Set the controller register base address to device struct */
  106. reg = (fsl_sata_reg_t *)(fsl_sata_info[dev].sata_reg_base);
  107. sata->reg_base = reg;
  108. /* Allocate the command header table, 4 bytes aligned */
  109. length = sizeof(struct cmd_hdr_tbl);
  110. align = SATA_HC_CMD_HDR_TBL_ALIGN;
  111. sata->cmd_hdr_tbl_offset = (void *)malloc(length + align);
  112. if (!sata) {
  113. printf("alloc the command header failed\n\r");
  114. return -1;
  115. }
  116. cmd_hdr = (cmd_hdr_tbl_t *)(((u32)sata->cmd_hdr_tbl_offset + align)
  117. & ~(align - 1));
  118. sata->cmd_hdr = cmd_hdr;
  119. /* Zero all of the command header table */
  120. memset((void *)sata->cmd_hdr_tbl_offset, 0, length + align);
  121. /* Allocate command descriptor for all command */
  122. length = sizeof(struct cmd_desc) * SATA_HC_MAX_CMD;
  123. align = SATA_HC_CMD_DESC_ALIGN;
  124. sata->cmd_desc_offset = (void *)malloc(length + align);
  125. if (!sata->cmd_desc_offset) {
  126. printf("alloc the command descriptor failed\n\r");
  127. return -1;
  128. }
  129. sata->cmd_desc = (cmd_desc_t *)(((u32)sata->cmd_desc_offset + align)
  130. & ~(align - 1));
  131. /* Zero all of command descriptor */
  132. memset((void *)sata->cmd_desc_offset, 0, length + align);
  133. /* Link the command descriptor to command header */
  134. for (i = 0; i < SATA_HC_MAX_CMD; i++) {
  135. cda = ((u32)sata->cmd_desc + SATA_HC_CMD_DESC_SIZE * i)
  136. & ~(CMD_HDR_CDA_ALIGN - 1);
  137. cmd_hdr->cmd_slot[i].cda = cpu_to_le32(cda);
  138. }
  139. /* To have safe state, force the controller offline */
  140. val32 = in_le32(&reg->hcontrol);
  141. val32 &= ~HCONTROL_ONOFF;
  142. val32 |= HCONTROL_FORCE_OFFLINE;
  143. out_le32(&reg->hcontrol, val32);
  144. /* Wait the controller offline */
  145. ata_wait_register(&reg->hstatus, HSTATUS_ONOFF, 0, 1000);
  146. /* Set the command header base address to CHBA register to tell DMA */
  147. out_le32(&reg->chba, (u32)cmd_hdr & ~0x3);
  148. /* Snoop for the command header */
  149. val32 = in_le32(&reg->hcontrol);
  150. val32 |= HCONTROL_HDR_SNOOP;
  151. out_le32(&reg->hcontrol, val32);
  152. /* Disable all of interrupts */
  153. val32 = in_le32(&reg->hcontrol);
  154. val32 &= ~HCONTROL_INT_EN_ALL;
  155. out_le32(&reg->hcontrol, val32);
  156. /* Clear all of interrupts */
  157. val32 = in_le32(&reg->hstatus);
  158. out_le32(&reg->hstatus, val32);
  159. /* Set the ICC, no interrupt coalescing */
  160. out_le32(&reg->icc, 0x01000000);
  161. /* No PM attatched, the SATA device direct connect */
  162. out_le32(&reg->cqpmp, 0);
  163. /* Clear SError register */
  164. val32 = in_le32(&reg->serror);
  165. out_le32(&reg->serror, val32);
  166. /* Clear CER register */
  167. val32 = in_le32(&reg->cer);
  168. out_le32(&reg->cer, val32);
  169. /* Clear DER register */
  170. val32 = in_le32(&reg->der);
  171. out_le32(&reg->der, val32);
  172. /* No device detection or initialization action requested */
  173. out_le32(&reg->scontrol, 0x00000300);
  174. /* Configure the transport layer, default value */
  175. out_le32(&reg->transcfg, 0x08000016);
  176. /* Configure the link layer, default value */
  177. out_le32(&reg->linkcfg, 0x0000ff34);
  178. /* Bring the controller online */
  179. val32 = in_le32(&reg->hcontrol);
  180. val32 |= HCONTROL_ONOFF;
  181. out_le32(&reg->hcontrol, val32);
  182. mdelay(100);
  183. /* print sata device name */
  184. if (!dev)
  185. printf("%s ", sata->name);
  186. else
  187. printf(" %s ", sata->name);
  188. /* Wait PHY RDY signal changed for 500ms */
  189. ata_wait_register(&reg->hstatus, HSTATUS_PHY_RDY,
  190. HSTATUS_PHY_RDY, 500);
  191. /* Check PHYRDY */
  192. val32 = in_le32(&reg->hstatus);
  193. if (val32 & HSTATUS_PHY_RDY) {
  194. sata->link = 1;
  195. } else {
  196. sata->link = 0;
  197. printf("(No RDY)\n\r");
  198. return -1;
  199. }
  200. /* Wait for signature updated, which is 1st D2H */
  201. ata_wait_register(&reg->hstatus, HSTATUS_SIGNATURE,
  202. HSTATUS_SIGNATURE, 10000);
  203. if (val32 & HSTATUS_SIGNATURE) {
  204. sig = in_le32(&reg->sig);
  205. debug("Signature updated, the sig =%08x\n\r", sig);
  206. sata->ata_device_type = ata_dev_classify(sig);
  207. }
  208. /* Check the speed */
  209. val32 = in_le32(&reg->sstatus);
  210. if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN1)
  211. printf("(1.5 Gbps)\n\r");
  212. else if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN2)
  213. printf("(3 Gbps)\n\r");
  214. return 0;
  215. }
  216. int reset_sata(int dev)
  217. {
  218. return 0;
  219. }
  220. static void fsl_sata_dump_regs(fsl_sata_reg_t __iomem *reg)
  221. {
  222. printf("\n\rSATA: %08x\n\r", (u32)reg);
  223. printf("CQR: %08x\n\r", in_le32(&reg->cqr));
  224. printf("CAR: %08x\n\r", in_le32(&reg->car));
  225. printf("CCR: %08x\n\r", in_le32(&reg->ccr));
  226. printf("CER: %08x\n\r", in_le32(&reg->cer));
  227. printf("CQR: %08x\n\r", in_le32(&reg->cqr));
  228. printf("DER: %08x\n\r", in_le32(&reg->der));
  229. printf("CHBA: %08x\n\r", in_le32(&reg->chba));
  230. printf("HStatus: %08x\n\r", in_le32(&reg->hstatus));
  231. printf("HControl: %08x\n\r", in_le32(&reg->hcontrol));
  232. printf("CQPMP: %08x\n\r", in_le32(&reg->cqpmp));
  233. printf("SIG: %08x\n\r", in_le32(&reg->sig));
  234. printf("ICC: %08x\n\r", in_le32(&reg->icc));
  235. printf("SStatus: %08x\n\r", in_le32(&reg->sstatus));
  236. printf("SError: %08x\n\r", in_le32(&reg->serror));
  237. printf("SControl: %08x\n\r", in_le32(&reg->scontrol));
  238. printf("SNotification: %08x\n\r", in_le32(&reg->snotification));
  239. printf("TransCfg: %08x\n\r", in_le32(&reg->transcfg));
  240. printf("TransStatus: %08x\n\r", in_le32(&reg->transstatus));
  241. printf("LinkCfg: %08x\n\r", in_le32(&reg->linkcfg));
  242. printf("LinkCfg1: %08x\n\r", in_le32(&reg->linkcfg1));
  243. printf("LinkCfg2: %08x\n\r", in_le32(&reg->linkcfg2));
  244. printf("LinkStatus: %08x\n\r", in_le32(&reg->linkstatus));
  245. printf("LinkStatus1: %08x\n\r", in_le32(&reg->linkstatus1));
  246. printf("PhyCtrlCfg: %08x\n\r", in_le32(&reg->phyctrlcfg));
  247. printf("SYSPR: %08x\n\r", in_be32(&reg->syspr));
  248. }
  249. static int fsl_ata_exec_ata_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
  250. int is_ncq, int tag, u8 *buffer, u32 len)
  251. {
  252. cmd_hdr_entry_t *cmd_hdr;
  253. cmd_desc_t *cmd_desc;
  254. sata_fis_h2d_t *h2d;
  255. prd_entry_t *prde;
  256. u32 ext_c_ddc;
  257. u32 prde_count;
  258. u32 val32;
  259. u32 ttl;
  260. fsl_sata_reg_t __iomem *reg = sata->reg_base;
  261. int i;
  262. /* Check xfer length */
  263. if (len > SATA_HC_MAX_XFER_LEN) {
  264. printf("max transfer length is 64MB\n\r");
  265. return 0;
  266. }
  267. /* Setup the command descriptor */
  268. cmd_desc = sata->cmd_desc + tag;
  269. /* Get the pointer cfis of command descriptor */
  270. h2d = (sata_fis_h2d_t *)cmd_desc->cfis;
  271. /* Zero the cfis of command descriptor */
  272. memset((void *)h2d, 0, SATA_HC_CMD_DESC_CFIS_SIZE);
  273. /* Copy the cfis from user to command descriptor */
  274. h2d->fis_type = cfis->fis_type;
  275. h2d->pm_port_c = cfis->pm_port_c;
  276. h2d->command = cfis->command;
  277. h2d->features = cfis->features;
  278. h2d->features_exp = cfis->features_exp;
  279. h2d->lba_low = cfis->lba_low;
  280. h2d->lba_mid = cfis->lba_mid;
  281. h2d->lba_high = cfis->lba_high;
  282. h2d->lba_low_exp = cfis->lba_low_exp;
  283. h2d->lba_mid_exp = cfis->lba_mid_exp;
  284. h2d->lba_high_exp = cfis->lba_high_exp;
  285. if (!is_ncq) {
  286. h2d->sector_count = cfis->sector_count;
  287. h2d->sector_count_exp = cfis->sector_count_exp;
  288. } else { /* NCQ */
  289. h2d->sector_count = (u8)(tag << 3);
  290. }
  291. h2d->device = cfis->device;
  292. h2d->control = cfis->control;
  293. /* Setup the PRD table */
  294. prde = (prd_entry_t *)cmd_desc->prdt;
  295. memset((void *)prde, 0, sizeof(struct prdt));
  296. prde_count = 0;
  297. ttl = len;
  298. for (i = 0; i < SATA_HC_MAX_PRD_DIRECT; i++) {
  299. if (!len)
  300. break;
  301. prde->dba = cpu_to_le32((u32)buffer & ~0x3);
  302. debug("dba = %08x\n\r", (u32)buffer);
  303. if (len < PRD_ENTRY_MAX_XFER_SZ) {
  304. ext_c_ddc = PRD_ENTRY_DATA_SNOOP | len;
  305. debug("ext_c_ddc1 = %08x, len = %08x\n\r", ext_c_ddc, len);
  306. prde->ext_c_ddc = cpu_to_le32(ext_c_ddc);
  307. prde_count++;
  308. prde++;
  309. break;
  310. } else {
  311. ext_c_ddc = PRD_ENTRY_DATA_SNOOP; /* 4M bytes */
  312. debug("ext_c_ddc2 = %08x, len = %08x\n\r", ext_c_ddc, len);
  313. prde->ext_c_ddc = cpu_to_le32(ext_c_ddc);
  314. buffer += PRD_ENTRY_MAX_XFER_SZ;
  315. len -= PRD_ENTRY_MAX_XFER_SZ;
  316. prde_count++;
  317. prde++;
  318. }
  319. }
  320. /* Setup the command slot of cmd hdr */
  321. cmd_hdr = (cmd_hdr_entry_t *)&sata->cmd_hdr->cmd_slot[tag];
  322. cmd_hdr->cda = cpu_to_le32((u32)cmd_desc & ~0x3);
  323. val32 = prde_count << CMD_HDR_PRD_ENTRY_SHIFT;
  324. val32 |= sizeof(sata_fis_h2d_t);
  325. cmd_hdr->prde_fis_len = cpu_to_le32(val32);
  326. cmd_hdr->ttl = cpu_to_le32(ttl);
  327. if (!is_ncq) {
  328. val32 = CMD_HDR_ATTR_RES | CMD_HDR_ATTR_SNOOP;
  329. } else {
  330. val32 = CMD_HDR_ATTR_RES | CMD_HDR_ATTR_SNOOP | CMD_HDR_ATTR_FPDMA;
  331. }
  332. tag &= CMD_HDR_ATTR_TAG;
  333. val32 |= tag;
  334. debug("attribute = %08x\n\r", val32);
  335. cmd_hdr->attribute = cpu_to_le32(val32);
  336. /* Make sure cmd desc and cmd slot valid before command issue */
  337. sync();
  338. /* PMP*/
  339. val32 = (u32)(h2d->pm_port_c & 0x0f);
  340. out_le32(&reg->cqpmp, val32);
  341. /* Wait no active */
  342. if (ata_wait_register(&reg->car, (1 << tag), 0, 10000))
  343. printf("Wait no active time out\n\r");
  344. /* Issue command */
  345. if (!(in_le32(&reg->cqr) & (1 << tag))) {
  346. val32 = 1 << tag;
  347. out_le32(&reg->cqr, val32);
  348. }
  349. /* Wait command completed for 10s */
  350. if (ata_wait_register(&reg->ccr, (1 << tag), (1 << tag), 10000)) {
  351. if (!is_ncq)
  352. printf("Non-NCQ command time out\n\r");
  353. else
  354. printf("NCQ command time out\n\r");
  355. }
  356. val32 = in_le32(&reg->cer);
  357. if (val32) {
  358. u32 der;
  359. fsl_sata_dump_sfis((struct sata_fis_d2h *)cmd_desc->sfis);
  360. printf("CE at device\n\r");
  361. fsl_sata_dump_regs(reg);
  362. der = in_le32(&reg->der);
  363. out_le32(&reg->cer, val32);
  364. out_le32(&reg->der, der);
  365. }
  366. /* Clear complete flags */
  367. val32 = in_le32(&reg->ccr);
  368. out_le32(&reg->ccr, val32);
  369. return len;
  370. }
  371. static int fsl_ata_exec_reset_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
  372. int tag, u8 *buffer, u32 len)
  373. {
  374. return 0;
  375. }
  376. static int fsl_sata_exec_cmd(struct fsl_sata *sata, struct sata_fis_h2d *cfis,
  377. enum cmd_type command_type, int tag, u8 *buffer, u32 len)
  378. {
  379. int rc;
  380. if (tag > SATA_HC_MAX_CMD || tag < 0) {
  381. printf("tag is out of range, tag=%d\n\r", tag);
  382. return -1;
  383. }
  384. switch (command_type) {
  385. case CMD_ATA:
  386. rc = fsl_ata_exec_ata_cmd(sata, cfis, 0, tag, buffer, len);
  387. return rc;
  388. case CMD_RESET:
  389. rc = fsl_ata_exec_reset_cmd(sata, cfis, tag, buffer, len);
  390. return rc;
  391. case CMD_NCQ:
  392. rc = fsl_ata_exec_ata_cmd(sata, cfis, 1, tag, buffer, len);
  393. return rc;
  394. case CMD_ATAPI:
  395. case CMD_VENDOR_BIST:
  396. case CMD_BIST:
  397. printf("not support now\n\r");
  398. return -1;
  399. default:
  400. break;
  401. }
  402. return -1;
  403. }
  404. static void fsl_sata_identify(int dev, u16 *id)
  405. {
  406. fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
  407. struct sata_fis_h2d h2d, *cfis = &h2d;
  408. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  409. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  410. cfis->pm_port_c = 0x80; /* is command */
  411. cfis->command = ATA_CMD_ID_ATA;
  412. fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, (u8 *)id, ATA_ID_WORDS * 2);
  413. ata_swap_buf_le16(id, ATA_ID_WORDS);
  414. }
  415. static void fsl_sata_xfer_mode(int dev, u16 *id)
  416. {
  417. fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
  418. sata->pio = id[ATA_ID_PIO_MODES];
  419. sata->mwdma = id[ATA_ID_MWDMA_MODES];
  420. sata->udma = id[ATA_ID_UDMA_MODES];
  421. debug("pio %04x, mwdma %04x, udma %04x\n\r", sata->pio, sata->mwdma, sata->udma);
  422. }
  423. static void fsl_sata_set_features(int dev)
  424. {
  425. fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
  426. struct sata_fis_h2d h2d, *cfis = &h2d;
  427. u8 udma_cap;
  428. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  429. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  430. cfis->pm_port_c = 0x80; /* is command */
  431. cfis->command = ATA_CMD_SET_FEATURES;
  432. cfis->features = SETFEATURES_XFER;
  433. /* First check the device capablity */
  434. udma_cap = (u8)(sata->udma & 0xff);
  435. debug("udma_cap %02x\n\r", udma_cap);
  436. if (udma_cap == ATA_UDMA6)
  437. cfis->sector_count = XFER_UDMA_6;
  438. if (udma_cap == ATA_UDMA5)
  439. cfis->sector_count = XFER_UDMA_5;
  440. if (udma_cap == ATA_UDMA4)
  441. cfis->sector_count = XFER_UDMA_4;
  442. if (udma_cap == ATA_UDMA3)
  443. cfis->sector_count = XFER_UDMA_3;
  444. fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
  445. }
  446. static u32 fsl_sata_rw_cmd(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write)
  447. {
  448. fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
  449. struct sata_fis_h2d h2d, *cfis = &h2d;
  450. u32 block;
  451. block = start;
  452. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  453. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  454. cfis->pm_port_c = 0x80; /* is command */
  455. cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
  456. cfis->device = ATA_LBA;
  457. cfis->device |= (block >> 24) & 0xf;
  458. cfis->lba_high = (block >> 16) & 0xff;
  459. cfis->lba_mid = (block >> 8) & 0xff;
  460. cfis->lba_low = block & 0xff;
  461. cfis->sector_count = (u8)(blkcnt & 0xff);
  462. fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, buffer, ATA_SECT_SIZE * blkcnt);
  463. return blkcnt;
  464. }
  465. static void fsl_sata_flush_cache(int dev)
  466. {
  467. fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
  468. struct sata_fis_h2d h2d, *cfis = &h2d;
  469. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  470. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  471. cfis->pm_port_c = 0x80; /* is command */
  472. cfis->command = ATA_CMD_FLUSH;
  473. fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
  474. }
  475. static u32 fsl_sata_rw_cmd_ext(int dev, u32 start, u32 blkcnt, u8 *buffer, int is_write)
  476. {
  477. fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
  478. struct sata_fis_h2d h2d, *cfis = &h2d;
  479. u64 block;
  480. block = (u64)start;
  481. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  482. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  483. cfis->pm_port_c = 0x80; /* is command */
  484. cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
  485. : ATA_CMD_READ_EXT;
  486. cfis->lba_high_exp = (block >> 40) & 0xff;
  487. cfis->lba_mid_exp = (block >> 32) & 0xff;
  488. cfis->lba_low_exp = (block >> 24) & 0xff;
  489. cfis->lba_high = (block >> 16) & 0xff;
  490. cfis->lba_mid = (block >> 8) & 0xff;
  491. cfis->lba_low = block & 0xff;
  492. cfis->device = ATA_LBA;
  493. cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
  494. cfis->sector_count = blkcnt & 0xff;
  495. fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, buffer, ATA_SECT_SIZE * blkcnt);
  496. return blkcnt;
  497. }
  498. static u32 fsl_sata_rw_ncq_cmd(int dev, u32 start, u32 blkcnt, u8 *buffer,
  499. int is_write)
  500. {
  501. fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
  502. struct sata_fis_h2d h2d, *cfis = &h2d;
  503. int ncq_channel;
  504. u64 block;
  505. if (sata->lba48 != 1) {
  506. printf("execute FPDMA command on non-LBA48 hard disk\n\r");
  507. return -1;
  508. }
  509. block = (u64)start;
  510. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  511. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  512. cfis->pm_port_c = 0x80; /* is command */
  513. cfis->command = (is_write) ? ATA_CMD_FPDMA_WRITE
  514. : ATA_CMD_FPDMA_READ;
  515. cfis->lba_high_exp = (block >> 40) & 0xff;
  516. cfis->lba_mid_exp = (block >> 32) & 0xff;
  517. cfis->lba_low_exp = (block >> 24) & 0xff;
  518. cfis->lba_high = (block >> 16) & 0xff;
  519. cfis->lba_mid = (block >> 8) & 0xff;
  520. cfis->lba_low = block & 0xff;
  521. cfis->device = ATA_LBA;
  522. cfis->features_exp = (blkcnt >> 8) & 0xff;
  523. cfis->features = blkcnt & 0xff;
  524. if (sata->queue_depth >= SATA_HC_MAX_CMD)
  525. ncq_channel = SATA_HC_MAX_CMD - 1;
  526. else
  527. ncq_channel = sata->queue_depth - 1;
  528. /* Use the latest queue */
  529. fsl_sata_exec_cmd(sata, cfis, CMD_NCQ, ncq_channel, buffer, ATA_SECT_SIZE * blkcnt);
  530. return blkcnt;
  531. }
  532. static void fsl_sata_flush_cache_ext(int dev)
  533. {
  534. fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
  535. struct sata_fis_h2d h2d, *cfis = &h2d;
  536. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  537. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  538. cfis->pm_port_c = 0x80; /* is command */
  539. cfis->command = ATA_CMD_FLUSH_EXT;
  540. fsl_sata_exec_cmd(sata, cfis, CMD_ATA, 0, NULL, 0);
  541. }
  542. static void fsl_sata_init_wcache(int dev, u16 *id)
  543. {
  544. fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
  545. if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
  546. sata->wcache = 1;
  547. if (ata_id_has_flush(id))
  548. sata->flush = 1;
  549. if (ata_id_has_flush_ext(id))
  550. sata->flush_ext = 1;
  551. }
  552. static int fsl_sata_get_wcache(int dev)
  553. {
  554. fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
  555. return sata->wcache;
  556. }
  557. static int fsl_sata_get_flush(int dev)
  558. {
  559. fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
  560. return sata->flush;
  561. }
  562. static int fsl_sata_get_flush_ext(int dev)
  563. {
  564. fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
  565. return sata->flush_ext;
  566. }
  567. static u32 ata_low_level_rw_lba48(int dev, u32 blknr, lbaint_t blkcnt,
  568. const void *buffer, int is_write)
  569. {
  570. u32 start, blks;
  571. u8 *addr;
  572. int max_blks;
  573. start = blknr;
  574. blks = blkcnt;
  575. addr = (u8 *)buffer;
  576. max_blks = ATA_MAX_SECTORS_LBA48;
  577. do {
  578. if (blks > max_blks) {
  579. if (fsl_sata_info[dev].flags != FLAGS_FPDMA)
  580. fsl_sata_rw_cmd_ext(dev, start, max_blks, addr, is_write);
  581. else
  582. fsl_sata_rw_ncq_cmd(dev, start, max_blks, addr, is_write);
  583. start += max_blks;
  584. blks -= max_blks;
  585. addr += ATA_SECT_SIZE * max_blks;
  586. } else {
  587. if (fsl_sata_info[dev].flags != FLAGS_FPDMA)
  588. fsl_sata_rw_cmd_ext(dev, start, blks, addr, is_write);
  589. else
  590. fsl_sata_rw_ncq_cmd(dev, start, blks, addr, is_write);
  591. start += blks;
  592. blks = 0;
  593. addr += ATA_SECT_SIZE * blks;
  594. }
  595. } while (blks != 0);
  596. return blkcnt;
  597. }
  598. static u32 ata_low_level_rw_lba28(int dev, u32 blknr, u32 blkcnt,
  599. const void *buffer, int is_write)
  600. {
  601. u32 start, blks;
  602. u8 *addr;
  603. int max_blks;
  604. start = blknr;
  605. blks = blkcnt;
  606. addr = (u8 *)buffer;
  607. max_blks = ATA_MAX_SECTORS;
  608. do {
  609. if (blks > max_blks) {
  610. fsl_sata_rw_cmd(dev, start, max_blks, addr, is_write);
  611. start += max_blks;
  612. blks -= max_blks;
  613. addr += ATA_SECT_SIZE * max_blks;
  614. } else {
  615. fsl_sata_rw_cmd(dev, start, blks, addr, is_write);
  616. start += blks;
  617. blks = 0;
  618. addr += ATA_SECT_SIZE * blks;
  619. }
  620. } while (blks != 0);
  621. return blkcnt;
  622. }
  623. /*
  624. * SATA interface between low level driver and command layer
  625. */
  626. ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
  627. {
  628. u32 rc;
  629. fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
  630. if (sata->lba48)
  631. rc = ata_low_level_rw_lba48(dev, blknr, blkcnt, buffer, READ_CMD);
  632. else
  633. rc = ata_low_level_rw_lba28(dev, blknr, blkcnt, buffer, READ_CMD);
  634. return rc;
  635. }
  636. ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
  637. {
  638. u32 rc;
  639. fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
  640. if (sata->lba48) {
  641. rc = ata_low_level_rw_lba48(dev, blknr, blkcnt, buffer, WRITE_CMD);
  642. if (fsl_sata_get_wcache(dev) && fsl_sata_get_flush_ext(dev))
  643. fsl_sata_flush_cache_ext(dev);
  644. } else {
  645. rc = ata_low_level_rw_lba28(dev, blknr, blkcnt, buffer, WRITE_CMD);
  646. if (fsl_sata_get_wcache(dev) && fsl_sata_get_flush(dev))
  647. fsl_sata_flush_cache(dev);
  648. }
  649. return rc;
  650. }
  651. int scan_sata(int dev)
  652. {
  653. fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
  654. unsigned char serial[ATA_ID_SERNO_LEN + 1];
  655. unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
  656. unsigned char product[ATA_ID_PROD_LEN + 1];
  657. u16 *id;
  658. u64 n_sectors;
  659. /* if no detected link */
  660. if (!sata->link)
  661. return -1;
  662. id = (u16 *)malloc(ATA_ID_WORDS * 2);
  663. if (!id) {
  664. printf("id malloc failed\n\r");
  665. return -1;
  666. }
  667. /* Identify device to get information */
  668. fsl_sata_identify(dev, id);
  669. /* Serial number */
  670. ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
  671. memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));
  672. /* Firmware version */
  673. ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
  674. memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));
  675. /* Product model */
  676. ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
  677. memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));
  678. /* Totoal sectors */
  679. n_sectors = ata_id_n_sectors(id);
  680. sata_dev_desc[dev].lba = (u32)n_sectors;
  681. #ifdef CONFIG_LBA48
  682. /* Check if support LBA48 */
  683. if (ata_id_has_lba48(id)) {
  684. sata->lba48 = 1;
  685. debug("Device support LBA48\n\r");
  686. } else
  687. debug("Device supports LBA28\n\r");
  688. #endif
  689. /* Get the NCQ queue depth from device */
  690. sata->queue_depth = ata_id_queue_depth(id);
  691. /* Get the xfer mode from device */
  692. fsl_sata_xfer_mode(dev, id);
  693. /* Get the write cache status from device */
  694. fsl_sata_init_wcache(dev, id);
  695. /* Set the xfer mode to highest speed */
  696. fsl_sata_set_features(dev);
  697. #ifdef DEBUG
  698. fsl_sata_identify(dev, id);
  699. ata_dump_id(id);
  700. #endif
  701. free((void *)id);
  702. return 0;
  703. }