PIP405.h 14 KB

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  1. /*
  2. * (C) Copyright 2001
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * board/config.h - configuration options, board specific
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. /***********************************************************
  29. * High Level Configuration Options
  30. * (easy to change)
  31. ***********************************************************/
  32. #define CONFIG_405GP 1 /* This is a PPC405 CPU */
  33. #define CONFIG_4xx 1 /* ...member of PPC4xx family */
  34. #define CONFIG_PIP405 1 /* ...on a PIP405 board */
  35. /***********************************************************
  36. * Clock
  37. ***********************************************************/
  38. #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
  39. /***********************************************************
  40. * Command definitions
  41. ***********************************************************/
  42. #define CONFIG_COMMANDS \
  43. (CONFIG_CMD_DFL | \
  44. CFG_CMD_IDE | \
  45. CFG_CMD_DHCP | \
  46. CFG_CMD_PCI | \
  47. CFG_CMD_CACHE | \
  48. CFG_CMD_IRQ | \
  49. CFG_CMD_EEPROM | \
  50. CFG_CMD_I2C | \
  51. CFG_CMD_REGINFO | \
  52. CFG_CMD_FDC | \
  53. CFG_CMD_SCSI | \
  54. CFG_CMD_DATE | \
  55. CFG_CMD_ELF | \
  56. CFG_CMD_USB | \
  57. CFG_CMD_MII | \
  58. CFG_CMD_SDRAM | \
  59. CFG_CMD_DOC | \
  60. CFG_CMD_SAVES | \
  61. CFG_CMD_BSP )
  62. /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  63. #include <cmd_confdefs.h>
  64. #define CFG_HUSH_PARSER
  65. #define CFG_PROMPT_HUSH_PS2 "> "
  66. /**************************************************************
  67. * I2C Stuff:
  68. * the PIP405 is equiped with an Atmel 24C128/256 EEPROM at address
  69. * 0x53.
  70. * Caution: on the same bus is the SPD (Serial Presens Detect
  71. * EEPROM of the SDRAM
  72. * The Atmel EEPROM uses 16Bit addressing.
  73. ***************************************************************/
  74. #define CONFIG_HARD_I2C /* I2c with hardware support */
  75. #define CFG_I2C_SPEED 50000 /* I2C speed and slave address */
  76. #define CFG_I2C_SLAVE 0x7F
  77. #define CFG_I2C_EEPROM_ADDR 0x53
  78. #define CFG_I2C_EEPROM_ADDR_LEN 2
  79. #define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
  80. #define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
  81. #define CFG_ENV_SIZE 0x800 /* 2 kBytes may be used for env vars */
  82. #undef CFG_I2C_EEPROM_ADDR_OVERFLOW
  83. #define CFG_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
  84. /* 64 byte page write mode using*/
  85. /* last 6 bits of the address */
  86. #define CFG_EEPROM_PAGE_WRITE_ENABLE /* enable Page write */
  87. #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
  88. /***************************************************************
  89. * Definitions for Serial Presence Detect EEPROM address
  90. * (to get SDRAM settings)
  91. ***************************************************************/
  92. #define SPD_EEPROM_ADDRESS 0x50
  93. #define CONFIG_BOARD_PRE_INIT
  94. /**************************************************************
  95. * Environment definitions
  96. **************************************************************/
  97. #define CONFIG_BAUDRATE 9600 /* STD Baudrate */
  98. #define CONFIG_BOOTDELAY 5
  99. /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
  100. #define CONFIG_BOOT_RETRY_TIME -10 /* feature is avaiable but not enabled */
  101. #define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
  102. #define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
  103. #define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
  104. #define CONFIG_IPADDR 10.0.0.100
  105. #define CONFIG_SERVERIP 10.0.0.1
  106. #define CONFIG_PREBOOT
  107. /***************************************************************
  108. * defines if the console is stored in the environment
  109. ***************************************************************/
  110. #define CFG_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
  111. /***************************************************************
  112. * defines if an overwrite_console function exists
  113. *************************************************************/
  114. #define CFG_CONSOLE_OVERWRITE_ROUTINE
  115. #define CFG_CONSOLE_INFO_QUIET
  116. /***************************************************************
  117. * defines if the overwrite_console should be stored in the
  118. * environment
  119. **************************************************************/
  120. #undef CFG_CONSOLE_ENV_OVERWRITE
  121. /**************************************************************
  122. * loads config
  123. *************************************************************/
  124. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  125. #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  126. /***********************************************************
  127. * Miscellaneous configurable options
  128. **********************************************************/
  129. #define CFG_LONGHELP /* undef to save memory */
  130. #define CFG_PROMPT "=> " /* Monitor Command Prompt */
  131. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  132. #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  133. #else
  134. #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  135. #endif
  136. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  137. #define CFG_MAXARGS 16 /* max number of command args */
  138. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  139. #define CFG_MEMTEST_START 0x0100000 /* memtest works on */
  140. #define CFG_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
  141. #undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
  142. #define CFG_BASE_BAUD 691200
  143. /* The following table includes the supported baudrates */
  144. #define CFG_BAUDRATE_TABLE \
  145. { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
  146. 57600, 115200, 230400, 460800, 921600 }
  147. #define CFG_LOAD_ADDR 0x400000 /* default load address */
  148. #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
  149. #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
  150. /*-----------------------------------------------------------------------
  151. * PCI stuff
  152. *-----------------------------------------------------------------------
  153. */
  154. #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
  155. #define PCI_HOST_FORCE 1 /* configure as pci host */
  156. #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
  157. #define CONFIG_PCI /* include pci support */
  158. #define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
  159. #define CONFIG_PCI_PNP /* pci plug-and-play */
  160. /* resource configuration */
  161. #define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
  162. #define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
  163. #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
  164. #define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
  165. #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
  166. #define CFG_PCI_PTM2LA 0x00000000 /* disabled */
  167. #define CFG_PCI_PTM2MS 0x00000000 /* disabled */
  168. #define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
  169. /*-----------------------------------------------------------------------
  170. * Start addresses for the final memory configuration
  171. * (Set up by the startup code)
  172. * Please note that CFG_SDRAM_BASE _must_ start at 0
  173. */
  174. #define CFG_SDRAM_BASE 0x00000000
  175. #define CFG_FLASH_BASE 0xFFF80000
  176. #define CFG_MONITOR_BASE CFG_FLASH_BASE
  177. #define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
  178. #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
  179. /*
  180. * For booting Linux, the board info and command line data
  181. * have to be in the first 8 MB of memory, since this is
  182. * the maximum mapped by the Linux kernel during initialization.
  183. */
  184. #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  185. /*-----------------------------------------------------------------------
  186. * FLASH organization
  187. */
  188. #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
  189. #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
  190. #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  191. #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  192. /*-----------------------------------------------------------------------
  193. * Cache Configuration
  194. */
  195. #define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
  196. #define CFG_CACHELINE_SIZE 32 /* ... */
  197. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  198. #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  199. #endif
  200. /*
  201. * Init Memory Controller:
  202. */
  203. #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
  204. #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
  205. /* Configuration Port location */
  206. #define CONFIG_PORT_ADDR 0xF4000000
  207. #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
  208. /*-----------------------------------------------------------------------
  209. * Definitions for initial stack pointer and data area (in On Chip SRAM)
  210. */
  211. #define CFG_TEMP_STACK_OCM 1
  212. #define CFG_OCM_DATA_ADDR 0xF0000000
  213. #define CFG_OCM_DATA_SIZE 0x1000
  214. #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */
  215. #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */
  216. #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
  217. #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  218. #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  219. /*
  220. * Internal Definitions
  221. *
  222. * Boot Flags
  223. */
  224. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  225. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  226. /***********************************************************************
  227. * External peripheral base address
  228. ***********************************************************************/
  229. #define CFG_ISA_IO_BASE_ADDRESS 0xE8000000
  230. /***********************************************************************
  231. * Last Stage Init
  232. ***********************************************************************/
  233. #define CONFIG_LAST_STAGE_INIT
  234. /************************************************************
  235. * Ethernet Stuff
  236. ***********************************************************/
  237. #define CONFIG_MII 1 /* MII PHY management */
  238. #define CONFIG_PHY_ADDR 1 /* PHY address */
  239. #define CONFIG_CS8952_PHY 1 /* its a CS8952 PHY */
  240. /************************************************************
  241. * RTC
  242. ***********************************************************/
  243. #define CONFIG_RTC_MC146818
  244. #undef CONFIG_WATCHDOG /* watchdog disabled */
  245. /************************************************************
  246. * IDE/ATA stuff
  247. ************************************************************/
  248. #define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */
  249. #define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
  250. #define CFG_ATA_BASE_ADDR CFG_ISA_IO_BASE_ADDRESS /* base address */
  251. #define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
  252. #define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
  253. #define CFG_ATA_DATA_OFFSET 0 /* data reg offset */
  254. #define CFG_ATA_REG_OFFSET 0 /* reg offset */
  255. #define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
  256. #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
  257. #undef CONFIG_IDE_LED /* no led for ide supported */
  258. #define CONFIG_IDE_RESET /* reset for ide supported... */
  259. #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
  260. /************************************************************
  261. * ATAPI support (experimental)
  262. ************************************************************/
  263. #define CONFIG_ATAPI /* enable ATAPI Support */
  264. /************************************************************
  265. * SCSI support (experimental) only SYM53C8xx supported
  266. ************************************************************/
  267. #define CONFIG_SCSI_SYM53C8XX
  268. #define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */
  269. #define CFG_SCSI_MAX_SCSI_ID 7 /* maximum SCSI ID (0..6) */
  270. #define CFG_SCSI_MAX_DEVICE CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */
  271. #define CFG_SCSI_SPIN_UP_TIME 2
  272. /************************************************************
  273. * Disk-On-Chip configuration
  274. ************************************************************/
  275. #define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
  276. #define CFG_DOC_SHORT_TIMEOUT
  277. #define CFG_DOC_SUPPORT_2000
  278. #define CFG_DOC_SUPPORT_MILLENNIUM
  279. /************************************************************
  280. * DISK Partition support
  281. ************************************************************/
  282. #define CONFIG_DOS_PARTITION
  283. #define CONFIG_MAC_PARTITION
  284. #define CONFIG_ISO_PARTITION /* Experimental */
  285. /************************************************************
  286. * Keyboard support
  287. ************************************************************/
  288. #define CONFIG_ISA_KEYBOARD
  289. /************************************************************
  290. * Video support
  291. ************************************************************/
  292. #define CONFIG_VIDEO /*To enable video controller support */
  293. #define CONFIG_VIDEO_CT69000
  294. #define CONFIG_CFB_CONSOLE
  295. #define CONFIG_VIDEO_LOGO
  296. #define CONFIG_CONSOLE_EXTRA_INFO
  297. #define CONFIG_VGA_AS_SINGLE_DEVICE
  298. #define CONFIG_VIDEO_SW_CURSOR
  299. #define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */
  300. /************************************************************
  301. * USB support
  302. ************************************************************/
  303. #define CONFIG_USB_UHCI
  304. #define CONFIG_USB_KEYBOARD
  305. #define CONFIG_USB_STORAGE
  306. /* Enable needed helper functions */
  307. #define CFG_DEVICE_DEREGISTER /* needs device_deregister */
  308. /************************************************************
  309. * Debug support
  310. ************************************************************/
  311. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  312. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  313. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  314. #endif
  315. /************************************************************
  316. * Ident
  317. ************************************************************/
  318. #define VERSION_TAG "released"
  319. #define CONFIG_IDENT_STRING "\n(c) 2002 by MPL AG Switzerland, MEV-10066-001 " VERSION_TAG
  320. #endif /* __CONFIG_H */