memsetup.S 4.1 KB

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  1. /*
  2. * Copyright (C) 2001, 2002 ETC s.r.o.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * as published by the Free Software Foundation; either version 2
  7. * of the License, or (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
  17. * 02111-1307, USA.
  18. *
  19. * Written by Marcel Telka <marcel@telka.sk>, 2001, 2002.
  20. * Changes for U-Boot Peter Figuli <peposh@etc.sk>, 2003.
  21. *
  22. * This file is taken from OpenWinCE project hosted by SourceForge.net
  23. *
  24. * Documentation:
  25. * [1] Intel Corporation, "Intel PXA250 and PXA210 Application Processors
  26. * Developer's Manual", February 2002, Order Number: 278522-001
  27. * [2] Samsung Electronics, "8Mx16 SDRAM 54CSP K4S281633D-RL/N/P",
  28. * Revision 1.0, February 2002
  29. * [3] Samsung Electronics, "16Mx16 SDRAM 54CSP K4S561633C-RL(N)",
  30. * Revision 1.0, February 2002
  31. *
  32. */
  33. #include <config.h>
  34. #include <version.h>
  35. #include <asm/arch/pxa-regs.h>
  36. .globl memsetup
  37. memsetup:
  38. mov r10, lr
  39. /* setup memory - see 6.12 in [1]
  40. * Step 1 - wait 200 us
  41. */
  42. mov r0,#0x2700 /* wait 200 us @ 99.5 MHz */
  43. 1: subs r0, r0, #1
  44. bne 1b
  45. /* TODO: complete step 1 for Synchronous Static memory*/
  46. ldr r0, =0x48000000 /* MC_BASE */
  47. /* step 1.a - setup MSCx
  48. */
  49. ldr r1, =0x000012B3 /* MSC0_RRR0(1) | MSC0_RDN0(2) | MSC0_RDF0(11) | MSC0_RT0(3) */
  50. str r1, [r0, #0x8] /* MSC0_OFFSET */
  51. /* step 1.c - clear MDREFR:K1FREE, set MDREFR:DRI
  52. * see AUTO REFRESH chapter in section D. in [2] and in [3]
  53. * DRI = (64ms / 4096) * 99.53MHz / 32 = 48 for K4S281633
  54. * DRI = (64ms / 8192) * 99.52MHz / 32 = 24 for K4S561633
  55. * TODO: complete for Synchronous Static memory
  56. */
  57. ldr r1, [r0, #4] /* MDREFR_OFFSET */
  58. ldr r2, =0x01000FFF /* MDREFR_K1FREE | MDREFR_DRI_MASK */
  59. bic r1, r1, r2
  60. #if defined( WEP_SDRAM_K4S281633 )
  61. orr r1, r1, #48 /* MDREFR_DRI(48) */
  62. #elif defined( WEP_SDRAM_K4S561633 )
  63. orr r1, r1, #24 /* MDREFR_DRI(24) */
  64. #else
  65. #error SDRAM chip is not defined
  66. #endif
  67. str r1, [r0, #4] /* MDREFR_OFFSET */
  68. /* Step 2 - only for Synchronous Static memory (TODO)
  69. *
  70. * Step 3 - same as step 4
  71. *
  72. * Step 4
  73. *
  74. * Step 4.a - set MDREFR:K1RUN, clear MDREFR:K1DB2
  75. */
  76. orr r1, r1, #0x00010000 /* MDREFR_K1RUN */
  77. bic r1, r1, #0x00020000 /* MDREFR_K1DB2 */
  78. str r1, [r0, #4] /* MDREFR_OFFSET */
  79. /* Step 4.b - clear MDREFR:SLFRSH */
  80. bic r1, r1, #0x00400000 /* MDREFR_SLFRSH */
  81. str r1, [r0, #4] /* MDREFR_OFFSET */
  82. /* Step 4.c - set MDREFR:E1PIN */
  83. orr r1, r1, #0x00008000 /* MDREFR_E1PIN */
  84. str r1, [r0, #4] /* MDREFR_OFFSET */
  85. /* Step 4.d - automatically done
  86. *
  87. * Steps 4.e and 4.f - configure SDRAM
  88. */
  89. #if defined( WEP_SDRAM_K4S281633 )
  90. ldr r1, =0x00000AA8 /* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(1) | MDCNFG_DNB0 */
  91. #elif defined( WEP_SDRAM_K4S561633 )
  92. ldr r1, =0x00000AC8 /* MDCNFG_DTC0(2) | MDCNFG_DLATCH0 | MDCNFG_DCAC0(1) | MDCNFG_DRAC0(2) | MDCNFG_DNB0 */
  93. #else
  94. #error SDRAM chip is not defined
  95. #endif
  96. str r1, [r0, #0] /* MDCNFG_OFFSET */
  97. /* Step 5 - wait at least 200 us for SDRAM
  98. * see section B. in [2]
  99. */
  100. mov r2,#0x2700 /* wait 200 us @ 99.5 MHz */
  101. 1: subs r2, r2, #1
  102. bne 1b
  103. /* Step 6 - after reset dcache is disabled, so automatically done
  104. *
  105. * Step 7 - eight refresh cycles
  106. */
  107. mov r2, #0xA0000000
  108. ldr r3, [r2]
  109. ldr r3, [r2]
  110. ldr r3, [r2]
  111. ldr r3, [r2]
  112. ldr r3, [r2]
  113. ldr r3, [r2]
  114. ldr r3, [r2]
  115. ldr r3, [r2]
  116. /* Step 8 - we don't need dcache now
  117. *
  118. * Step 9 - enable SDRAM partition 0
  119. */
  120. orr r1, r1, #1 /* MDCNFG_DE0 */
  121. str r1, [r0, #0] /* MDCNFG_OFFSET */
  122. /* Step 10 - write MDMRS */
  123. mov r1, #0
  124. str r1, [r0, #0x40] /* MDMRS_OFFSET */
  125. /* Step 11 - optional (TODO) */
  126. mov pc,r10