sbc8641d.c 5.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
  4. * Copyright 2007 Embedded Specialties, Inc.
  5. * Joe Hamman joe.hamman@embeddedspecialties.com
  6. *
  7. * Copyright 2004 Freescale Semiconductor.
  8. * Jeff Brown
  9. * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
  10. *
  11. * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  12. */
  13. #include <common.h>
  14. #include <command.h>
  15. #include <init.h>
  16. #include <pci.h>
  17. #include <asm/processor.h>
  18. #include <asm/immap_86xx.h>
  19. #include <asm/fsl_pci.h>
  20. #include <fsl_ddr_sdram.h>
  21. #include <asm/fsl_serdes.h>
  22. #include <linux/libfdt.h>
  23. #include <fdt_support.h>
  24. DECLARE_GLOBAL_DATA_PTR;
  25. long int fixed_sdram (void);
  26. int board_early_init_f (void)
  27. {
  28. return 0;
  29. }
  30. int checkboard (void)
  31. {
  32. puts ("Board: Wind River SBC8641D\n");
  33. return 0;
  34. }
  35. int dram_init(void)
  36. {
  37. long dram_size = 0;
  38. #if defined(CONFIG_SPD_EEPROM)
  39. dram_size = fsl_ddr_sdram();
  40. #else
  41. dram_size = fixed_sdram ();
  42. #endif
  43. debug(" DDR: ");
  44. gd->ram_size = dram_size;
  45. return 0;
  46. }
  47. #if defined(CONFIG_SYS_DRAM_TEST)
  48. int testdram(void)
  49. {
  50. uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
  51. uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
  52. uint *p;
  53. puts ("SDRAM test phase 1:\n");
  54. for (p = pstart; p < pend; p++)
  55. *p = 0xaaaaaaaa;
  56. for (p = pstart; p < pend; p++) {
  57. if (*p != 0xaaaaaaaa) {
  58. printf ("SDRAM test fails at: %08x\n", (uint) p);
  59. return 1;
  60. }
  61. }
  62. puts ("SDRAM test phase 2:\n");
  63. for (p = pstart; p < pend; p++)
  64. *p = 0x55555555;
  65. for (p = pstart; p < pend; p++) {
  66. if (*p != 0x55555555) {
  67. printf ("SDRAM test fails at: %08x\n", (uint) p);
  68. return 1;
  69. }
  70. }
  71. puts ("SDRAM test passed.\n");
  72. return 0;
  73. }
  74. #endif
  75. #if !defined(CONFIG_SPD_EEPROM)
  76. /*
  77. * Fixed sdram init -- doesn't use serial presence detect.
  78. */
  79. long int fixed_sdram (void)
  80. {
  81. #if !defined(CONFIG_SYS_RAMBOOT)
  82. volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  83. volatile struct ccsr_ddr *ddr = &immap->im_ddr1;
  84. ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
  85. ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
  86. ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS;
  87. ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS;
  88. ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
  89. ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
  90. ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG;
  91. ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG;
  92. ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  93. ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  94. ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  95. ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  96. ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A;
  97. ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
  98. ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
  99. ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
  100. ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTL;
  101. ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  102. ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
  103. ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
  104. asm ("sync;isync");
  105. udelay (500);
  106. ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B;
  107. asm ("sync; isync");
  108. udelay (500);
  109. ddr = &immap->im_ddr2;
  110. ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS;
  111. ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS;
  112. ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS;
  113. ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS;
  114. ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG;
  115. ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG;
  116. ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG;
  117. ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG;
  118. ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH;
  119. ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
  120. ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
  121. ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
  122. ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A;
  123. ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
  124. ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
  125. ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
  126. ddr->sdram_md_cntl = CONFIG_SYS_DDR2_MODE_CTL;
  127. ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
  128. ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
  129. ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;
  130. asm ("sync;isync");
  131. udelay (500);
  132. ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B;
  133. asm ("sync; isync");
  134. udelay (500);
  135. #endif
  136. return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  137. }
  138. #endif /* !defined(CONFIG_SPD_EEPROM) */
  139. #if defined(CONFIG_PCI)
  140. /*
  141. * Initialize PCI Devices, report devices found.
  142. */
  143. void pci_init_board(void)
  144. {
  145. fsl_pcie_init_board(0);
  146. }
  147. #endif /* CONFIG_PCI */
  148. #if defined(CONFIG_OF_BOARD_SETUP)
  149. int ft_board_setup(void *blob, bd_t *bd)
  150. {
  151. ft_cpu_setup(blob, bd);
  152. FT_FSL_PCI_SETUP;
  153. return 0;
  154. }
  155. #endif
  156. void sbc8641d_reset_board (void)
  157. {
  158. puts ("Resetting board....\n");
  159. }
  160. /*
  161. * get_board_sys_clk
  162. * Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ
  163. */
  164. unsigned long get_board_sys_clk (ulong dummy)
  165. {
  166. int i;
  167. ulong val = 0;
  168. i = 5;
  169. i &= 0x07;
  170. switch (i) {
  171. case 0:
  172. val = 33000000;
  173. break;
  174. case 1:
  175. val = 40000000;
  176. break;
  177. case 2:
  178. val = 50000000;
  179. break;
  180. case 3:
  181. val = 66000000;
  182. break;
  183. case 4:
  184. val = 83000000;
  185. break;
  186. case 5:
  187. val = 100000000;
  188. break;
  189. case 6:
  190. val = 134000000;
  191. break;
  192. case 7:
  193. val = 166000000;
  194. break;
  195. }
  196. return val;
  197. }
  198. void board_reset(void)
  199. {
  200. #ifdef CONFIG_SYS_RESET_ADDRESS
  201. ulong addr = CONFIG_SYS_RESET_ADDRESS;
  202. /* flush and disable I/D cache */
  203. __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
  204. __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
  205. __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
  206. __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
  207. __asm__ __volatile__ ("sync");
  208. __asm__ __volatile__ ("mtspr 1008, 4");
  209. __asm__ __volatile__ ("isync");
  210. __asm__ __volatile__ ("sync");
  211. __asm__ __volatile__ ("mtspr 1008, 5");
  212. __asm__ __volatile__ ("isync");
  213. __asm__ __volatile__ ("sync");
  214. /*
  215. * SRR0 has system reset vector, SRR1 has default MSR value
  216. * rfi restores MSR from SRR1 and sets the PC to the SRR0 value
  217. */
  218. __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
  219. __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
  220. __asm__ __volatile__ ("mtspr 27, 4");
  221. __asm__ __volatile__ ("rfi");
  222. #endif
  223. }