musb_dsps.c 20 KB

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  1. /*
  2. * Texas Instruments DSPS platforms "glue layer"
  3. *
  4. * Copyright (C) 2012, by Texas Instruments
  5. *
  6. * Based on the am35x "glue layer" code.
  7. *
  8. * This file is part of the Inventra Controller Driver for Linux.
  9. *
  10. * The Inventra Controller Driver for Linux is free software; you
  11. * can redistribute it and/or modify it under the terms of the GNU
  12. * General Public License version 2 as published by the Free Software
  13. * Foundation.
  14. *
  15. * The Inventra Controller Driver for Linux is distributed in
  16. * the hope that it will be useful, but WITHOUT ANY WARRANTY;
  17. * without even the implied warranty of MERCHANTABILITY or
  18. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
  19. * License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with The Inventra Controller Driver for Linux ; if not,
  23. * write to the Free Software Foundation, Inc., 59 Temple Place,
  24. * Suite 330, Boston, MA 02111-1307 USA
  25. *
  26. * musb_dsps.c will be a common file for all the TI DSPS platforms
  27. * such as dm64x, dm36x, dm35x, da8x, am35x and ti81x.
  28. * For now only ti81x is using this and in future davinci.c, am35x.c
  29. * da8xx.c would be merged to this file after testing.
  30. */
  31. #ifndef __UBOOT__
  32. #include <linux/init.h>
  33. #include <linux/io.h>
  34. #include <linux/err.h>
  35. #include <linux/platform_device.h>
  36. #include <linux/dma-mapping.h>
  37. #include <linux/pm_runtime.h>
  38. #include <linux/module.h>
  39. #include <linux/of.h>
  40. #include <linux/of_device.h>
  41. #include <linux/of_address.h>
  42. #include <plat/usb.h>
  43. #else
  44. #include <common.h>
  45. #include <asm/omap_musb.h>
  46. #include "linux-compat.h"
  47. #endif
  48. #include "musb_core.h"
  49. /**
  50. * avoid using musb_readx()/musb_writex() as glue layer should not be
  51. * dependent on musb core layer symbols.
  52. */
  53. static inline u8 dsps_readb(const void __iomem *addr, unsigned offset)
  54. { return __raw_readb(addr + offset); }
  55. static inline u32 dsps_readl(const void __iomem *addr, unsigned offset)
  56. { return __raw_readl(addr + offset); }
  57. static inline void dsps_writeb(void __iomem *addr, unsigned offset, u8 data)
  58. { __raw_writeb(data, addr + offset); }
  59. static inline void dsps_writel(void __iomem *addr, unsigned offset, u32 data)
  60. { __raw_writel(data, addr + offset); }
  61. /**
  62. * DSPS musb wrapper register offset.
  63. * FIXME: This should be expanded to have all the wrapper registers from TI DSPS
  64. * musb ips.
  65. */
  66. struct dsps_musb_wrapper {
  67. u16 revision;
  68. u16 control;
  69. u16 status;
  70. u16 eoi;
  71. u16 epintr_set;
  72. u16 epintr_clear;
  73. u16 epintr_status;
  74. u16 coreintr_set;
  75. u16 coreintr_clear;
  76. u16 coreintr_status;
  77. u16 phy_utmi;
  78. u16 mode;
  79. /* bit positions for control */
  80. unsigned reset:5;
  81. /* bit positions for interrupt */
  82. unsigned usb_shift:5;
  83. u32 usb_mask;
  84. u32 usb_bitmap;
  85. unsigned drvvbus:5;
  86. unsigned txep_shift:5;
  87. u32 txep_mask;
  88. u32 txep_bitmap;
  89. unsigned rxep_shift:5;
  90. u32 rxep_mask;
  91. u32 rxep_bitmap;
  92. /* bit positions for phy_utmi */
  93. unsigned otg_disable:5;
  94. /* bit positions for mode */
  95. unsigned iddig:5;
  96. /* miscellaneous stuff */
  97. u32 musb_core_offset;
  98. u8 poll_seconds;
  99. };
  100. static const struct dsps_musb_wrapper ti81xx_driver_data __devinitconst = {
  101. .revision = 0x00,
  102. .control = 0x14,
  103. .status = 0x18,
  104. .eoi = 0x24,
  105. .epintr_set = 0x38,
  106. .epintr_clear = 0x40,
  107. .epintr_status = 0x30,
  108. .coreintr_set = 0x3c,
  109. .coreintr_clear = 0x44,
  110. .coreintr_status = 0x34,
  111. .phy_utmi = 0xe0,
  112. .mode = 0xe8,
  113. .reset = 0,
  114. .otg_disable = 21,
  115. .iddig = 8,
  116. .usb_shift = 0,
  117. .usb_mask = 0x1ff,
  118. .usb_bitmap = (0x1ff << 0),
  119. .drvvbus = 8,
  120. .txep_shift = 0,
  121. .txep_mask = 0xffff,
  122. .txep_bitmap = (0xffff << 0),
  123. .rxep_shift = 16,
  124. .rxep_mask = 0xfffe,
  125. .rxep_bitmap = (0xfffe << 16),
  126. .musb_core_offset = 0x400,
  127. .poll_seconds = 2,
  128. };
  129. /**
  130. * DSPS glue structure.
  131. */
  132. struct dsps_glue {
  133. struct device *dev;
  134. struct platform_device *musb; /* child musb pdev */
  135. const struct dsps_musb_wrapper *wrp; /* wrapper register offsets */
  136. struct timer_list timer; /* otg_workaround timer */
  137. };
  138. /**
  139. * dsps_musb_enable - enable interrupts
  140. */
  141. static void dsps_musb_enable(struct musb *musb)
  142. {
  143. #ifndef __UBOOT__
  144. struct device *dev = musb->controller;
  145. struct platform_device *pdev = to_platform_device(dev->parent);
  146. struct dsps_glue *glue = platform_get_drvdata(pdev);
  147. const struct dsps_musb_wrapper *wrp = glue->wrp;
  148. #else
  149. const struct dsps_musb_wrapper *wrp = &ti81xx_driver_data;
  150. #endif
  151. void __iomem *reg_base = musb->ctrl_base;
  152. u32 epmask, coremask;
  153. /* Workaround: setup IRQs through both register sets. */
  154. epmask = ((musb->epmask & wrp->txep_mask) << wrp->txep_shift) |
  155. ((musb->epmask & wrp->rxep_mask) << wrp->rxep_shift);
  156. coremask = (wrp->usb_bitmap & ~MUSB_INTR_SOF);
  157. dsps_writel(reg_base, wrp->epintr_set, epmask);
  158. dsps_writel(reg_base, wrp->coreintr_set, coremask);
  159. /* Force the DRVVBUS IRQ so we can start polling for ID change. */
  160. #ifndef __UBOOT__
  161. if (is_otg_enabled(musb))
  162. dsps_writel(reg_base, wrp->coreintr_set,
  163. (1 << wrp->drvvbus) << wrp->usb_shift);
  164. #endif
  165. }
  166. /**
  167. * dsps_musb_disable - disable HDRC and flush interrupts
  168. */
  169. static void dsps_musb_disable(struct musb *musb)
  170. {
  171. #ifndef __UBOOT__
  172. struct device *dev = musb->controller;
  173. struct platform_device *pdev = to_platform_device(dev->parent);
  174. struct dsps_glue *glue = platform_get_drvdata(pdev);
  175. const struct dsps_musb_wrapper *wrp = glue->wrp;
  176. void __iomem *reg_base = musb->ctrl_base;
  177. dsps_writel(reg_base, wrp->coreintr_clear, wrp->usb_bitmap);
  178. dsps_writel(reg_base, wrp->epintr_clear,
  179. wrp->txep_bitmap | wrp->rxep_bitmap);
  180. dsps_writeb(musb->mregs, MUSB_DEVCTL, 0);
  181. dsps_writel(reg_base, wrp->eoi, 0);
  182. #endif
  183. }
  184. #ifndef __UBOOT__
  185. static void otg_timer(unsigned long _musb)
  186. {
  187. struct musb *musb = (void *)_musb;
  188. void __iomem *mregs = musb->mregs;
  189. struct device *dev = musb->controller;
  190. struct platform_device *pdev = to_platform_device(dev->parent);
  191. struct dsps_glue *glue = platform_get_drvdata(pdev);
  192. const struct dsps_musb_wrapper *wrp = glue->wrp;
  193. u8 devctl;
  194. unsigned long flags;
  195. /*
  196. * We poll because DSPS IP's won't expose several OTG-critical
  197. * status change events (from the transceiver) otherwise.
  198. */
  199. devctl = dsps_readb(mregs, MUSB_DEVCTL);
  200. dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
  201. otg_state_string(musb->xceiv->state));
  202. spin_lock_irqsave(&musb->lock, flags);
  203. switch (musb->xceiv->state) {
  204. case OTG_STATE_A_WAIT_BCON:
  205. devctl &= ~MUSB_DEVCTL_SESSION;
  206. dsps_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  207. devctl = dsps_readb(musb->mregs, MUSB_DEVCTL);
  208. if (devctl & MUSB_DEVCTL_BDEVICE) {
  209. musb->xceiv->state = OTG_STATE_B_IDLE;
  210. MUSB_DEV_MODE(musb);
  211. } else {
  212. musb->xceiv->state = OTG_STATE_A_IDLE;
  213. MUSB_HST_MODE(musb);
  214. }
  215. break;
  216. case OTG_STATE_A_WAIT_VFALL:
  217. musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
  218. dsps_writel(musb->ctrl_base, wrp->coreintr_set,
  219. MUSB_INTR_VBUSERROR << wrp->usb_shift);
  220. break;
  221. case OTG_STATE_B_IDLE:
  222. if (!is_peripheral_enabled(musb))
  223. break;
  224. devctl = dsps_readb(mregs, MUSB_DEVCTL);
  225. if (devctl & MUSB_DEVCTL_BDEVICE)
  226. mod_timer(&glue->timer,
  227. jiffies + wrp->poll_seconds * HZ);
  228. else
  229. musb->xceiv->state = OTG_STATE_A_IDLE;
  230. break;
  231. default:
  232. break;
  233. }
  234. spin_unlock_irqrestore(&musb->lock, flags);
  235. }
  236. static void dsps_musb_try_idle(struct musb *musb, unsigned long timeout)
  237. {
  238. struct device *dev = musb->controller;
  239. struct platform_device *pdev = to_platform_device(dev->parent);
  240. struct dsps_glue *glue = platform_get_drvdata(pdev);
  241. static unsigned long last_timer;
  242. if (!is_otg_enabled(musb))
  243. return;
  244. if (timeout == 0)
  245. timeout = jiffies + msecs_to_jiffies(3);
  246. /* Never idle if active, or when VBUS timeout is not set as host */
  247. if (musb->is_active || (musb->a_wait_bcon == 0 &&
  248. musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
  249. dev_dbg(musb->controller, "%s active, deleting timer\n",
  250. otg_state_string(musb->xceiv->state));
  251. del_timer(&glue->timer);
  252. last_timer = jiffies;
  253. return;
  254. }
  255. if (time_after(last_timer, timeout) && timer_pending(&glue->timer)) {
  256. dev_dbg(musb->controller,
  257. "Longer idle timer already pending, ignoring...\n");
  258. return;
  259. }
  260. last_timer = timeout;
  261. dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
  262. otg_state_string(musb->xceiv->state),
  263. jiffies_to_msecs(timeout - jiffies));
  264. mod_timer(&glue->timer, timeout);
  265. }
  266. #endif
  267. static irqreturn_t dsps_interrupt(int irq, void *hci)
  268. {
  269. struct musb *musb = hci;
  270. void __iomem *reg_base = musb->ctrl_base;
  271. #ifndef __UBOOT__
  272. struct device *dev = musb->controller;
  273. struct platform_device *pdev = to_platform_device(dev->parent);
  274. struct dsps_glue *glue = platform_get_drvdata(pdev);
  275. const struct dsps_musb_wrapper *wrp = glue->wrp;
  276. #else
  277. const struct dsps_musb_wrapper *wrp = &ti81xx_driver_data;
  278. #endif
  279. unsigned long flags;
  280. irqreturn_t ret = IRQ_NONE;
  281. u32 epintr, usbintr;
  282. spin_lock_irqsave(&musb->lock, flags);
  283. /* Get endpoint interrupts */
  284. epintr = dsps_readl(reg_base, wrp->epintr_status);
  285. musb->int_rx = (epintr & wrp->rxep_bitmap) >> wrp->rxep_shift;
  286. musb->int_tx = (epintr & wrp->txep_bitmap) >> wrp->txep_shift;
  287. if (epintr)
  288. dsps_writel(reg_base, wrp->epintr_status, epintr);
  289. /* Get usb core interrupts */
  290. usbintr = dsps_readl(reg_base, wrp->coreintr_status);
  291. if (!usbintr && !epintr)
  292. goto eoi;
  293. musb->int_usb = (usbintr & wrp->usb_bitmap) >> wrp->usb_shift;
  294. if (usbintr)
  295. dsps_writel(reg_base, wrp->coreintr_status, usbintr);
  296. dev_dbg(musb->controller, "usbintr (%x) epintr(%x)\n",
  297. usbintr, epintr);
  298. #ifndef __UBOOT__
  299. /*
  300. * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
  301. * DSPS IP's missing ID change IRQ. We need an ID change IRQ to
  302. * switch appropriately between halves of the OTG state machine.
  303. * Managing DEVCTL.SESSION per Mentor docs requires that we know its
  304. * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
  305. * Also, DRVVBUS pulses for SRP (but not at 5V) ...
  306. */
  307. if ((usbintr & MUSB_INTR_BABBLE) && is_host_enabled(musb))
  308. pr_info("CAUTION: musb: Babble Interrupt Occured\n");
  309. if (usbintr & ((1 << wrp->drvvbus) << wrp->usb_shift)) {
  310. int drvvbus = dsps_readl(reg_base, wrp->status);
  311. void __iomem *mregs = musb->mregs;
  312. u8 devctl = dsps_readb(mregs, MUSB_DEVCTL);
  313. int err;
  314. err = is_host_enabled(musb) && (musb->int_usb &
  315. MUSB_INTR_VBUSERROR);
  316. if (err) {
  317. /*
  318. * The Mentor core doesn't debounce VBUS as needed
  319. * to cope with device connect current spikes. This
  320. * means it's not uncommon for bus-powered devices
  321. * to get VBUS errors during enumeration.
  322. *
  323. * This is a workaround, but newer RTL from Mentor
  324. * seems to allow a better one: "re"-starting sessions
  325. * without waiting for VBUS to stop registering in
  326. * devctl.
  327. */
  328. musb->int_usb &= ~MUSB_INTR_VBUSERROR;
  329. musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
  330. mod_timer(&glue->timer,
  331. jiffies + wrp->poll_seconds * HZ);
  332. WARNING("VBUS error workaround (delay coming)\n");
  333. } else if (is_host_enabled(musb) && drvvbus) {
  334. musb->is_active = 1;
  335. MUSB_HST_MODE(musb);
  336. musb->xceiv->otg->default_a = 1;
  337. musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
  338. del_timer(&glue->timer);
  339. } else {
  340. musb->is_active = 0;
  341. MUSB_DEV_MODE(musb);
  342. musb->xceiv->otg->default_a = 0;
  343. musb->xceiv->state = OTG_STATE_B_IDLE;
  344. }
  345. /* NOTE: this must complete power-on within 100 ms. */
  346. dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
  347. drvvbus ? "on" : "off",
  348. otg_state_string(musb->xceiv->state),
  349. err ? " ERROR" : "",
  350. devctl);
  351. ret = IRQ_HANDLED;
  352. }
  353. #endif
  354. if (musb->int_tx || musb->int_rx || musb->int_usb)
  355. ret |= musb_interrupt(musb);
  356. eoi:
  357. /* EOI needs to be written for the IRQ to be re-asserted. */
  358. if (ret == IRQ_HANDLED || epintr || usbintr)
  359. dsps_writel(reg_base, wrp->eoi, 1);
  360. #ifndef __UBOOT__
  361. /* Poll for ID change */
  362. if (is_otg_enabled(musb) && musb->xceiv->state == OTG_STATE_B_IDLE)
  363. mod_timer(&glue->timer, jiffies + wrp->poll_seconds * HZ);
  364. #endif
  365. spin_unlock_irqrestore(&musb->lock, flags);
  366. return ret;
  367. }
  368. static int dsps_musb_init(struct musb *musb)
  369. {
  370. #ifndef __UBOOT__
  371. struct device *dev = musb->controller;
  372. struct musb_hdrc_platform_data *plat = dev->platform_data;
  373. struct platform_device *pdev = to_platform_device(dev->parent);
  374. struct dsps_glue *glue = platform_get_drvdata(pdev);
  375. const struct dsps_musb_wrapper *wrp = glue->wrp;
  376. struct omap_musb_board_data *data = plat->board_data;
  377. #else
  378. struct omap_musb_board_data *data =
  379. (struct omap_musb_board_data *)musb->controller;
  380. const struct dsps_musb_wrapper *wrp = &ti81xx_driver_data;
  381. #endif
  382. void __iomem *reg_base = musb->ctrl_base;
  383. u32 rev, val;
  384. int status;
  385. /* mentor core register starts at offset of 0x400 from musb base */
  386. musb->mregs += wrp->musb_core_offset;
  387. #ifndef __UBOOT__
  388. /* NOP driver needs change if supporting dual instance */
  389. usb_nop_xceiv_register();
  390. musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
  391. if (IS_ERR_OR_NULL(musb->xceiv))
  392. return -ENODEV;
  393. #endif
  394. /* Returns zero if e.g. not clocked */
  395. rev = dsps_readl(reg_base, wrp->revision);
  396. if (!rev) {
  397. status = -ENODEV;
  398. goto err0;
  399. }
  400. #ifndef __UBOOT__
  401. if (is_host_enabled(musb))
  402. setup_timer(&glue->timer, otg_timer, (unsigned long) musb);
  403. #endif
  404. /* Reset the musb */
  405. dsps_writel(reg_base, wrp->control, (1 << wrp->reset));
  406. /* Start the on-chip PHY and its PLL. */
  407. if (data->set_phy_power)
  408. data->set_phy_power(1);
  409. musb->isr = dsps_interrupt;
  410. /* reset the otgdisable bit, needed for host mode to work */
  411. val = dsps_readl(reg_base, wrp->phy_utmi);
  412. val &= ~(1 << wrp->otg_disable);
  413. dsps_writel(musb->ctrl_base, wrp->phy_utmi, val);
  414. /* clear level interrupt */
  415. dsps_writel(reg_base, wrp->eoi, 0);
  416. return 0;
  417. err0:
  418. #ifndef __UBOOT__
  419. usb_put_phy(musb->xceiv);
  420. usb_nop_xceiv_unregister();
  421. #endif
  422. return status;
  423. }
  424. static int dsps_musb_exit(struct musb *musb)
  425. {
  426. #ifndef __UBOOT__
  427. struct device *dev = musb->controller;
  428. struct musb_hdrc_platform_data *plat = dev->platform_data;
  429. struct omap_musb_board_data *data = plat->board_data;
  430. struct platform_device *pdev = to_platform_device(dev->parent);
  431. struct dsps_glue *glue = platform_get_drvdata(pdev);
  432. #else
  433. struct omap_musb_board_data *data =
  434. (struct omap_musb_board_data *)musb->controller;
  435. #endif
  436. #ifndef __UBOOT__
  437. if (is_host_enabled(musb))
  438. del_timer_sync(&glue->timer);
  439. #endif
  440. /* Shutdown the on-chip PHY and its PLL. */
  441. if (data->set_phy_power)
  442. data->set_phy_power(0);
  443. #ifndef __UBOOT__
  444. /* NOP driver needs change if supporting dual instance */
  445. usb_put_phy(musb->xceiv);
  446. usb_nop_xceiv_unregister();
  447. #endif
  448. return 0;
  449. }
  450. #ifndef __UBOOT__
  451. static struct musb_platform_ops dsps_ops = {
  452. #else
  453. struct musb_platform_ops musb_dsps_ops = {
  454. #endif
  455. .init = dsps_musb_init,
  456. .exit = dsps_musb_exit,
  457. .enable = dsps_musb_enable,
  458. .disable = dsps_musb_disable,
  459. #ifndef __UBOOT__
  460. .try_idle = dsps_musb_try_idle,
  461. #endif
  462. };
  463. #ifndef __UBOOT__
  464. static u64 musb_dmamask = DMA_BIT_MASK(32);
  465. #endif
  466. #ifndef __UBOOT__
  467. static int __devinit dsps_create_musb_pdev(struct dsps_glue *glue, u8 id)
  468. {
  469. struct device *dev = glue->dev;
  470. struct platform_device *pdev = to_platform_device(dev);
  471. struct musb_hdrc_platform_data *pdata = dev->platform_data;
  472. struct platform_device *musb;
  473. struct resource *res;
  474. struct resource resources[2];
  475. char res_name[10];
  476. int ret;
  477. /* get memory resource */
  478. sprintf(res_name, "musb%d", id);
  479. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, res_name);
  480. if (!res) {
  481. dev_err(dev, "%s get mem resource failed\n", res_name);
  482. ret = -ENODEV;
  483. goto err0;
  484. }
  485. res->parent = NULL;
  486. resources[0] = *res;
  487. /* get irq resource */
  488. sprintf(res_name, "musb%d-irq", id);
  489. res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, res_name);
  490. if (!res) {
  491. dev_err(dev, "%s get irq resource failed\n", res_name);
  492. ret = -ENODEV;
  493. goto err0;
  494. }
  495. res->parent = NULL;
  496. resources[1] = *res;
  497. resources[1].name = "mc";
  498. /* allocate the child platform device */
  499. musb = platform_device_alloc("musb-hdrc", -1);
  500. if (!musb) {
  501. dev_err(dev, "failed to allocate musb device\n");
  502. ret = -ENOMEM;
  503. goto err0;
  504. }
  505. musb->dev.parent = dev;
  506. musb->dev.dma_mask = &musb_dmamask;
  507. musb->dev.coherent_dma_mask = musb_dmamask;
  508. glue->musb = musb;
  509. pdata->platform_ops = &dsps_ops;
  510. ret = platform_device_add_resources(musb, resources, 2);
  511. if (ret) {
  512. dev_err(dev, "failed to add resources\n");
  513. goto err1;
  514. }
  515. ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
  516. if (ret) {
  517. dev_err(dev, "failed to add platform_data\n");
  518. goto err1;
  519. }
  520. ret = platform_device_add(musb);
  521. if (ret) {
  522. dev_err(dev, "failed to register musb device\n");
  523. goto err1;
  524. }
  525. return 0;
  526. err1:
  527. platform_device_put(musb);
  528. err0:
  529. return ret;
  530. }
  531. static void __devexit dsps_delete_musb_pdev(struct dsps_glue *glue)
  532. {
  533. platform_device_del(glue->musb);
  534. platform_device_put(glue->musb);
  535. }
  536. static int __devinit dsps_probe(struct platform_device *pdev)
  537. {
  538. const struct platform_device_id *id = platform_get_device_id(pdev);
  539. const struct dsps_musb_wrapper *wrp =
  540. (struct dsps_musb_wrapper *)id->driver_data;
  541. struct dsps_glue *glue;
  542. struct resource *iomem;
  543. int ret;
  544. /* allocate glue */
  545. glue = kzalloc(sizeof(*glue), GFP_KERNEL);
  546. if (!glue) {
  547. dev_err(&pdev->dev, "unable to allocate glue memory\n");
  548. ret = -ENOMEM;
  549. goto err0;
  550. }
  551. /* get memory resource */
  552. iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  553. if (!iomem) {
  554. dev_err(&pdev->dev, "failed to get usbss mem resourse\n");
  555. ret = -ENODEV;
  556. goto err1;
  557. }
  558. glue->dev = &pdev->dev;
  559. glue->wrp = kmemdup(wrp, sizeof(*wrp), GFP_KERNEL);
  560. if (!glue->wrp) {
  561. dev_err(&pdev->dev, "failed to duplicate wrapper struct memory\n");
  562. ret = -ENOMEM;
  563. goto err1;
  564. }
  565. platform_set_drvdata(pdev, glue);
  566. /* enable the usbss clocks */
  567. pm_runtime_enable(&pdev->dev);
  568. ret = pm_runtime_get_sync(&pdev->dev);
  569. if (ret < 0) {
  570. dev_err(&pdev->dev, "pm_runtime_get_sync FAILED");
  571. goto err2;
  572. }
  573. /* create the child platform device for first instances of musb */
  574. ret = dsps_create_musb_pdev(glue, 0);
  575. if (ret != 0) {
  576. dev_err(&pdev->dev, "failed to create child pdev\n");
  577. goto err3;
  578. }
  579. return 0;
  580. err3:
  581. pm_runtime_put(&pdev->dev);
  582. err2:
  583. pm_runtime_disable(&pdev->dev);
  584. kfree(glue->wrp);
  585. err1:
  586. kfree(glue);
  587. err0:
  588. return ret;
  589. }
  590. static int __devexit dsps_remove(struct platform_device *pdev)
  591. {
  592. struct dsps_glue *glue = platform_get_drvdata(pdev);
  593. /* delete the child platform device */
  594. dsps_delete_musb_pdev(glue);
  595. /* disable usbss clocks */
  596. pm_runtime_put(&pdev->dev);
  597. pm_runtime_disable(&pdev->dev);
  598. kfree(glue->wrp);
  599. kfree(glue);
  600. return 0;
  601. }
  602. #ifdef CONFIG_PM_SLEEP
  603. static int dsps_suspend(struct device *dev)
  604. {
  605. struct musb_hdrc_platform_data *plat = dev->platform_data;
  606. struct omap_musb_board_data *data = plat->board_data;
  607. /* Shutdown the on-chip PHY and its PLL. */
  608. if (data->set_phy_power)
  609. data->set_phy_power(0);
  610. return 0;
  611. }
  612. static int dsps_resume(struct device *dev)
  613. {
  614. struct musb_hdrc_platform_data *plat = dev->platform_data;
  615. struct omap_musb_board_data *data = plat->board_data;
  616. /* Start the on-chip PHY and its PLL. */
  617. if (data->set_phy_power)
  618. data->set_phy_power(1);
  619. return 0;
  620. }
  621. #endif
  622. static SIMPLE_DEV_PM_OPS(dsps_pm_ops, dsps_suspend, dsps_resume);
  623. #endif
  624. #ifndef __UBOOT__
  625. static const struct platform_device_id musb_dsps_id_table[] __devinitconst = {
  626. {
  627. .name = "musb-ti81xx",
  628. .driver_data = (kernel_ulong_t) &ti81xx_driver_data,
  629. },
  630. { }, /* Terminating Entry */
  631. };
  632. MODULE_DEVICE_TABLE(platform, musb_dsps_id_table);
  633. static const struct of_device_id musb_dsps_of_match[] __devinitconst = {
  634. { .compatible = "musb-ti81xx", },
  635. { .compatible = "ti,ti81xx-musb", },
  636. { .compatible = "ti,am335x-musb", },
  637. { },
  638. };
  639. MODULE_DEVICE_TABLE(of, musb_dsps_of_match);
  640. static struct platform_driver dsps_usbss_driver = {
  641. .probe = dsps_probe,
  642. .remove = __devexit_p(dsps_remove),
  643. .driver = {
  644. .name = "musb-dsps",
  645. .pm = &dsps_pm_ops,
  646. .of_match_table = musb_dsps_of_match,
  647. },
  648. .id_table = musb_dsps_id_table,
  649. };
  650. MODULE_DESCRIPTION("TI DSPS MUSB Glue Layer");
  651. MODULE_AUTHOR("Ravi B <ravibabu@ti.com>");
  652. MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
  653. MODULE_LICENSE("GPL v2");
  654. static int __init dsps_init(void)
  655. {
  656. return platform_driver_register(&dsps_usbss_driver);
  657. }
  658. subsys_initcall(dsps_init);
  659. static void __exit dsps_exit(void)
  660. {
  661. platform_driver_unregister(&dsps_usbss_driver);
  662. }
  663. module_exit(dsps_exit);
  664. #endif