musb_core.c 68 KB

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  1. /*
  2. * MUSB OTG driver core code
  3. *
  4. * Copyright 2005 Mentor Graphics Corporation
  5. * Copyright (C) 2005-2006 by Texas Instruments
  6. * Copyright (C) 2006-2007 Nokia Corporation
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License
  10. * version 2 as published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but
  13. * WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  15. * General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20. * 02110-1301 USA
  21. *
  22. * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
  23. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  24. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  25. * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  26. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  27. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  28. * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  29. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  31. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32. *
  33. */
  34. /*
  35. * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
  36. *
  37. * This consists of a Host Controller Driver (HCD) and a peripheral
  38. * controller driver implementing the "Gadget" API; OTG support is
  39. * in the works. These are normal Linux-USB controller drivers which
  40. * use IRQs and have no dedicated thread.
  41. *
  42. * This version of the driver has only been used with products from
  43. * Texas Instruments. Those products integrate the Inventra logic
  44. * with other DMA, IRQ, and bus modules, as well as other logic that
  45. * needs to be reflected in this driver.
  46. *
  47. *
  48. * NOTE: the original Mentor code here was pretty much a collection
  49. * of mechanisms that don't seem to have been fully integrated/working
  50. * for *any* Linux kernel version. This version aims at Linux 2.6.now,
  51. * Key open issues include:
  52. *
  53. * - Lack of host-side transaction scheduling, for all transfer types.
  54. * The hardware doesn't do it; instead, software must.
  55. *
  56. * This is not an issue for OTG devices that don't support external
  57. * hubs, but for more "normal" USB hosts it's a user issue that the
  58. * "multipoint" support doesn't scale in the expected ways. That
  59. * includes DaVinci EVM in a common non-OTG mode.
  60. *
  61. * * Control and bulk use dedicated endpoints, and there's as
  62. * yet no mechanism to either (a) reclaim the hardware when
  63. * peripherals are NAKing, which gets complicated with bulk
  64. * endpoints, or (b) use more than a single bulk endpoint in
  65. * each direction.
  66. *
  67. * RESULT: one device may be perceived as blocking another one.
  68. *
  69. * * Interrupt and isochronous will dynamically allocate endpoint
  70. * hardware, but (a) there's no record keeping for bandwidth;
  71. * (b) in the common case that few endpoints are available, there
  72. * is no mechanism to reuse endpoints to talk to multiple devices.
  73. *
  74. * RESULT: At one extreme, bandwidth can be overcommitted in
  75. * some hardware configurations, no faults will be reported.
  76. * At the other extreme, the bandwidth capabilities which do
  77. * exist tend to be severely undercommitted. You can't yet hook
  78. * up both a keyboard and a mouse to an external USB hub.
  79. */
  80. /*
  81. * This gets many kinds of configuration information:
  82. * - Kconfig for everything user-configurable
  83. * - platform_device for addressing, irq, and platform_data
  84. * - platform_data is mostly for board-specific informarion
  85. * (plus recentrly, SOC or family details)
  86. *
  87. * Most of the conditional compilation will (someday) vanish.
  88. */
  89. #ifndef __UBOOT__
  90. #include <linux/module.h>
  91. #include <linux/kernel.h>
  92. #include <linux/sched.h>
  93. #include <linux/slab.h>
  94. #include <linux/init.h>
  95. #include <linux/list.h>
  96. #include <linux/kobject.h>
  97. #include <linux/prefetch.h>
  98. #include <linux/platform_device.h>
  99. #include <linux/io.h>
  100. #else
  101. #include <common.h>
  102. #include <usb.h>
  103. #include <asm/errno.h>
  104. #include <linux/usb/ch9.h>
  105. #include <linux/usb/gadget.h>
  106. #include <linux/usb/musb.h>
  107. #include <asm/io.h>
  108. #include "linux-compat.h"
  109. #include "usb-compat.h"
  110. #endif
  111. #include "musb_core.h"
  112. #define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
  113. #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
  114. #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
  115. #define MUSB_VERSION "6.0"
  116. #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
  117. #define MUSB_DRIVER_NAME "musb-hdrc"
  118. const char musb_driver_name[] = MUSB_DRIVER_NAME;
  119. MODULE_DESCRIPTION(DRIVER_INFO);
  120. MODULE_AUTHOR(DRIVER_AUTHOR);
  121. MODULE_LICENSE("GPL");
  122. MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
  123. #ifndef __UBOOT__
  124. /*-------------------------------------------------------------------------*/
  125. static inline struct musb *dev_to_musb(struct device *dev)
  126. {
  127. return dev_get_drvdata(dev);
  128. }
  129. #endif
  130. /*-------------------------------------------------------------------------*/
  131. #ifndef __UBOOT__
  132. #ifndef CONFIG_BLACKFIN
  133. static int musb_ulpi_read(struct usb_phy *phy, u32 offset)
  134. {
  135. void __iomem *addr = phy->io_priv;
  136. int i = 0;
  137. u8 r;
  138. u8 power;
  139. int ret;
  140. pm_runtime_get_sync(phy->io_dev);
  141. /* Make sure the transceiver is not in low power mode */
  142. power = musb_readb(addr, MUSB_POWER);
  143. power &= ~MUSB_POWER_SUSPENDM;
  144. musb_writeb(addr, MUSB_POWER, power);
  145. /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
  146. * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
  147. */
  148. musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
  149. musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
  150. MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
  151. while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
  152. & MUSB_ULPI_REG_CMPLT)) {
  153. i++;
  154. if (i == 10000) {
  155. ret = -ETIMEDOUT;
  156. goto out;
  157. }
  158. }
  159. r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
  160. r &= ~MUSB_ULPI_REG_CMPLT;
  161. musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
  162. ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
  163. out:
  164. pm_runtime_put(phy->io_dev);
  165. return ret;
  166. }
  167. static int musb_ulpi_write(struct usb_phy *phy, u32 offset, u32 data)
  168. {
  169. void __iomem *addr = phy->io_priv;
  170. int i = 0;
  171. u8 r = 0;
  172. u8 power;
  173. int ret = 0;
  174. pm_runtime_get_sync(phy->io_dev);
  175. /* Make sure the transceiver is not in low power mode */
  176. power = musb_readb(addr, MUSB_POWER);
  177. power &= ~MUSB_POWER_SUSPENDM;
  178. musb_writeb(addr, MUSB_POWER, power);
  179. musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)offset);
  180. musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)data);
  181. musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
  182. while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
  183. & MUSB_ULPI_REG_CMPLT)) {
  184. i++;
  185. if (i == 10000) {
  186. ret = -ETIMEDOUT;
  187. goto out;
  188. }
  189. }
  190. r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
  191. r &= ~MUSB_ULPI_REG_CMPLT;
  192. musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
  193. out:
  194. pm_runtime_put(phy->io_dev);
  195. return ret;
  196. }
  197. #else
  198. #define musb_ulpi_read NULL
  199. #define musb_ulpi_write NULL
  200. #endif
  201. static struct usb_phy_io_ops musb_ulpi_access = {
  202. .read = musb_ulpi_read,
  203. .write = musb_ulpi_write,
  204. };
  205. #endif
  206. /*-------------------------------------------------------------------------*/
  207. #if !defined(CONFIG_USB_MUSB_TUSB6010) && !defined(CONFIG_USB_MUSB_BLACKFIN)
  208. /*
  209. * Load an endpoint's FIFO
  210. */
  211. void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
  212. {
  213. struct musb *musb = hw_ep->musb;
  214. void __iomem *fifo = hw_ep->fifo;
  215. prefetch((u8 *)src);
  216. dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
  217. 'T', hw_ep->epnum, fifo, len, src);
  218. /* we can't assume unaligned reads work */
  219. if (likely((0x01 & (unsigned long) src) == 0)) {
  220. u16 index = 0;
  221. /* best case is 32bit-aligned source address */
  222. if ((0x02 & (unsigned long) src) == 0) {
  223. if (len >= 4) {
  224. writesl(fifo, src + index, len >> 2);
  225. index += len & ~0x03;
  226. }
  227. if (len & 0x02) {
  228. musb_writew(fifo, 0, *(u16 *)&src[index]);
  229. index += 2;
  230. }
  231. } else {
  232. if (len >= 2) {
  233. writesw(fifo, src + index, len >> 1);
  234. index += len & ~0x01;
  235. }
  236. }
  237. if (len & 0x01)
  238. musb_writeb(fifo, 0, src[index]);
  239. } else {
  240. /* byte aligned */
  241. writesb(fifo, src, len);
  242. }
  243. }
  244. #if !defined(CONFIG_USB_MUSB_AM35X)
  245. /*
  246. * Unload an endpoint's FIFO
  247. */
  248. void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
  249. {
  250. struct musb *musb = hw_ep->musb;
  251. void __iomem *fifo = hw_ep->fifo;
  252. dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
  253. 'R', hw_ep->epnum, fifo, len, dst);
  254. /* we can't assume unaligned writes work */
  255. if (likely((0x01 & (unsigned long) dst) == 0)) {
  256. u16 index = 0;
  257. /* best case is 32bit-aligned destination address */
  258. if ((0x02 & (unsigned long) dst) == 0) {
  259. if (len >= 4) {
  260. readsl(fifo, dst, len >> 2);
  261. index = len & ~0x03;
  262. }
  263. if (len & 0x02) {
  264. *(u16 *)&dst[index] = musb_readw(fifo, 0);
  265. index += 2;
  266. }
  267. } else {
  268. if (len >= 2) {
  269. readsw(fifo, dst, len >> 1);
  270. index = len & ~0x01;
  271. }
  272. }
  273. if (len & 0x01)
  274. dst[index] = musb_readb(fifo, 0);
  275. } else {
  276. /* byte aligned */
  277. readsb(fifo, dst, len);
  278. }
  279. }
  280. #endif
  281. #endif /* normal PIO */
  282. /*-------------------------------------------------------------------------*/
  283. /* for high speed test mode; see USB 2.0 spec 7.1.20 */
  284. static const u8 musb_test_packet[53] = {
  285. /* implicit SYNC then DATA0 to start */
  286. /* JKJKJKJK x9 */
  287. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  288. /* JJKKJJKK x8 */
  289. 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
  290. /* JJJJKKKK x8 */
  291. 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
  292. /* JJJJJJJKKKKKKK x8 */
  293. 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
  294. /* JJJJJJJK x8 */
  295. 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
  296. /* JKKKKKKK x10, JK */
  297. 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
  298. /* implicit CRC16 then EOP to end */
  299. };
  300. void musb_load_testpacket(struct musb *musb)
  301. {
  302. void __iomem *regs = musb->endpoints[0].regs;
  303. musb_ep_select(musb->mregs, 0);
  304. musb_write_fifo(musb->control_ep,
  305. sizeof(musb_test_packet), musb_test_packet);
  306. musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
  307. }
  308. #ifndef __UBOOT__
  309. /*-------------------------------------------------------------------------*/
  310. /*
  311. * Handles OTG hnp timeouts, such as b_ase0_brst
  312. */
  313. void musb_otg_timer_func(unsigned long data)
  314. {
  315. struct musb *musb = (struct musb *)data;
  316. unsigned long flags;
  317. spin_lock_irqsave(&musb->lock, flags);
  318. switch (musb->xceiv->state) {
  319. case OTG_STATE_B_WAIT_ACON:
  320. dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
  321. musb_g_disconnect(musb);
  322. musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
  323. musb->is_active = 0;
  324. break;
  325. case OTG_STATE_A_SUSPEND:
  326. case OTG_STATE_A_WAIT_BCON:
  327. dev_dbg(musb->controller, "HNP: %s timeout\n",
  328. otg_state_string(musb->xceiv->state));
  329. musb_platform_set_vbus(musb, 0);
  330. musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
  331. break;
  332. default:
  333. dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
  334. otg_state_string(musb->xceiv->state));
  335. }
  336. musb->ignore_disconnect = 0;
  337. spin_unlock_irqrestore(&musb->lock, flags);
  338. }
  339. /*
  340. * Stops the HNP transition. Caller must take care of locking.
  341. */
  342. void musb_hnp_stop(struct musb *musb)
  343. {
  344. struct usb_hcd *hcd = musb_to_hcd(musb);
  345. void __iomem *mbase = musb->mregs;
  346. u8 reg;
  347. dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state));
  348. switch (musb->xceiv->state) {
  349. case OTG_STATE_A_PERIPHERAL:
  350. musb_g_disconnect(musb);
  351. dev_dbg(musb->controller, "HNP: back to %s\n",
  352. otg_state_string(musb->xceiv->state));
  353. break;
  354. case OTG_STATE_B_HOST:
  355. dev_dbg(musb->controller, "HNP: Disabling HR\n");
  356. hcd->self.is_b_host = 0;
  357. musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
  358. MUSB_DEV_MODE(musb);
  359. reg = musb_readb(mbase, MUSB_POWER);
  360. reg |= MUSB_POWER_SUSPENDM;
  361. musb_writeb(mbase, MUSB_POWER, reg);
  362. /* REVISIT: Start SESSION_REQUEST here? */
  363. break;
  364. default:
  365. dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
  366. otg_state_string(musb->xceiv->state));
  367. }
  368. /*
  369. * When returning to A state after HNP, avoid hub_port_rebounce(),
  370. * which cause occasional OPT A "Did not receive reset after connect"
  371. * errors.
  372. */
  373. musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
  374. }
  375. #endif
  376. /*
  377. * Interrupt Service Routine to record USB "global" interrupts.
  378. * Since these do not happen often and signify things of
  379. * paramount importance, it seems OK to check them individually;
  380. * the order of the tests is specified in the manual
  381. *
  382. * @param musb instance pointer
  383. * @param int_usb register contents
  384. * @param devctl
  385. * @param power
  386. */
  387. static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
  388. u8 devctl, u8 power)
  389. {
  390. #ifndef __UBOOT__
  391. struct usb_otg *otg = musb->xceiv->otg;
  392. #endif
  393. irqreturn_t handled = IRQ_NONE;
  394. dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
  395. int_usb);
  396. #ifndef __UBOOT__
  397. /* in host mode, the peripheral may issue remote wakeup.
  398. * in peripheral mode, the host may resume the link.
  399. * spurious RESUME irqs happen too, paired with SUSPEND.
  400. */
  401. if (int_usb & MUSB_INTR_RESUME) {
  402. handled = IRQ_HANDLED;
  403. dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state));
  404. if (devctl & MUSB_DEVCTL_HM) {
  405. void __iomem *mbase = musb->mregs;
  406. switch (musb->xceiv->state) {
  407. case OTG_STATE_A_SUSPEND:
  408. /* remote wakeup? later, GetPortStatus
  409. * will stop RESUME signaling
  410. */
  411. if (power & MUSB_POWER_SUSPENDM) {
  412. /* spurious */
  413. musb->int_usb &= ~MUSB_INTR_SUSPEND;
  414. dev_dbg(musb->controller, "Spurious SUSPENDM\n");
  415. break;
  416. }
  417. power &= ~MUSB_POWER_SUSPENDM;
  418. musb_writeb(mbase, MUSB_POWER,
  419. power | MUSB_POWER_RESUME);
  420. musb->port1_status |=
  421. (USB_PORT_STAT_C_SUSPEND << 16)
  422. | MUSB_PORT_STAT_RESUME;
  423. musb->rh_timer = jiffies
  424. + msecs_to_jiffies(20);
  425. musb->xceiv->state = OTG_STATE_A_HOST;
  426. musb->is_active = 1;
  427. usb_hcd_resume_root_hub(musb_to_hcd(musb));
  428. break;
  429. case OTG_STATE_B_WAIT_ACON:
  430. musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
  431. musb->is_active = 1;
  432. MUSB_DEV_MODE(musb);
  433. break;
  434. default:
  435. WARNING("bogus %s RESUME (%s)\n",
  436. "host",
  437. otg_state_string(musb->xceiv->state));
  438. }
  439. } else {
  440. switch (musb->xceiv->state) {
  441. case OTG_STATE_A_SUSPEND:
  442. /* possibly DISCONNECT is upcoming */
  443. musb->xceiv->state = OTG_STATE_A_HOST;
  444. usb_hcd_resume_root_hub(musb_to_hcd(musb));
  445. break;
  446. case OTG_STATE_B_WAIT_ACON:
  447. case OTG_STATE_B_PERIPHERAL:
  448. /* disconnect while suspended? we may
  449. * not get a disconnect irq...
  450. */
  451. if ((devctl & MUSB_DEVCTL_VBUS)
  452. != (3 << MUSB_DEVCTL_VBUS_SHIFT)
  453. ) {
  454. musb->int_usb |= MUSB_INTR_DISCONNECT;
  455. musb->int_usb &= ~MUSB_INTR_SUSPEND;
  456. break;
  457. }
  458. musb_g_resume(musb);
  459. break;
  460. case OTG_STATE_B_IDLE:
  461. musb->int_usb &= ~MUSB_INTR_SUSPEND;
  462. break;
  463. default:
  464. WARNING("bogus %s RESUME (%s)\n",
  465. "peripheral",
  466. otg_state_string(musb->xceiv->state));
  467. }
  468. }
  469. }
  470. /* see manual for the order of the tests */
  471. if (int_usb & MUSB_INTR_SESSREQ) {
  472. void __iomem *mbase = musb->mregs;
  473. if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
  474. && (devctl & MUSB_DEVCTL_BDEVICE)) {
  475. dev_dbg(musb->controller, "SessReq while on B state\n");
  476. return IRQ_HANDLED;
  477. }
  478. dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
  479. otg_state_string(musb->xceiv->state));
  480. /* IRQ arrives from ID pin sense or (later, if VBUS power
  481. * is removed) SRP. responses are time critical:
  482. * - turn on VBUS (with silicon-specific mechanism)
  483. * - go through A_WAIT_VRISE
  484. * - ... to A_WAIT_BCON.
  485. * a_wait_vrise_tmout triggers VBUS_ERROR transitions
  486. */
  487. musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
  488. musb->ep0_stage = MUSB_EP0_START;
  489. musb->xceiv->state = OTG_STATE_A_IDLE;
  490. MUSB_HST_MODE(musb);
  491. musb_platform_set_vbus(musb, 1);
  492. handled = IRQ_HANDLED;
  493. }
  494. if (int_usb & MUSB_INTR_VBUSERROR) {
  495. int ignore = 0;
  496. /* During connection as an A-Device, we may see a short
  497. * current spikes causing voltage drop, because of cable
  498. * and peripheral capacitance combined with vbus draw.
  499. * (So: less common with truly self-powered devices, where
  500. * vbus doesn't act like a power supply.)
  501. *
  502. * Such spikes are short; usually less than ~500 usec, max
  503. * of ~2 msec. That is, they're not sustained overcurrent
  504. * errors, though they're reported using VBUSERROR irqs.
  505. *
  506. * Workarounds: (a) hardware: use self powered devices.
  507. * (b) software: ignore non-repeated VBUS errors.
  508. *
  509. * REVISIT: do delays from lots of DEBUG_KERNEL checks
  510. * make trouble here, keeping VBUS < 4.4V ?
  511. */
  512. switch (musb->xceiv->state) {
  513. case OTG_STATE_A_HOST:
  514. /* recovery is dicey once we've gotten past the
  515. * initial stages of enumeration, but if VBUS
  516. * stayed ok at the other end of the link, and
  517. * another reset is due (at least for high speed,
  518. * to redo the chirp etc), it might work OK...
  519. */
  520. case OTG_STATE_A_WAIT_BCON:
  521. case OTG_STATE_A_WAIT_VRISE:
  522. if (musb->vbuserr_retry) {
  523. void __iomem *mbase = musb->mregs;
  524. musb->vbuserr_retry--;
  525. ignore = 1;
  526. devctl |= MUSB_DEVCTL_SESSION;
  527. musb_writeb(mbase, MUSB_DEVCTL, devctl);
  528. } else {
  529. musb->port1_status |=
  530. USB_PORT_STAT_OVERCURRENT
  531. | (USB_PORT_STAT_C_OVERCURRENT << 16);
  532. }
  533. break;
  534. default:
  535. break;
  536. }
  537. dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
  538. otg_state_string(musb->xceiv->state),
  539. devctl,
  540. ({ char *s;
  541. switch (devctl & MUSB_DEVCTL_VBUS) {
  542. case 0 << MUSB_DEVCTL_VBUS_SHIFT:
  543. s = "<SessEnd"; break;
  544. case 1 << MUSB_DEVCTL_VBUS_SHIFT:
  545. s = "<AValid"; break;
  546. case 2 << MUSB_DEVCTL_VBUS_SHIFT:
  547. s = "<VBusValid"; break;
  548. /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
  549. default:
  550. s = "VALID"; break;
  551. }; s; }),
  552. VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
  553. musb->port1_status);
  554. /* go through A_WAIT_VFALL then start a new session */
  555. if (!ignore)
  556. musb_platform_set_vbus(musb, 0);
  557. handled = IRQ_HANDLED;
  558. }
  559. if (int_usb & MUSB_INTR_SUSPEND) {
  560. dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n",
  561. otg_state_string(musb->xceiv->state), devctl, power);
  562. handled = IRQ_HANDLED;
  563. switch (musb->xceiv->state) {
  564. case OTG_STATE_A_PERIPHERAL:
  565. /* We also come here if the cable is removed, since
  566. * this silicon doesn't report ID-no-longer-grounded.
  567. *
  568. * We depend on T(a_wait_bcon) to shut us down, and
  569. * hope users don't do anything dicey during this
  570. * undesired detour through A_WAIT_BCON.
  571. */
  572. musb_hnp_stop(musb);
  573. usb_hcd_resume_root_hub(musb_to_hcd(musb));
  574. musb_root_disconnect(musb);
  575. musb_platform_try_idle(musb, jiffies
  576. + msecs_to_jiffies(musb->a_wait_bcon
  577. ? : OTG_TIME_A_WAIT_BCON));
  578. break;
  579. case OTG_STATE_B_IDLE:
  580. if (!musb->is_active)
  581. break;
  582. case OTG_STATE_B_PERIPHERAL:
  583. musb_g_suspend(musb);
  584. musb->is_active = is_otg_enabled(musb)
  585. && otg->gadget->b_hnp_enable;
  586. if (musb->is_active) {
  587. musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
  588. dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
  589. mod_timer(&musb->otg_timer, jiffies
  590. + msecs_to_jiffies(
  591. OTG_TIME_B_ASE0_BRST));
  592. }
  593. break;
  594. case OTG_STATE_A_WAIT_BCON:
  595. if (musb->a_wait_bcon != 0)
  596. musb_platform_try_idle(musb, jiffies
  597. + msecs_to_jiffies(musb->a_wait_bcon));
  598. break;
  599. case OTG_STATE_A_HOST:
  600. musb->xceiv->state = OTG_STATE_A_SUSPEND;
  601. musb->is_active = is_otg_enabled(musb)
  602. && otg->host->b_hnp_enable;
  603. break;
  604. case OTG_STATE_B_HOST:
  605. /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
  606. dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
  607. break;
  608. default:
  609. /* "should not happen" */
  610. musb->is_active = 0;
  611. break;
  612. }
  613. }
  614. #endif
  615. if (int_usb & MUSB_INTR_CONNECT) {
  616. struct usb_hcd *hcd = musb_to_hcd(musb);
  617. handled = IRQ_HANDLED;
  618. musb->is_active = 1;
  619. musb->ep0_stage = MUSB_EP0_START;
  620. /* flush endpoints when transitioning from Device Mode */
  621. if (is_peripheral_active(musb)) {
  622. /* REVISIT HNP; just force disconnect */
  623. }
  624. musb_writew(musb->mregs, MUSB_INTRTXE, musb->epmask);
  625. musb_writew(musb->mregs, MUSB_INTRRXE, musb->epmask & 0xfffe);
  626. musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
  627. #ifndef __UBOOT__
  628. musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
  629. |USB_PORT_STAT_HIGH_SPEED
  630. |USB_PORT_STAT_ENABLE
  631. );
  632. musb->port1_status |= USB_PORT_STAT_CONNECTION
  633. |(USB_PORT_STAT_C_CONNECTION << 16);
  634. /* high vs full speed is just a guess until after reset */
  635. if (devctl & MUSB_DEVCTL_LSDEV)
  636. musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
  637. /* indicate new connection to OTG machine */
  638. switch (musb->xceiv->state) {
  639. case OTG_STATE_B_PERIPHERAL:
  640. if (int_usb & MUSB_INTR_SUSPEND) {
  641. dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
  642. int_usb &= ~MUSB_INTR_SUSPEND;
  643. goto b_host;
  644. } else
  645. dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
  646. break;
  647. case OTG_STATE_B_WAIT_ACON:
  648. dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
  649. b_host:
  650. musb->xceiv->state = OTG_STATE_B_HOST;
  651. hcd->self.is_b_host = 1;
  652. musb->ignore_disconnect = 0;
  653. del_timer(&musb->otg_timer);
  654. break;
  655. default:
  656. if ((devctl & MUSB_DEVCTL_VBUS)
  657. == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
  658. musb->xceiv->state = OTG_STATE_A_HOST;
  659. hcd->self.is_b_host = 0;
  660. }
  661. break;
  662. }
  663. /* poke the root hub */
  664. MUSB_HST_MODE(musb);
  665. if (hcd->status_urb)
  666. usb_hcd_poll_rh_status(hcd);
  667. else
  668. usb_hcd_resume_root_hub(hcd);
  669. dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
  670. otg_state_string(musb->xceiv->state), devctl);
  671. #endif
  672. }
  673. #ifndef __UBOOT__
  674. if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
  675. dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
  676. otg_state_string(musb->xceiv->state),
  677. MUSB_MODE(musb), devctl);
  678. handled = IRQ_HANDLED;
  679. switch (musb->xceiv->state) {
  680. case OTG_STATE_A_HOST:
  681. case OTG_STATE_A_SUSPEND:
  682. usb_hcd_resume_root_hub(musb_to_hcd(musb));
  683. musb_root_disconnect(musb);
  684. if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
  685. musb_platform_try_idle(musb, jiffies
  686. + msecs_to_jiffies(musb->a_wait_bcon));
  687. break;
  688. case OTG_STATE_B_HOST:
  689. /* REVISIT this behaves for "real disconnect"
  690. * cases; make sure the other transitions from
  691. * from B_HOST act right too. The B_HOST code
  692. * in hnp_stop() is currently not used...
  693. */
  694. musb_root_disconnect(musb);
  695. musb_to_hcd(musb)->self.is_b_host = 0;
  696. musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
  697. MUSB_DEV_MODE(musb);
  698. musb_g_disconnect(musb);
  699. break;
  700. case OTG_STATE_A_PERIPHERAL:
  701. musb_hnp_stop(musb);
  702. musb_root_disconnect(musb);
  703. /* FALLTHROUGH */
  704. case OTG_STATE_B_WAIT_ACON:
  705. /* FALLTHROUGH */
  706. case OTG_STATE_B_PERIPHERAL:
  707. case OTG_STATE_B_IDLE:
  708. musb_g_disconnect(musb);
  709. break;
  710. default:
  711. WARNING("unhandled DISCONNECT transition (%s)\n",
  712. otg_state_string(musb->xceiv->state));
  713. break;
  714. }
  715. }
  716. /* mentor saves a bit: bus reset and babble share the same irq.
  717. * only host sees babble; only peripheral sees bus reset.
  718. */
  719. if (int_usb & MUSB_INTR_RESET) {
  720. handled = IRQ_HANDLED;
  721. if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
  722. /*
  723. * Looks like non-HS BABBLE can be ignored, but
  724. * HS BABBLE is an error condition. For HS the solution
  725. * is to avoid babble in the first place and fix what
  726. * caused BABBLE. When HS BABBLE happens we can only
  727. * stop the session.
  728. */
  729. if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
  730. dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
  731. else {
  732. ERR("Stopping host session -- babble\n");
  733. musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
  734. }
  735. } else if (is_peripheral_capable()) {
  736. dev_dbg(musb->controller, "BUS RESET as %s\n",
  737. otg_state_string(musb->xceiv->state));
  738. switch (musb->xceiv->state) {
  739. case OTG_STATE_A_SUSPEND:
  740. /* We need to ignore disconnect on suspend
  741. * otherwise tusb 2.0 won't reconnect after a
  742. * power cycle, which breaks otg compliance.
  743. */
  744. musb->ignore_disconnect = 1;
  745. musb_g_reset(musb);
  746. /* FALLTHROUGH */
  747. case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
  748. /* never use invalid T(a_wait_bcon) */
  749. dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
  750. otg_state_string(musb->xceiv->state),
  751. TA_WAIT_BCON(musb));
  752. mod_timer(&musb->otg_timer, jiffies
  753. + msecs_to_jiffies(TA_WAIT_BCON(musb)));
  754. break;
  755. case OTG_STATE_A_PERIPHERAL:
  756. musb->ignore_disconnect = 0;
  757. del_timer(&musb->otg_timer);
  758. musb_g_reset(musb);
  759. break;
  760. case OTG_STATE_B_WAIT_ACON:
  761. dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
  762. otg_state_string(musb->xceiv->state));
  763. musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
  764. musb_g_reset(musb);
  765. break;
  766. case OTG_STATE_B_IDLE:
  767. musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
  768. /* FALLTHROUGH */
  769. case OTG_STATE_B_PERIPHERAL:
  770. musb_g_reset(musb);
  771. break;
  772. default:
  773. dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
  774. otg_state_string(musb->xceiv->state));
  775. }
  776. }
  777. }
  778. #endif
  779. #if 0
  780. /* REVISIT ... this would be for multiplexing periodic endpoints, or
  781. * supporting transfer phasing to prevent exceeding ISO bandwidth
  782. * limits of a given frame or microframe.
  783. *
  784. * It's not needed for peripheral side, which dedicates endpoints;
  785. * though it _might_ use SOF irqs for other purposes.
  786. *
  787. * And it's not currently needed for host side, which also dedicates
  788. * endpoints, relies on TX/RX interval registers, and isn't claimed
  789. * to support ISO transfers yet.
  790. */
  791. if (int_usb & MUSB_INTR_SOF) {
  792. void __iomem *mbase = musb->mregs;
  793. struct musb_hw_ep *ep;
  794. u8 epnum;
  795. u16 frame;
  796. dev_dbg(musb->controller, "START_OF_FRAME\n");
  797. handled = IRQ_HANDLED;
  798. /* start any periodic Tx transfers waiting for current frame */
  799. frame = musb_readw(mbase, MUSB_FRAME);
  800. ep = musb->endpoints;
  801. for (epnum = 1; (epnum < musb->nr_endpoints)
  802. && (musb->epmask >= (1 << epnum));
  803. epnum++, ep++) {
  804. /*
  805. * FIXME handle framecounter wraps (12 bits)
  806. * eliminate duplicated StartUrb logic
  807. */
  808. if (ep->dwWaitFrame >= frame) {
  809. ep->dwWaitFrame = 0;
  810. pr_debug("SOF --> periodic TX%s on %d\n",
  811. ep->tx_channel ? " DMA" : "",
  812. epnum);
  813. if (!ep->tx_channel)
  814. musb_h_tx_start(musb, epnum);
  815. else
  816. cppi_hostdma_start(musb, epnum);
  817. }
  818. } /* end of for loop */
  819. }
  820. #endif
  821. schedule_work(&musb->irq_work);
  822. return handled;
  823. }
  824. /*-------------------------------------------------------------------------*/
  825. /*
  826. * Program the HDRC to start (enable interrupts, dma, etc.).
  827. */
  828. void musb_start(struct musb *musb)
  829. {
  830. void __iomem *regs = musb->mregs;
  831. u8 devctl = musb_readb(regs, MUSB_DEVCTL);
  832. dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
  833. /* Set INT enable registers, enable interrupts */
  834. musb_writew(regs, MUSB_INTRTXE, musb->epmask);
  835. musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
  836. musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
  837. musb_writeb(regs, MUSB_TESTMODE, 0);
  838. /* put into basic highspeed mode and start session */
  839. musb_writeb(regs, MUSB_POWER, MUSB_POWER_ISOUPDATE
  840. #ifdef CONFIG_USB_GADGET_DUALSPEED
  841. | MUSB_POWER_HSENAB
  842. #endif
  843. /* ENSUSPEND wedges tusb */
  844. /* | MUSB_POWER_ENSUSPEND */
  845. );
  846. musb->is_active = 0;
  847. devctl = musb_readb(regs, MUSB_DEVCTL);
  848. devctl &= ~MUSB_DEVCTL_SESSION;
  849. if (is_otg_enabled(musb)) {
  850. #ifndef __UBOOT__
  851. /* session started after:
  852. * (a) ID-grounded irq, host mode;
  853. * (b) vbus present/connect IRQ, peripheral mode;
  854. * (c) peripheral initiates, using SRP
  855. */
  856. if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
  857. musb->is_active = 1;
  858. else
  859. devctl |= MUSB_DEVCTL_SESSION;
  860. #endif
  861. } else if (is_host_enabled(musb)) {
  862. /* assume ID pin is hard-wired to ground */
  863. devctl |= MUSB_DEVCTL_SESSION;
  864. } else /* peripheral is enabled */ {
  865. if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
  866. musb->is_active = 1;
  867. }
  868. musb_platform_enable(musb);
  869. musb_writeb(regs, MUSB_DEVCTL, devctl);
  870. }
  871. static void musb_generic_disable(struct musb *musb)
  872. {
  873. void __iomem *mbase = musb->mregs;
  874. u16 temp;
  875. /* disable interrupts */
  876. musb_writeb(mbase, MUSB_INTRUSBE, 0);
  877. musb_writew(mbase, MUSB_INTRTXE, 0);
  878. musb_writew(mbase, MUSB_INTRRXE, 0);
  879. /* off */
  880. musb_writeb(mbase, MUSB_DEVCTL, 0);
  881. /* flush pending interrupts */
  882. temp = musb_readb(mbase, MUSB_INTRUSB);
  883. temp = musb_readw(mbase, MUSB_INTRTX);
  884. temp = musb_readw(mbase, MUSB_INTRRX);
  885. }
  886. /*
  887. * Make the HDRC stop (disable interrupts, etc.);
  888. * reversible by musb_start
  889. * called on gadget driver unregister
  890. * with controller locked, irqs blocked
  891. * acts as a NOP unless some role activated the hardware
  892. */
  893. void musb_stop(struct musb *musb)
  894. {
  895. /* stop IRQs, timers, ... */
  896. musb_platform_disable(musb);
  897. musb_generic_disable(musb);
  898. dev_dbg(musb->controller, "HDRC disabled\n");
  899. /* FIXME
  900. * - mark host and/or peripheral drivers unusable/inactive
  901. * - disable DMA (and enable it in HdrcStart)
  902. * - make sure we can musb_start() after musb_stop(); with
  903. * OTG mode, gadget driver module rmmod/modprobe cycles that
  904. * - ...
  905. */
  906. musb_platform_try_idle(musb, 0);
  907. }
  908. #ifndef __UBOOT__
  909. static void musb_shutdown(struct platform_device *pdev)
  910. {
  911. struct musb *musb = dev_to_musb(&pdev->dev);
  912. unsigned long flags;
  913. pm_runtime_get_sync(musb->controller);
  914. musb_gadget_cleanup(musb);
  915. spin_lock_irqsave(&musb->lock, flags);
  916. musb_platform_disable(musb);
  917. musb_generic_disable(musb);
  918. spin_unlock_irqrestore(&musb->lock, flags);
  919. if (!is_otg_enabled(musb) && is_host_enabled(musb))
  920. usb_remove_hcd(musb_to_hcd(musb));
  921. musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
  922. musb_platform_exit(musb);
  923. pm_runtime_put(musb->controller);
  924. /* FIXME power down */
  925. }
  926. #endif
  927. /*-------------------------------------------------------------------------*/
  928. /*
  929. * The silicon either has hard-wired endpoint configurations, or else
  930. * "dynamic fifo" sizing. The driver has support for both, though at this
  931. * writing only the dynamic sizing is very well tested. Since we switched
  932. * away from compile-time hardware parameters, we can no longer rely on
  933. * dead code elimination to leave only the relevant one in the object file.
  934. *
  935. * We don't currently use dynamic fifo setup capability to do anything
  936. * more than selecting one of a bunch of predefined configurations.
  937. */
  938. #if defined(CONFIG_USB_MUSB_TUSB6010) \
  939. || defined(CONFIG_USB_MUSB_TUSB6010_MODULE) \
  940. || defined(CONFIG_USB_MUSB_OMAP2PLUS) \
  941. || defined(CONFIG_USB_MUSB_OMAP2PLUS_MODULE) \
  942. || defined(CONFIG_USB_MUSB_AM35X) \
  943. || defined(CONFIG_USB_MUSB_AM35X_MODULE) \
  944. || defined(CONFIG_USB_MUSB_DSPS) \
  945. || defined(CONFIG_USB_MUSB_DSPS_MODULE)
  946. static ushort __devinitdata fifo_mode = 4;
  947. #elif defined(CONFIG_USB_MUSB_UX500) \
  948. || defined(CONFIG_USB_MUSB_UX500_MODULE)
  949. static ushort __devinitdata fifo_mode = 5;
  950. #else
  951. static ushort __devinitdata fifo_mode = 2;
  952. #endif
  953. /* "modprobe ... fifo_mode=1" etc */
  954. module_param(fifo_mode, ushort, 0);
  955. MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
  956. /*
  957. * tables defining fifo_mode values. define more if you like.
  958. * for host side, make sure both halves of ep1 are set up.
  959. */
  960. /* mode 0 - fits in 2KB */
  961. static struct musb_fifo_cfg __devinitdata mode_0_cfg[] = {
  962. { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
  963. { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
  964. { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
  965. { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
  966. { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
  967. };
  968. /* mode 1 - fits in 4KB */
  969. static struct musb_fifo_cfg __devinitdata mode_1_cfg[] = {
  970. { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
  971. { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
  972. { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
  973. { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
  974. { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
  975. };
  976. /* mode 2 - fits in 4KB */
  977. static struct musb_fifo_cfg __devinitdata mode_2_cfg[] = {
  978. { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
  979. { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
  980. { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
  981. { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
  982. { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
  983. { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
  984. };
  985. /* mode 3 - fits in 4KB */
  986. static struct musb_fifo_cfg __devinitdata mode_3_cfg[] = {
  987. { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
  988. { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
  989. { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
  990. { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
  991. { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
  992. { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
  993. };
  994. /* mode 4 - fits in 16KB */
  995. static struct musb_fifo_cfg __devinitdata mode_4_cfg[] = {
  996. { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
  997. { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
  998. { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
  999. { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
  1000. { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
  1001. { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
  1002. { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
  1003. { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
  1004. { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
  1005. { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
  1006. { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
  1007. { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
  1008. { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
  1009. { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
  1010. { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
  1011. { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
  1012. { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
  1013. { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
  1014. { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
  1015. { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
  1016. { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
  1017. { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
  1018. { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
  1019. { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
  1020. { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
  1021. { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
  1022. { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
  1023. };
  1024. /* mode 5 - fits in 8KB */
  1025. static struct musb_fifo_cfg __devinitdata mode_5_cfg[] = {
  1026. { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
  1027. { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
  1028. { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
  1029. { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
  1030. { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
  1031. { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
  1032. { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
  1033. { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
  1034. { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
  1035. { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
  1036. { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
  1037. { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
  1038. { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
  1039. { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
  1040. { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
  1041. { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
  1042. { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
  1043. { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
  1044. { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
  1045. { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
  1046. { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
  1047. { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
  1048. { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
  1049. { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
  1050. { .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
  1051. { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
  1052. { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
  1053. };
  1054. /*
  1055. * configure a fifo; for non-shared endpoints, this may be called
  1056. * once for a tx fifo and once for an rx fifo.
  1057. *
  1058. * returns negative errno or offset for next fifo.
  1059. */
  1060. static int __devinit
  1061. fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
  1062. const struct musb_fifo_cfg *cfg, u16 offset)
  1063. {
  1064. void __iomem *mbase = musb->mregs;
  1065. int size = 0;
  1066. u16 maxpacket = cfg->maxpacket;
  1067. u16 c_off = offset >> 3;
  1068. u8 c_size;
  1069. /* expect hw_ep has already been zero-initialized */
  1070. size = ffs(max(maxpacket, (u16) 8)) - 1;
  1071. maxpacket = 1 << size;
  1072. c_size = size - 3;
  1073. if (cfg->mode == BUF_DOUBLE) {
  1074. if ((offset + (maxpacket << 1)) >
  1075. (1 << (musb->config->ram_bits + 2)))
  1076. return -EMSGSIZE;
  1077. c_size |= MUSB_FIFOSZ_DPB;
  1078. } else {
  1079. if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
  1080. return -EMSGSIZE;
  1081. }
  1082. /* configure the FIFO */
  1083. musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
  1084. /* EP0 reserved endpoint for control, bidirectional;
  1085. * EP1 reserved for bulk, two unidirection halves.
  1086. */
  1087. if (hw_ep->epnum == 1)
  1088. musb->bulk_ep = hw_ep;
  1089. /* REVISIT error check: be sure ep0 can both rx and tx ... */
  1090. switch (cfg->style) {
  1091. case FIFO_TX:
  1092. musb_write_txfifosz(mbase, c_size);
  1093. musb_write_txfifoadd(mbase, c_off);
  1094. hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
  1095. hw_ep->max_packet_sz_tx = maxpacket;
  1096. break;
  1097. case FIFO_RX:
  1098. musb_write_rxfifosz(mbase, c_size);
  1099. musb_write_rxfifoadd(mbase, c_off);
  1100. hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
  1101. hw_ep->max_packet_sz_rx = maxpacket;
  1102. break;
  1103. case FIFO_RXTX:
  1104. musb_write_txfifosz(mbase, c_size);
  1105. musb_write_txfifoadd(mbase, c_off);
  1106. hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
  1107. hw_ep->max_packet_sz_rx = maxpacket;
  1108. musb_write_rxfifosz(mbase, c_size);
  1109. musb_write_rxfifoadd(mbase, c_off);
  1110. hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
  1111. hw_ep->max_packet_sz_tx = maxpacket;
  1112. hw_ep->is_shared_fifo = true;
  1113. break;
  1114. }
  1115. /* NOTE rx and tx endpoint irqs aren't managed separately,
  1116. * which happens to be ok
  1117. */
  1118. musb->epmask |= (1 << hw_ep->epnum);
  1119. return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
  1120. }
  1121. static struct musb_fifo_cfg __devinitdata ep0_cfg = {
  1122. .style = FIFO_RXTX, .maxpacket = 64,
  1123. };
  1124. static int __devinit ep_config_from_table(struct musb *musb)
  1125. {
  1126. const struct musb_fifo_cfg *cfg;
  1127. unsigned i, n;
  1128. int offset;
  1129. struct musb_hw_ep *hw_ep = musb->endpoints;
  1130. if (musb->config->fifo_cfg) {
  1131. cfg = musb->config->fifo_cfg;
  1132. n = musb->config->fifo_cfg_size;
  1133. goto done;
  1134. }
  1135. switch (fifo_mode) {
  1136. default:
  1137. fifo_mode = 0;
  1138. /* FALLTHROUGH */
  1139. case 0:
  1140. cfg = mode_0_cfg;
  1141. n = ARRAY_SIZE(mode_0_cfg);
  1142. break;
  1143. case 1:
  1144. cfg = mode_1_cfg;
  1145. n = ARRAY_SIZE(mode_1_cfg);
  1146. break;
  1147. case 2:
  1148. cfg = mode_2_cfg;
  1149. n = ARRAY_SIZE(mode_2_cfg);
  1150. break;
  1151. case 3:
  1152. cfg = mode_3_cfg;
  1153. n = ARRAY_SIZE(mode_3_cfg);
  1154. break;
  1155. case 4:
  1156. cfg = mode_4_cfg;
  1157. n = ARRAY_SIZE(mode_4_cfg);
  1158. break;
  1159. case 5:
  1160. cfg = mode_5_cfg;
  1161. n = ARRAY_SIZE(mode_5_cfg);
  1162. break;
  1163. }
  1164. pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode);
  1165. done:
  1166. offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
  1167. /* assert(offset > 0) */
  1168. /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
  1169. * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
  1170. */
  1171. for (i = 0; i < n; i++) {
  1172. u8 epn = cfg->hw_ep_num;
  1173. if (epn >= musb->config->num_eps) {
  1174. pr_debug("%s: invalid ep %d\n",
  1175. musb_driver_name, epn);
  1176. return -EINVAL;
  1177. }
  1178. offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
  1179. if (offset < 0) {
  1180. pr_debug("%s: mem overrun, ep %d\n",
  1181. musb_driver_name, epn);
  1182. return -EINVAL;
  1183. }
  1184. epn++;
  1185. musb->nr_endpoints = max(epn, musb->nr_endpoints);
  1186. }
  1187. pr_debug("%s: %d/%d max ep, %d/%d memory\n", musb_driver_name, n + 1,
  1188. musb->config->num_eps * 2 - 1, offset,
  1189. (1 << (musb->config->ram_bits + 2)));
  1190. if (!musb->bulk_ep) {
  1191. pr_debug("%s: missing bulk\n", musb_driver_name);
  1192. return -EINVAL;
  1193. }
  1194. return 0;
  1195. }
  1196. /*
  1197. * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
  1198. * @param musb the controller
  1199. */
  1200. static int __devinit ep_config_from_hw(struct musb *musb)
  1201. {
  1202. u8 epnum = 0;
  1203. struct musb_hw_ep *hw_ep;
  1204. void *mbase = musb->mregs;
  1205. int ret = 0;
  1206. dev_dbg(musb->controller, "<== static silicon ep config\n");
  1207. /* FIXME pick up ep0 maxpacket size */
  1208. for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
  1209. musb_ep_select(mbase, epnum);
  1210. hw_ep = musb->endpoints + epnum;
  1211. ret = musb_read_fifosize(musb, hw_ep, epnum);
  1212. if (ret < 0)
  1213. break;
  1214. /* FIXME set up hw_ep->{rx,tx}_double_buffered */
  1215. /* pick an RX/TX endpoint for bulk */
  1216. if (hw_ep->max_packet_sz_tx < 512
  1217. || hw_ep->max_packet_sz_rx < 512)
  1218. continue;
  1219. /* REVISIT: this algorithm is lazy, we should at least
  1220. * try to pick a double buffered endpoint.
  1221. */
  1222. if (musb->bulk_ep)
  1223. continue;
  1224. musb->bulk_ep = hw_ep;
  1225. }
  1226. if (!musb->bulk_ep) {
  1227. pr_debug("%s: missing bulk\n", musb_driver_name);
  1228. return -EINVAL;
  1229. }
  1230. return 0;
  1231. }
  1232. enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
  1233. /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
  1234. * configure endpoints, or take their config from silicon
  1235. */
  1236. static int __devinit musb_core_init(u16 musb_type, struct musb *musb)
  1237. {
  1238. u8 reg;
  1239. char *type;
  1240. char aInfo[90], aRevision[32], aDate[12];
  1241. void __iomem *mbase = musb->mregs;
  1242. int status = 0;
  1243. int i;
  1244. /* log core options (read using indexed model) */
  1245. reg = musb_read_configdata(mbase);
  1246. strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
  1247. if (reg & MUSB_CONFIGDATA_DYNFIFO) {
  1248. strcat(aInfo, ", dyn FIFOs");
  1249. musb->dyn_fifo = true;
  1250. }
  1251. #ifndef CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
  1252. if (reg & MUSB_CONFIGDATA_MPRXE) {
  1253. strcat(aInfo, ", bulk combine");
  1254. musb->bulk_combine = true;
  1255. }
  1256. if (reg & MUSB_CONFIGDATA_MPTXE) {
  1257. strcat(aInfo, ", bulk split");
  1258. musb->bulk_split = true;
  1259. }
  1260. #else
  1261. musb->bulk_combine = false;
  1262. musb->bulk_split = false;
  1263. #endif
  1264. if (reg & MUSB_CONFIGDATA_HBRXE) {
  1265. strcat(aInfo, ", HB-ISO Rx");
  1266. musb->hb_iso_rx = true;
  1267. }
  1268. if (reg & MUSB_CONFIGDATA_HBTXE) {
  1269. strcat(aInfo, ", HB-ISO Tx");
  1270. musb->hb_iso_tx = true;
  1271. }
  1272. if (reg & MUSB_CONFIGDATA_SOFTCONE)
  1273. strcat(aInfo, ", SoftConn");
  1274. pr_debug("%s:ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo);
  1275. aDate[0] = 0;
  1276. if (MUSB_CONTROLLER_MHDRC == musb_type) {
  1277. musb->is_multipoint = 1;
  1278. type = "M";
  1279. } else {
  1280. musb->is_multipoint = 0;
  1281. type = "";
  1282. #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
  1283. printk(KERN_ERR
  1284. "%s: kernel must blacklist external hubs\n",
  1285. musb_driver_name);
  1286. #endif
  1287. }
  1288. /* log release info */
  1289. musb->hwvers = musb_read_hwvers(mbase);
  1290. snprintf(aRevision, 32, "%d.%d%s", MUSB_HWVERS_MAJOR(musb->hwvers),
  1291. MUSB_HWVERS_MINOR(musb->hwvers),
  1292. (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
  1293. pr_debug("%s: %sHDRC RTL version %s %s\n", musb_driver_name, type,
  1294. aRevision, aDate);
  1295. /* configure ep0 */
  1296. musb_configure_ep0(musb);
  1297. /* discover endpoint configuration */
  1298. musb->nr_endpoints = 1;
  1299. musb->epmask = 1;
  1300. if (musb->dyn_fifo)
  1301. status = ep_config_from_table(musb);
  1302. else
  1303. status = ep_config_from_hw(musb);
  1304. if (status < 0)
  1305. return status;
  1306. /* finish init, and print endpoint config */
  1307. for (i = 0; i < musb->nr_endpoints; i++) {
  1308. struct musb_hw_ep *hw_ep = musb->endpoints + i;
  1309. hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
  1310. #if defined(CONFIG_USB_MUSB_TUSB6010) || defined (CONFIG_USB_MUSB_TUSB6010_MODULE)
  1311. hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
  1312. hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
  1313. hw_ep->fifo_sync_va =
  1314. musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
  1315. if (i == 0)
  1316. hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
  1317. else
  1318. hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
  1319. #endif
  1320. hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
  1321. hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
  1322. hw_ep->rx_reinit = 1;
  1323. hw_ep->tx_reinit = 1;
  1324. if (hw_ep->max_packet_sz_tx) {
  1325. dev_dbg(musb->controller,
  1326. "%s: hw_ep %d%s, %smax %d\n",
  1327. musb_driver_name, i,
  1328. hw_ep->is_shared_fifo ? "shared" : "tx",
  1329. hw_ep->tx_double_buffered
  1330. ? "doublebuffer, " : "",
  1331. hw_ep->max_packet_sz_tx);
  1332. }
  1333. if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
  1334. dev_dbg(musb->controller,
  1335. "%s: hw_ep %d%s, %smax %d\n",
  1336. musb_driver_name, i,
  1337. "rx",
  1338. hw_ep->rx_double_buffered
  1339. ? "doublebuffer, " : "",
  1340. hw_ep->max_packet_sz_rx);
  1341. }
  1342. if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
  1343. dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
  1344. }
  1345. return 0;
  1346. }
  1347. /*-------------------------------------------------------------------------*/
  1348. #if defined(CONFIG_SOC_OMAP2430) || defined(CONFIG_SOC_OMAP3430) || \
  1349. defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_U8500)
  1350. static irqreturn_t generic_interrupt(int irq, void *__hci)
  1351. {
  1352. unsigned long flags;
  1353. irqreturn_t retval = IRQ_NONE;
  1354. struct musb *musb = __hci;
  1355. spin_lock_irqsave(&musb->lock, flags);
  1356. musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
  1357. musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
  1358. musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
  1359. if (musb->int_usb || musb->int_tx || musb->int_rx)
  1360. retval = musb_interrupt(musb);
  1361. spin_unlock_irqrestore(&musb->lock, flags);
  1362. return retval;
  1363. }
  1364. #else
  1365. #define generic_interrupt NULL
  1366. #endif
  1367. /*
  1368. * handle all the irqs defined by the HDRC core. for now we expect: other
  1369. * irq sources (phy, dma, etc) will be handled first, musb->int_* values
  1370. * will be assigned, and the irq will already have been acked.
  1371. *
  1372. * called in irq context with spinlock held, irqs blocked
  1373. */
  1374. irqreturn_t musb_interrupt(struct musb *musb)
  1375. {
  1376. irqreturn_t retval = IRQ_NONE;
  1377. u8 devctl, power;
  1378. int ep_num;
  1379. u32 reg;
  1380. devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  1381. power = musb_readb(musb->mregs, MUSB_POWER);
  1382. dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
  1383. (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
  1384. musb->int_usb, musb->int_tx, musb->int_rx);
  1385. /* the core can interrupt us for multiple reasons; docs have
  1386. * a generic interrupt flowchart to follow
  1387. */
  1388. if (musb->int_usb)
  1389. retval |= musb_stage0_irq(musb, musb->int_usb,
  1390. devctl, power);
  1391. /* "stage 1" is handling endpoint irqs */
  1392. /* handle endpoint 0 first */
  1393. if (musb->int_tx & 1) {
  1394. if (devctl & MUSB_DEVCTL_HM) {
  1395. if (is_host_capable())
  1396. retval |= musb_h_ep0_irq(musb);
  1397. } else {
  1398. if (is_peripheral_capable())
  1399. retval |= musb_g_ep0_irq(musb);
  1400. }
  1401. }
  1402. /* RX on endpoints 1-15 */
  1403. reg = musb->int_rx >> 1;
  1404. ep_num = 1;
  1405. while (reg) {
  1406. if (reg & 1) {
  1407. /* musb_ep_select(musb->mregs, ep_num); */
  1408. /* REVISIT just retval = ep->rx_irq(...) */
  1409. retval = IRQ_HANDLED;
  1410. if (devctl & MUSB_DEVCTL_HM) {
  1411. if (is_host_capable())
  1412. musb_host_rx(musb, ep_num);
  1413. } else {
  1414. if (is_peripheral_capable())
  1415. musb_g_rx(musb, ep_num);
  1416. }
  1417. }
  1418. reg >>= 1;
  1419. ep_num++;
  1420. }
  1421. /* TX on endpoints 1-15 */
  1422. reg = musb->int_tx >> 1;
  1423. ep_num = 1;
  1424. while (reg) {
  1425. if (reg & 1) {
  1426. /* musb_ep_select(musb->mregs, ep_num); */
  1427. /* REVISIT just retval |= ep->tx_irq(...) */
  1428. retval = IRQ_HANDLED;
  1429. if (devctl & MUSB_DEVCTL_HM) {
  1430. if (is_host_capable())
  1431. musb_host_tx(musb, ep_num);
  1432. } else {
  1433. if (is_peripheral_capable())
  1434. musb_g_tx(musb, ep_num);
  1435. }
  1436. }
  1437. reg >>= 1;
  1438. ep_num++;
  1439. }
  1440. return retval;
  1441. }
  1442. EXPORT_SYMBOL_GPL(musb_interrupt);
  1443. #ifndef CONFIG_MUSB_PIO_ONLY
  1444. static bool __devinitdata use_dma = 1;
  1445. /* "modprobe ... use_dma=0" etc */
  1446. module_param(use_dma, bool, 0);
  1447. MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
  1448. void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
  1449. {
  1450. u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  1451. /* called with controller lock already held */
  1452. if (!epnum) {
  1453. #ifndef CONFIG_USB_TUSB_OMAP_DMA
  1454. if (!is_cppi_enabled()) {
  1455. /* endpoint 0 */
  1456. if (devctl & MUSB_DEVCTL_HM)
  1457. musb_h_ep0_irq(musb);
  1458. else
  1459. musb_g_ep0_irq(musb);
  1460. }
  1461. #endif
  1462. } else {
  1463. /* endpoints 1..15 */
  1464. if (transmit) {
  1465. if (devctl & MUSB_DEVCTL_HM) {
  1466. if (is_host_capable())
  1467. musb_host_tx(musb, epnum);
  1468. } else {
  1469. if (is_peripheral_capable())
  1470. musb_g_tx(musb, epnum);
  1471. }
  1472. } else {
  1473. /* receive */
  1474. if (devctl & MUSB_DEVCTL_HM) {
  1475. if (is_host_capable())
  1476. musb_host_rx(musb, epnum);
  1477. } else {
  1478. if (is_peripheral_capable())
  1479. musb_g_rx(musb, epnum);
  1480. }
  1481. }
  1482. }
  1483. }
  1484. EXPORT_SYMBOL_GPL(musb_dma_completion);
  1485. #else
  1486. #define use_dma 0
  1487. #endif
  1488. /*-------------------------------------------------------------------------*/
  1489. #ifdef CONFIG_SYSFS
  1490. static ssize_t
  1491. musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
  1492. {
  1493. struct musb *musb = dev_to_musb(dev);
  1494. unsigned long flags;
  1495. int ret = -EINVAL;
  1496. spin_lock_irqsave(&musb->lock, flags);
  1497. ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state));
  1498. spin_unlock_irqrestore(&musb->lock, flags);
  1499. return ret;
  1500. }
  1501. static ssize_t
  1502. musb_mode_store(struct device *dev, struct device_attribute *attr,
  1503. const char *buf, size_t n)
  1504. {
  1505. struct musb *musb = dev_to_musb(dev);
  1506. unsigned long flags;
  1507. int status;
  1508. spin_lock_irqsave(&musb->lock, flags);
  1509. if (sysfs_streq(buf, "host"))
  1510. status = musb_platform_set_mode(musb, MUSB_HOST);
  1511. else if (sysfs_streq(buf, "peripheral"))
  1512. status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
  1513. else if (sysfs_streq(buf, "otg"))
  1514. status = musb_platform_set_mode(musb, MUSB_OTG);
  1515. else
  1516. status = -EINVAL;
  1517. spin_unlock_irqrestore(&musb->lock, flags);
  1518. return (status == 0) ? n : status;
  1519. }
  1520. static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
  1521. static ssize_t
  1522. musb_vbus_store(struct device *dev, struct device_attribute *attr,
  1523. const char *buf, size_t n)
  1524. {
  1525. struct musb *musb = dev_to_musb(dev);
  1526. unsigned long flags;
  1527. unsigned long val;
  1528. if (sscanf(buf, "%lu", &val) < 1) {
  1529. dev_err(dev, "Invalid VBUS timeout ms value\n");
  1530. return -EINVAL;
  1531. }
  1532. spin_lock_irqsave(&musb->lock, flags);
  1533. /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
  1534. musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
  1535. if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
  1536. musb->is_active = 0;
  1537. musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
  1538. spin_unlock_irqrestore(&musb->lock, flags);
  1539. return n;
  1540. }
  1541. static ssize_t
  1542. musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
  1543. {
  1544. struct musb *musb = dev_to_musb(dev);
  1545. unsigned long flags;
  1546. unsigned long val;
  1547. int vbus;
  1548. spin_lock_irqsave(&musb->lock, flags);
  1549. val = musb->a_wait_bcon;
  1550. /* FIXME get_vbus_status() is normally #defined as false...
  1551. * and is effectively TUSB-specific.
  1552. */
  1553. vbus = musb_platform_get_vbus_status(musb);
  1554. spin_unlock_irqrestore(&musb->lock, flags);
  1555. return sprintf(buf, "Vbus %s, timeout %lu msec\n",
  1556. vbus ? "on" : "off", val);
  1557. }
  1558. static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
  1559. /* Gadget drivers can't know that a host is connected so they might want
  1560. * to start SRP, but users can. This allows userspace to trigger SRP.
  1561. */
  1562. static ssize_t
  1563. musb_srp_store(struct device *dev, struct device_attribute *attr,
  1564. const char *buf, size_t n)
  1565. {
  1566. struct musb *musb = dev_to_musb(dev);
  1567. unsigned short srp;
  1568. if (sscanf(buf, "%hu", &srp) != 1
  1569. || (srp != 1)) {
  1570. dev_err(dev, "SRP: Value must be 1\n");
  1571. return -EINVAL;
  1572. }
  1573. if (srp == 1)
  1574. musb_g_wakeup(musb);
  1575. return n;
  1576. }
  1577. static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
  1578. static struct attribute *musb_attributes[] = {
  1579. &dev_attr_mode.attr,
  1580. &dev_attr_vbus.attr,
  1581. &dev_attr_srp.attr,
  1582. NULL
  1583. };
  1584. static const struct attribute_group musb_attr_group = {
  1585. .attrs = musb_attributes,
  1586. };
  1587. #endif /* sysfs */
  1588. #ifndef __UBOOT__
  1589. /* Only used to provide driver mode change events */
  1590. static void musb_irq_work(struct work_struct *data)
  1591. {
  1592. struct musb *musb = container_of(data, struct musb, irq_work);
  1593. static int old_state;
  1594. if (musb->xceiv->state != old_state) {
  1595. old_state = musb->xceiv->state;
  1596. sysfs_notify(&musb->controller->kobj, NULL, "mode");
  1597. }
  1598. }
  1599. #endif
  1600. /* --------------------------------------------------------------------------
  1601. * Init support
  1602. */
  1603. static struct musb *__devinit
  1604. allocate_instance(struct device *dev,
  1605. struct musb_hdrc_config *config, void __iomem *mbase)
  1606. {
  1607. struct musb *musb;
  1608. struct musb_hw_ep *ep;
  1609. int epnum;
  1610. #ifndef __UBOOT__
  1611. struct usb_hcd *hcd;
  1612. hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
  1613. if (!hcd)
  1614. return NULL;
  1615. /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
  1616. musb = hcd_to_musb(hcd);
  1617. #else
  1618. musb = calloc(1, sizeof(*musb));
  1619. if (!musb)
  1620. return NULL;
  1621. #endif
  1622. INIT_LIST_HEAD(&musb->control);
  1623. INIT_LIST_HEAD(&musb->in_bulk);
  1624. INIT_LIST_HEAD(&musb->out_bulk);
  1625. #ifndef __UBOOT__
  1626. hcd->uses_new_polling = 1;
  1627. hcd->has_tt = 1;
  1628. #endif
  1629. musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
  1630. musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
  1631. dev_set_drvdata(dev, musb);
  1632. musb->mregs = mbase;
  1633. musb->ctrl_base = mbase;
  1634. musb->nIrq = -ENODEV;
  1635. musb->config = config;
  1636. BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
  1637. for (epnum = 0, ep = musb->endpoints;
  1638. epnum < musb->config->num_eps;
  1639. epnum++, ep++) {
  1640. ep->musb = musb;
  1641. ep->epnum = epnum;
  1642. }
  1643. musb->controller = dev;
  1644. return musb;
  1645. }
  1646. static void musb_free(struct musb *musb)
  1647. {
  1648. /* this has multiple entry modes. it handles fault cleanup after
  1649. * probe(), where things may be partially set up, as well as rmmod
  1650. * cleanup after everything's been de-activated.
  1651. */
  1652. #ifdef CONFIG_SYSFS
  1653. sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
  1654. #endif
  1655. if (musb->nIrq >= 0) {
  1656. if (musb->irq_wake)
  1657. disable_irq_wake(musb->nIrq);
  1658. free_irq(musb->nIrq, musb);
  1659. }
  1660. if (is_dma_capable() && musb->dma_controller) {
  1661. struct dma_controller *c = musb->dma_controller;
  1662. (void) c->stop(c);
  1663. dma_controller_destroy(c);
  1664. }
  1665. kfree(musb);
  1666. }
  1667. /*
  1668. * Perform generic per-controller initialization.
  1669. *
  1670. * @pDevice: the controller (already clocked, etc)
  1671. * @nIrq: irq
  1672. * @mregs: virtual address of controller registers,
  1673. * not yet corrected for platform-specific offsets
  1674. */
  1675. #ifndef __UBOOT__
  1676. static int __devinit
  1677. musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
  1678. #else
  1679. struct musb *
  1680. musb_init_controller(struct musb_hdrc_platform_data *plat, struct device *dev,
  1681. void *ctrl)
  1682. #endif
  1683. {
  1684. int status;
  1685. struct musb *musb;
  1686. #ifndef __UBOOT__
  1687. struct musb_hdrc_platform_data *plat = dev->platform_data;
  1688. #else
  1689. int nIrq = 0;
  1690. #endif
  1691. /* The driver might handle more features than the board; OK.
  1692. * Fail when the board needs a feature that's not enabled.
  1693. */
  1694. if (!plat) {
  1695. dev_dbg(dev, "no platform_data?\n");
  1696. status = -ENODEV;
  1697. goto fail0;
  1698. }
  1699. /* allocate */
  1700. musb = allocate_instance(dev, plat->config, ctrl);
  1701. if (!musb) {
  1702. status = -ENOMEM;
  1703. goto fail0;
  1704. }
  1705. pm_runtime_use_autosuspend(musb->controller);
  1706. pm_runtime_set_autosuspend_delay(musb->controller, 200);
  1707. pm_runtime_enable(musb->controller);
  1708. spin_lock_init(&musb->lock);
  1709. musb->board_mode = plat->mode;
  1710. musb->board_set_power = plat->set_power;
  1711. musb->min_power = plat->min_power;
  1712. musb->ops = plat->platform_ops;
  1713. /* The musb_platform_init() call:
  1714. * - adjusts musb->mregs and musb->isr if needed,
  1715. * - may initialize an integrated tranceiver
  1716. * - initializes musb->xceiv, usually by otg_get_phy()
  1717. * - stops powering VBUS
  1718. *
  1719. * There are various transceiver configurations. Blackfin,
  1720. * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
  1721. * external/discrete ones in various flavors (twl4030 family,
  1722. * isp1504, non-OTG, etc) mostly hooking up through ULPI.
  1723. */
  1724. musb->isr = generic_interrupt;
  1725. status = musb_platform_init(musb);
  1726. if (status < 0)
  1727. goto fail1;
  1728. if (!musb->isr) {
  1729. status = -ENODEV;
  1730. goto fail2;
  1731. }
  1732. #ifndef __UBOOT__
  1733. if (!musb->xceiv->io_ops) {
  1734. musb->xceiv->io_dev = musb->controller;
  1735. musb->xceiv->io_priv = musb->mregs;
  1736. musb->xceiv->io_ops = &musb_ulpi_access;
  1737. }
  1738. #endif
  1739. pm_runtime_get_sync(musb->controller);
  1740. #ifndef CONFIG_MUSB_PIO_ONLY
  1741. if (use_dma && dev->dma_mask) {
  1742. struct dma_controller *c;
  1743. c = dma_controller_create(musb, musb->mregs);
  1744. musb->dma_controller = c;
  1745. if (c)
  1746. (void) c->start(c);
  1747. }
  1748. #endif
  1749. #ifndef __UBOOT__
  1750. /* ideally this would be abstracted in platform setup */
  1751. if (!is_dma_capable() || !musb->dma_controller)
  1752. dev->dma_mask = NULL;
  1753. #endif
  1754. /* be sure interrupts are disabled before connecting ISR */
  1755. musb_platform_disable(musb);
  1756. musb_generic_disable(musb);
  1757. /* setup musb parts of the core (especially endpoints) */
  1758. status = musb_core_init(plat->config->multipoint
  1759. ? MUSB_CONTROLLER_MHDRC
  1760. : MUSB_CONTROLLER_HDRC, musb);
  1761. if (status < 0)
  1762. goto fail3;
  1763. setup_timer(&musb->otg_timer, musb_otg_timer_func, (unsigned long) musb);
  1764. /* Init IRQ workqueue before request_irq */
  1765. INIT_WORK(&musb->irq_work, musb_irq_work);
  1766. /* attach to the IRQ */
  1767. if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
  1768. dev_err(dev, "request_irq %d failed!\n", nIrq);
  1769. status = -ENODEV;
  1770. goto fail3;
  1771. }
  1772. musb->nIrq = nIrq;
  1773. /* FIXME this handles wakeup irqs wrong */
  1774. if (enable_irq_wake(nIrq) == 0) {
  1775. musb->irq_wake = 1;
  1776. device_init_wakeup(dev, 1);
  1777. } else {
  1778. musb->irq_wake = 0;
  1779. }
  1780. #ifndef __UBOOT__
  1781. /* host side needs more setup */
  1782. if (is_host_enabled(musb)) {
  1783. struct usb_hcd *hcd = musb_to_hcd(musb);
  1784. otg_set_host(musb->xceiv->otg, &hcd->self);
  1785. if (is_otg_enabled(musb))
  1786. hcd->self.otg_port = 1;
  1787. musb->xceiv->otg->host = &hcd->self;
  1788. hcd->power_budget = 2 * (plat->power ? : 250);
  1789. /* program PHY to use external vBus if required */
  1790. if (plat->extvbus) {
  1791. u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
  1792. busctl |= MUSB_ULPI_USE_EXTVBUS;
  1793. musb_write_ulpi_buscontrol(musb->mregs, busctl);
  1794. }
  1795. }
  1796. #endif
  1797. /* For the host-only role, we can activate right away.
  1798. * (We expect the ID pin to be forcibly grounded!!)
  1799. * Otherwise, wait till the gadget driver hooks up.
  1800. */
  1801. if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
  1802. struct usb_hcd *hcd = musb_to_hcd(musb);
  1803. MUSB_HST_MODE(musb);
  1804. #ifndef __UBOOT__
  1805. musb->xceiv->otg->default_a = 1;
  1806. musb->xceiv->state = OTG_STATE_A_IDLE;
  1807. status = usb_add_hcd(musb_to_hcd(musb), 0, 0);
  1808. hcd->self.uses_pio_for_control = 1;
  1809. dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n",
  1810. "HOST", status,
  1811. musb_readb(musb->mregs, MUSB_DEVCTL),
  1812. (musb_readb(musb->mregs, MUSB_DEVCTL)
  1813. & MUSB_DEVCTL_BDEVICE
  1814. ? 'B' : 'A'));
  1815. #endif
  1816. } else /* peripheral is enabled */ {
  1817. MUSB_DEV_MODE(musb);
  1818. #ifndef __UBOOT__
  1819. musb->xceiv->otg->default_a = 0;
  1820. musb->xceiv->state = OTG_STATE_B_IDLE;
  1821. #endif
  1822. if (is_peripheral_capable())
  1823. status = musb_gadget_setup(musb);
  1824. #ifndef __UBOOT__
  1825. dev_dbg(musb->controller, "%s mode, status %d, dev%02x\n",
  1826. is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
  1827. status,
  1828. musb_readb(musb->mregs, MUSB_DEVCTL));
  1829. #endif
  1830. }
  1831. if (status < 0)
  1832. goto fail3;
  1833. status = musb_init_debugfs(musb);
  1834. if (status < 0)
  1835. goto fail4;
  1836. #ifdef CONFIG_SYSFS
  1837. status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
  1838. if (status)
  1839. goto fail5;
  1840. #endif
  1841. pm_runtime_put(musb->controller);
  1842. pr_debug("USB %s mode controller at %p using %s, IRQ %d\n",
  1843. ({char *s;
  1844. switch (musb->board_mode) {
  1845. case MUSB_HOST: s = "Host"; break;
  1846. case MUSB_PERIPHERAL: s = "Peripheral"; break;
  1847. default: s = "OTG"; break;
  1848. }; s; }),
  1849. ctrl,
  1850. (is_dma_capable() && musb->dma_controller)
  1851. ? "DMA" : "PIO",
  1852. musb->nIrq);
  1853. #ifndef __UBOOT__
  1854. return 0;
  1855. #else
  1856. return status == 0 ? musb : NULL;
  1857. #endif
  1858. fail5:
  1859. musb_exit_debugfs(musb);
  1860. fail4:
  1861. #ifndef __UBOOT__
  1862. if (!is_otg_enabled(musb) && is_host_enabled(musb))
  1863. usb_remove_hcd(musb_to_hcd(musb));
  1864. else
  1865. #endif
  1866. musb_gadget_cleanup(musb);
  1867. fail3:
  1868. pm_runtime_put_sync(musb->controller);
  1869. fail2:
  1870. if (musb->irq_wake)
  1871. device_init_wakeup(dev, 0);
  1872. musb_platform_exit(musb);
  1873. fail1:
  1874. dev_err(musb->controller,
  1875. "musb_init_controller failed with status %d\n", status);
  1876. musb_free(musb);
  1877. fail0:
  1878. #ifndef __UBOOT__
  1879. return status;
  1880. #else
  1881. return status == 0 ? musb : NULL;
  1882. #endif
  1883. }
  1884. /*-------------------------------------------------------------------------*/
  1885. /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
  1886. * bridge to a platform device; this driver then suffices.
  1887. */
  1888. #ifndef CONFIG_MUSB_PIO_ONLY
  1889. static u64 *orig_dma_mask;
  1890. #endif
  1891. #ifndef __UBOOT__
  1892. static int __devinit musb_probe(struct platform_device *pdev)
  1893. {
  1894. struct device *dev = &pdev->dev;
  1895. int irq = platform_get_irq_byname(pdev, "mc");
  1896. int status;
  1897. struct resource *iomem;
  1898. void __iomem *base;
  1899. iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1900. if (!iomem || irq <= 0)
  1901. return -ENODEV;
  1902. base = ioremap(iomem->start, resource_size(iomem));
  1903. if (!base) {
  1904. dev_err(dev, "ioremap failed\n");
  1905. return -ENOMEM;
  1906. }
  1907. #ifndef CONFIG_MUSB_PIO_ONLY
  1908. /* clobbered by use_dma=n */
  1909. orig_dma_mask = dev->dma_mask;
  1910. #endif
  1911. status = musb_init_controller(dev, irq, base);
  1912. if (status < 0)
  1913. iounmap(base);
  1914. return status;
  1915. }
  1916. static int __devexit musb_remove(struct platform_device *pdev)
  1917. {
  1918. struct musb *musb = dev_to_musb(&pdev->dev);
  1919. void __iomem *ctrl_base = musb->ctrl_base;
  1920. /* this gets called on rmmod.
  1921. * - Host mode: host may still be active
  1922. * - Peripheral mode: peripheral is deactivated (or never-activated)
  1923. * - OTG mode: both roles are deactivated (or never-activated)
  1924. */
  1925. musb_exit_debugfs(musb);
  1926. musb_shutdown(pdev);
  1927. musb_free(musb);
  1928. iounmap(ctrl_base);
  1929. device_init_wakeup(&pdev->dev, 0);
  1930. #ifndef CONFIG_MUSB_PIO_ONLY
  1931. pdev->dev.dma_mask = orig_dma_mask;
  1932. #endif
  1933. return 0;
  1934. }
  1935. #ifdef CONFIG_PM
  1936. static void musb_save_context(struct musb *musb)
  1937. {
  1938. int i;
  1939. void __iomem *musb_base = musb->mregs;
  1940. void __iomem *epio;
  1941. if (is_host_enabled(musb)) {
  1942. musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
  1943. musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
  1944. musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
  1945. }
  1946. musb->context.power = musb_readb(musb_base, MUSB_POWER);
  1947. musb->context.intrtxe = musb_readw(musb_base, MUSB_INTRTXE);
  1948. musb->context.intrrxe = musb_readw(musb_base, MUSB_INTRRXE);
  1949. musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
  1950. musb->context.index = musb_readb(musb_base, MUSB_INDEX);
  1951. musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
  1952. for (i = 0; i < musb->config->num_eps; ++i) {
  1953. struct musb_hw_ep *hw_ep;
  1954. hw_ep = &musb->endpoints[i];
  1955. if (!hw_ep)
  1956. continue;
  1957. epio = hw_ep->regs;
  1958. if (!epio)
  1959. continue;
  1960. musb_writeb(musb_base, MUSB_INDEX, i);
  1961. musb->context.index_regs[i].txmaxp =
  1962. musb_readw(epio, MUSB_TXMAXP);
  1963. musb->context.index_regs[i].txcsr =
  1964. musb_readw(epio, MUSB_TXCSR);
  1965. musb->context.index_regs[i].rxmaxp =
  1966. musb_readw(epio, MUSB_RXMAXP);
  1967. musb->context.index_regs[i].rxcsr =
  1968. musb_readw(epio, MUSB_RXCSR);
  1969. if (musb->dyn_fifo) {
  1970. musb->context.index_regs[i].txfifoadd =
  1971. musb_read_txfifoadd(musb_base);
  1972. musb->context.index_regs[i].rxfifoadd =
  1973. musb_read_rxfifoadd(musb_base);
  1974. musb->context.index_regs[i].txfifosz =
  1975. musb_read_txfifosz(musb_base);
  1976. musb->context.index_regs[i].rxfifosz =
  1977. musb_read_rxfifosz(musb_base);
  1978. }
  1979. if (is_host_enabled(musb)) {
  1980. musb->context.index_regs[i].txtype =
  1981. musb_readb(epio, MUSB_TXTYPE);
  1982. musb->context.index_regs[i].txinterval =
  1983. musb_readb(epio, MUSB_TXINTERVAL);
  1984. musb->context.index_regs[i].rxtype =
  1985. musb_readb(epio, MUSB_RXTYPE);
  1986. musb->context.index_regs[i].rxinterval =
  1987. musb_readb(epio, MUSB_RXINTERVAL);
  1988. musb->context.index_regs[i].txfunaddr =
  1989. musb_read_txfunaddr(musb_base, i);
  1990. musb->context.index_regs[i].txhubaddr =
  1991. musb_read_txhubaddr(musb_base, i);
  1992. musb->context.index_regs[i].txhubport =
  1993. musb_read_txhubport(musb_base, i);
  1994. musb->context.index_regs[i].rxfunaddr =
  1995. musb_read_rxfunaddr(musb_base, i);
  1996. musb->context.index_regs[i].rxhubaddr =
  1997. musb_read_rxhubaddr(musb_base, i);
  1998. musb->context.index_regs[i].rxhubport =
  1999. musb_read_rxhubport(musb_base, i);
  2000. }
  2001. }
  2002. }
  2003. static void musb_restore_context(struct musb *musb)
  2004. {
  2005. int i;
  2006. void __iomem *musb_base = musb->mregs;
  2007. void __iomem *ep_target_regs;
  2008. void __iomem *epio;
  2009. if (is_host_enabled(musb)) {
  2010. musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
  2011. musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
  2012. musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
  2013. }
  2014. musb_writeb(musb_base, MUSB_POWER, musb->context.power);
  2015. musb_writew(musb_base, MUSB_INTRTXE, musb->context.intrtxe);
  2016. musb_writew(musb_base, MUSB_INTRRXE, musb->context.intrrxe);
  2017. musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
  2018. musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
  2019. for (i = 0; i < musb->config->num_eps; ++i) {
  2020. struct musb_hw_ep *hw_ep;
  2021. hw_ep = &musb->endpoints[i];
  2022. if (!hw_ep)
  2023. continue;
  2024. epio = hw_ep->regs;
  2025. if (!epio)
  2026. continue;
  2027. musb_writeb(musb_base, MUSB_INDEX, i);
  2028. musb_writew(epio, MUSB_TXMAXP,
  2029. musb->context.index_regs[i].txmaxp);
  2030. musb_writew(epio, MUSB_TXCSR,
  2031. musb->context.index_regs[i].txcsr);
  2032. musb_writew(epio, MUSB_RXMAXP,
  2033. musb->context.index_regs[i].rxmaxp);
  2034. musb_writew(epio, MUSB_RXCSR,
  2035. musb->context.index_regs[i].rxcsr);
  2036. if (musb->dyn_fifo) {
  2037. musb_write_txfifosz(musb_base,
  2038. musb->context.index_regs[i].txfifosz);
  2039. musb_write_rxfifosz(musb_base,
  2040. musb->context.index_regs[i].rxfifosz);
  2041. musb_write_txfifoadd(musb_base,
  2042. musb->context.index_regs[i].txfifoadd);
  2043. musb_write_rxfifoadd(musb_base,
  2044. musb->context.index_regs[i].rxfifoadd);
  2045. }
  2046. if (is_host_enabled(musb)) {
  2047. musb_writeb(epio, MUSB_TXTYPE,
  2048. musb->context.index_regs[i].txtype);
  2049. musb_writeb(epio, MUSB_TXINTERVAL,
  2050. musb->context.index_regs[i].txinterval);
  2051. musb_writeb(epio, MUSB_RXTYPE,
  2052. musb->context.index_regs[i].rxtype);
  2053. musb_writeb(epio, MUSB_RXINTERVAL,
  2054. musb->context.index_regs[i].rxinterval);
  2055. musb_write_txfunaddr(musb_base, i,
  2056. musb->context.index_regs[i].txfunaddr);
  2057. musb_write_txhubaddr(musb_base, i,
  2058. musb->context.index_regs[i].txhubaddr);
  2059. musb_write_txhubport(musb_base, i,
  2060. musb->context.index_regs[i].txhubport);
  2061. ep_target_regs =
  2062. musb_read_target_reg_base(i, musb_base);
  2063. musb_write_rxfunaddr(ep_target_regs,
  2064. musb->context.index_regs[i].rxfunaddr);
  2065. musb_write_rxhubaddr(ep_target_regs,
  2066. musb->context.index_regs[i].rxhubaddr);
  2067. musb_write_rxhubport(ep_target_regs,
  2068. musb->context.index_regs[i].rxhubport);
  2069. }
  2070. }
  2071. musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
  2072. }
  2073. static int musb_suspend(struct device *dev)
  2074. {
  2075. struct musb *musb = dev_to_musb(dev);
  2076. unsigned long flags;
  2077. spin_lock_irqsave(&musb->lock, flags);
  2078. if (is_peripheral_active(musb)) {
  2079. /* FIXME force disconnect unless we know USB will wake
  2080. * the system up quickly enough to respond ...
  2081. */
  2082. } else if (is_host_active(musb)) {
  2083. /* we know all the children are suspended; sometimes
  2084. * they will even be wakeup-enabled.
  2085. */
  2086. }
  2087. spin_unlock_irqrestore(&musb->lock, flags);
  2088. return 0;
  2089. }
  2090. static int musb_resume_noirq(struct device *dev)
  2091. {
  2092. /* for static cmos like DaVinci, register values were preserved
  2093. * unless for some reason the whole soc powered down or the USB
  2094. * module got reset through the PSC (vs just being disabled).
  2095. */
  2096. return 0;
  2097. }
  2098. static int musb_runtime_suspend(struct device *dev)
  2099. {
  2100. struct musb *musb = dev_to_musb(dev);
  2101. musb_save_context(musb);
  2102. return 0;
  2103. }
  2104. static int musb_runtime_resume(struct device *dev)
  2105. {
  2106. struct musb *musb = dev_to_musb(dev);
  2107. static int first = 1;
  2108. /*
  2109. * When pm_runtime_get_sync called for the first time in driver
  2110. * init, some of the structure is still not initialized which is
  2111. * used in restore function. But clock needs to be
  2112. * enabled before any register access, so
  2113. * pm_runtime_get_sync has to be called.
  2114. * Also context restore without save does not make
  2115. * any sense
  2116. */
  2117. if (!first)
  2118. musb_restore_context(musb);
  2119. first = 0;
  2120. return 0;
  2121. }
  2122. static const struct dev_pm_ops musb_dev_pm_ops = {
  2123. .suspend = musb_suspend,
  2124. .resume_noirq = musb_resume_noirq,
  2125. .runtime_suspend = musb_runtime_suspend,
  2126. .runtime_resume = musb_runtime_resume,
  2127. };
  2128. #define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
  2129. #else
  2130. #define MUSB_DEV_PM_OPS NULL
  2131. #endif
  2132. static struct platform_driver musb_driver = {
  2133. .driver = {
  2134. .name = (char *)musb_driver_name,
  2135. .bus = &platform_bus_type,
  2136. .owner = THIS_MODULE,
  2137. .pm = MUSB_DEV_PM_OPS,
  2138. },
  2139. .probe = musb_probe,
  2140. .remove = __devexit_p(musb_remove),
  2141. .shutdown = musb_shutdown,
  2142. };
  2143. /*-------------------------------------------------------------------------*/
  2144. static int __init musb_init(void)
  2145. {
  2146. if (usb_disabled())
  2147. return 0;
  2148. pr_info("%s: version " MUSB_VERSION ", "
  2149. "?dma?"
  2150. ", "
  2151. "otg (peripheral+host)",
  2152. musb_driver_name);
  2153. return platform_driver_register(&musb_driver);
  2154. }
  2155. module_init(musb_init);
  2156. static void __exit musb_cleanup(void)
  2157. {
  2158. platform_driver_unregister(&musb_driver);
  2159. }
  2160. module_exit(musb_cleanup);
  2161. #endif