bd82x6x.c 2.9 KB

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  1. /*
  2. * Copyright (C) 2014 Google, Inc
  3. *
  4. * SPDX-License-Identifier: GPL-2.0+
  5. */
  6. #include <common.h>
  7. #include <errno.h>
  8. #include <fdtdec.h>
  9. #include <malloc.h>
  10. #include <asm/lapic.h>
  11. #include <asm/pci.h>
  12. #include <asm/arch/bd82x6x.h>
  13. #include <asm/arch/model_206ax.h>
  14. #include <asm/arch/pch.h>
  15. #include <asm/arch/sandybridge.h>
  16. void bd82x6x_pci_init(pci_dev_t dev)
  17. {
  18. u16 reg16;
  19. u8 reg8;
  20. debug("bd82x6x PCI init.\n");
  21. /* Enable Bus Master */
  22. reg16 = pci_read_config16(dev, PCI_COMMAND);
  23. reg16 |= PCI_COMMAND_MASTER;
  24. pci_write_config16(dev, PCI_COMMAND, reg16);
  25. /* This device has no interrupt */
  26. pci_write_config8(dev, INTR, 0xff);
  27. /* disable parity error response and SERR */
  28. reg16 = pci_read_config16(dev, BCTRL);
  29. reg16 &= ~(1 << 0);
  30. reg16 &= ~(1 << 1);
  31. pci_write_config16(dev, BCTRL, reg16);
  32. /* Master Latency Count must be set to 0x04! */
  33. reg8 = pci_read_config8(dev, SMLT);
  34. reg8 &= 0x07;
  35. reg8 |= (0x04 << 3);
  36. pci_write_config8(dev, SMLT, reg8);
  37. /* Will this improve throughput of bus masters? */
  38. pci_write_config8(dev, PCI_MIN_GNT, 0x06);
  39. /* Clear errors in status registers */
  40. reg16 = pci_read_config16(dev, PSTS);
  41. /* reg16 |= 0xf900; */
  42. pci_write_config16(dev, PSTS, reg16);
  43. reg16 = pci_read_config16(dev, SECSTS);
  44. /* reg16 |= 0xf900; */
  45. pci_write_config16(dev, SECSTS, reg16);
  46. }
  47. #define PCI_BRIDGE_UPDATE_COMMAND
  48. void bd82x6x_pci_dev_enable_resources(pci_dev_t dev)
  49. {
  50. uint16_t command;
  51. command = pci_read_config16(dev, PCI_COMMAND);
  52. command |= PCI_COMMAND_IO;
  53. #ifdef PCI_BRIDGE_UPDATE_COMMAND
  54. /*
  55. * If we write to PCI_COMMAND, on some systems this will cause the
  56. * ROM and APICs to become invisible.
  57. */
  58. debug("%x cmd <- %02x\n", dev, command);
  59. pci_write_config16(dev, PCI_COMMAND, command);
  60. #else
  61. printf("%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command);
  62. #endif
  63. }
  64. void bd82x6x_pci_bus_enable_resources(pci_dev_t dev)
  65. {
  66. uint16_t ctrl;
  67. ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
  68. ctrl |= PCI_COMMAND_IO;
  69. ctrl |= PCI_BRIDGE_CTL_VGA;
  70. debug("%x bridge ctrl <- %04x\n", dev, ctrl);
  71. pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
  72. bd82x6x_pci_dev_enable_resources(dev);
  73. }
  74. int bd82x6x_init_pci_devices(void)
  75. {
  76. const void *blob = gd->fdt_blob;
  77. struct pci_controller *hose;
  78. int sata_node;
  79. hose = pci_bus_to_hose(0);
  80. lpc_enable(PCH_LPC_DEV);
  81. lpc_init(hose, PCH_LPC_DEV);
  82. sata_node = fdtdec_next_compatible(blob, 0,
  83. COMPAT_INTEL_PANTHERPOINT_AHCI);
  84. if (sata_node < 0) {
  85. debug("%s: Cannot find SATA node\n", __func__);
  86. return -EINVAL;
  87. }
  88. bd82x6x_sata_init(PCH_SATA_DEV, blob, sata_node);
  89. return 0;
  90. }
  91. int bd82x6x_init(void)
  92. {
  93. const void *blob = gd->fdt_blob;
  94. int sata_node;
  95. sata_node = fdtdec_next_compatible(blob, 0,
  96. COMPAT_INTEL_PANTHERPOINT_AHCI);
  97. if (sata_node < 0) {
  98. debug("%s: Cannot find SATA node\n", __func__);
  99. return -EINVAL;
  100. }
  101. bd82x6x_pci_init(PCH_DEV);
  102. bd82x6x_sata_enable(PCH_SATA_DEV, blob, sata_node);
  103. return 0;
  104. }