fu540_ddr.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * (C) Copyright 2020 SiFive, Inc.
  4. *
  5. * Authors:
  6. * Pragnesh Patel <pragnesh.patel@sifive.com>
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <fdtdec.h>
  11. #include <init.h>
  12. #include <ram.h>
  13. #include <regmap.h>
  14. #include <syscon.h>
  15. #include <asm/io.h>
  16. #include <clk.h>
  17. #include <wait_bit.h>
  18. #include <linux/bitops.h>
  19. #define DENALI_CTL_0 0
  20. #define DENALI_CTL_21 21
  21. #define DENALI_CTL_120 120
  22. #define DENALI_CTL_132 132
  23. #define DENALI_CTL_136 136
  24. #define DENALI_CTL_170 170
  25. #define DENALI_CTL_181 181
  26. #define DENALI_CTL_182 182
  27. #define DENALI_CTL_184 184
  28. #define DENALI_CTL_208 208
  29. #define DENALI_CTL_209 209
  30. #define DENALI_CTL_210 210
  31. #define DENALI_CTL_212 212
  32. #define DENALI_CTL_214 214
  33. #define DENALI_CTL_216 216
  34. #define DENALI_CTL_224 224
  35. #define DENALI_CTL_225 225
  36. #define DENALI_CTL_260 260
  37. #define DENALI_PHY_1152 1152
  38. #define DENALI_PHY_1214 1214
  39. #define DRAM_CLASS_OFFSET 8
  40. #define DRAM_CLASS_DDR4 0xA
  41. #define OPTIMAL_RMODW_EN_OFFSET 0
  42. #define DISABLE_RD_INTERLEAVE_OFFSET 16
  43. #define OUT_OF_RANGE_OFFSET 1
  44. #define MULTIPLE_OUT_OF_RANGE_OFFSET 2
  45. #define PORT_COMMAND_CHANNEL_ERROR_OFFSET 7
  46. #define MC_INIT_COMPLETE_OFFSET 8
  47. #define LEVELING_OPERATION_COMPLETED_OFFSET 22
  48. #define DFI_PHY_WRLELV_MODE_OFFSET 24
  49. #define DFI_PHY_RDLVL_MODE_OFFSET 24
  50. #define DFI_PHY_RDLVL_GATE_MODE_OFFSET 0
  51. #define VREF_EN_OFFSET 24
  52. #define PORT_ADDR_PROTECTION_EN_OFFSET 0
  53. #define AXI0_ADDRESS_RANGE_ENABLE 8
  54. #define AXI0_RANGE_PROT_BITS_0_OFFSET 24
  55. #define RDLVL_EN_OFFSET 16
  56. #define RDLVL_GATE_EN_OFFSET 24
  57. #define WRLVL_EN_OFFSET 0
  58. #define PHY_RX_CAL_DQ0_0_OFFSET 0
  59. #define PHY_RX_CAL_DQ1_0_OFFSET 16
  60. DECLARE_GLOBAL_DATA_PTR;
  61. struct fu540_ddrctl {
  62. volatile u32 denali_ctl[265];
  63. };
  64. struct fu540_ddrphy {
  65. volatile u32 denali_phy[1215];
  66. };
  67. /**
  68. * struct fu540_ddr_info
  69. *
  70. * @dev : pointer for the device
  71. * @info : UCLASS RAM information
  72. * @ctl : DDR controller base address
  73. * @phy : DDR PHY base address
  74. * @ctrl : DDR control base address
  75. * @physical_filter_ctrl : DDR physical filter control base address
  76. */
  77. struct fu540_ddr_info {
  78. struct udevice *dev;
  79. struct ram_info info;
  80. struct fu540_ddrctl *ctl;
  81. struct fu540_ddrphy *phy;
  82. struct clk ddr_clk;
  83. u32 *physical_filter_ctrl;
  84. };
  85. #if defined(CONFIG_SPL_BUILD)
  86. struct fu540_ddr_params {
  87. struct fu540_ddrctl pctl_regs;
  88. struct fu540_ddrphy phy_regs;
  89. };
  90. struct sifive_dmc_plat {
  91. struct fu540_ddr_params ddr_params;
  92. };
  93. /*
  94. * TODO : It can be possible to use common sdram_copy_to_reg() API
  95. * n: Unit bytes
  96. */
  97. static void sdram_copy_to_reg(volatile u32 *dest,
  98. volatile u32 *src, u32 n)
  99. {
  100. int i;
  101. for (i = 0; i < n / sizeof(u32); i++) {
  102. writel(*src, dest);
  103. src++;
  104. dest++;
  105. }
  106. }
  107. static void fu540_ddr_setup_range_protection(volatile u32 *ctl, u64 end_addr)
  108. {
  109. u32 end_addr_16kblocks = ((end_addr >> 14) & 0x7FFFFF) - 1;
  110. writel(0x0, DENALI_CTL_209 + ctl);
  111. writel(end_addr_16kblocks, DENALI_CTL_210 + ctl);
  112. writel(0x0, DENALI_CTL_212 + ctl);
  113. writel(0x0, DENALI_CTL_214 + ctl);
  114. writel(0x0, DENALI_CTL_216 + ctl);
  115. setbits_le32(DENALI_CTL_224 + ctl,
  116. 0x3 << AXI0_RANGE_PROT_BITS_0_OFFSET);
  117. writel(0xFFFFFFFF, DENALI_CTL_225 + ctl);
  118. setbits_le32(DENALI_CTL_208 + ctl, 0x1 << AXI0_ADDRESS_RANGE_ENABLE);
  119. setbits_le32(DENALI_CTL_208 + ctl,
  120. 0x1 << PORT_ADDR_PROTECTION_EN_OFFSET);
  121. }
  122. static void fu540_ddr_start(volatile u32 *ctl, u32 *physical_filter_ctrl,
  123. u64 ddr_end)
  124. {
  125. volatile u64 *filterreg = (volatile u64 *)physical_filter_ctrl;
  126. setbits_le32(DENALI_CTL_0 + ctl, 0x1);
  127. wait_for_bit_le32((void *)ctl + DENALI_CTL_132,
  128. BIT(MC_INIT_COMPLETE_OFFSET), false, 100, false);
  129. /* Disable the BusBlocker in front of the controller AXI slave ports */
  130. filterreg[0] = 0x0f00000000000000UL | (ddr_end >> 2);
  131. }
  132. static void fu540_ddr_check_errata(u32 regbase, u32 updownreg)
  133. {
  134. u64 fails = 0;
  135. u32 dq = 0;
  136. u32 down, up;
  137. u8 failc0, failc1;
  138. u32 phy_rx_cal_dqn_0_offset;
  139. for (u32 bit = 0; bit < 2; bit++) {
  140. if (bit == 0) {
  141. phy_rx_cal_dqn_0_offset =
  142. PHY_RX_CAL_DQ0_0_OFFSET;
  143. } else {
  144. phy_rx_cal_dqn_0_offset =
  145. PHY_RX_CAL_DQ1_0_OFFSET;
  146. }
  147. down = (updownreg >>
  148. phy_rx_cal_dqn_0_offset) & 0x3F;
  149. up = (updownreg >>
  150. (phy_rx_cal_dqn_0_offset + 6)) &
  151. 0x3F;
  152. failc0 = ((down == 0) && (up == 0x3F));
  153. failc1 = ((up == 0) && (down == 0x3F));
  154. /* print error message on failure */
  155. if (failc0 || failc1) {
  156. if (fails == 0)
  157. printf("DDR error in fixing up\n");
  158. fails |= (1 << dq);
  159. char slicelsc = '0';
  160. char slicemsc = '0';
  161. slicelsc += (dq % 10);
  162. slicemsc += (dq / 10);
  163. printf("S ");
  164. printf("%c", slicemsc);
  165. printf("%c", slicelsc);
  166. if (failc0)
  167. printf("U");
  168. else
  169. printf("D");
  170. printf("\n");
  171. }
  172. dq++;
  173. }
  174. }
  175. static u64 fu540_ddr_phy_fixup(volatile u32 *ddrphyreg)
  176. {
  177. u32 slicebase = 0;
  178. /* check errata condition */
  179. for (u32 slice = 0; slice < 8; slice++) {
  180. u32 regbase = slicebase + 34;
  181. for (u32 reg = 0; reg < 4; reg++) {
  182. u32 updownreg = readl(regbase + reg + ddrphyreg);
  183. fu540_ddr_check_errata(regbase, updownreg);
  184. }
  185. slicebase += 128;
  186. }
  187. return(0);
  188. }
  189. static u32 fu540_ddr_get_dram_class(volatile u32 *ctl)
  190. {
  191. u32 reg = readl(DENALI_CTL_0 + ctl);
  192. return ((reg >> DRAM_CLASS_OFFSET) & 0xF);
  193. }
  194. static int fu540_ddr_setup(struct udevice *dev)
  195. {
  196. struct fu540_ddr_info *priv = dev_get_priv(dev);
  197. struct sifive_dmc_plat *plat = dev_get_platdata(dev);
  198. struct fu540_ddr_params *params = &plat->ddr_params;
  199. volatile u32 *denali_ctl = priv->ctl->denali_ctl;
  200. volatile u32 *denali_phy = priv->phy->denali_phy;
  201. const u64 ddr_size = priv->info.size;
  202. const u64 ddr_end = priv->info.base + ddr_size;
  203. int ret, i;
  204. u32 physet;
  205. ret = dev_read_u32_array(dev, "sifive,ddr-params",
  206. (u32 *)&plat->ddr_params,
  207. sizeof(plat->ddr_params) / sizeof(u32));
  208. if (ret) {
  209. printf("%s: Cannot read sifive,ddr-params %d\n",
  210. __func__, ret);
  211. return ret;
  212. }
  213. sdram_copy_to_reg(priv->ctl->denali_ctl,
  214. params->pctl_regs.denali_ctl,
  215. sizeof(struct fu540_ddrctl));
  216. /* phy reset */
  217. for (i = DENALI_PHY_1152; i <= DENALI_PHY_1214; i++) {
  218. physet = params->phy_regs.denali_phy[i];
  219. priv->phy->denali_phy[i] = physet;
  220. }
  221. for (i = 0; i < DENALI_PHY_1152; i++) {
  222. physet = params->phy_regs.denali_phy[i];
  223. priv->phy->denali_phy[i] = physet;
  224. }
  225. /* Disable read interleave DENALI_CTL_120 */
  226. setbits_le32(DENALI_CTL_120 + denali_ctl,
  227. 1 << DISABLE_RD_INTERLEAVE_OFFSET);
  228. /* Disable optimal read/modify/write logic DENALI_CTL_21 */
  229. clrbits_le32(DENALI_CTL_21 + denali_ctl, 1 << OPTIMAL_RMODW_EN_OFFSET);
  230. /* Enable write Leveling DENALI_CTL_170 */
  231. setbits_le32(DENALI_CTL_170 + denali_ctl, (1 << WRLVL_EN_OFFSET)
  232. | (1 << DFI_PHY_WRLELV_MODE_OFFSET));
  233. /* Enable read leveling DENALI_CTL_181 and DENALI_CTL_260 */
  234. setbits_le32(DENALI_CTL_181 + denali_ctl,
  235. 1 << DFI_PHY_RDLVL_MODE_OFFSET);
  236. setbits_le32(DENALI_CTL_260 + denali_ctl, 1 << RDLVL_EN_OFFSET);
  237. /* Enable read leveling gate DENALI_CTL_260 and DENALI_CTL_182 */
  238. setbits_le32(DENALI_CTL_260 + denali_ctl, 1 << RDLVL_GATE_EN_OFFSET);
  239. setbits_le32(DENALI_CTL_182 + denali_ctl,
  240. 1 << DFI_PHY_RDLVL_GATE_MODE_OFFSET);
  241. if (fu540_ddr_get_dram_class(denali_ctl) == DRAM_CLASS_DDR4) {
  242. /* Enable vref training DENALI_CTL_184 */
  243. setbits_le32(DENALI_CTL_184 + denali_ctl, 1 << VREF_EN_OFFSET);
  244. }
  245. /* Mask off leveling completion interrupt DENALI_CTL_136 */
  246. setbits_le32(DENALI_CTL_136 + denali_ctl,
  247. 1 << LEVELING_OPERATION_COMPLETED_OFFSET);
  248. /* Mask off MC init complete interrupt DENALI_CTL_136 */
  249. setbits_le32(DENALI_CTL_136 + denali_ctl, 1 << MC_INIT_COMPLETE_OFFSET);
  250. /* Mask off out of range interrupts DENALI_CTL_136 */
  251. setbits_le32(DENALI_CTL_136 + denali_ctl, (1 << OUT_OF_RANGE_OFFSET)
  252. | (1 << MULTIPLE_OUT_OF_RANGE_OFFSET));
  253. /* set up range protection */
  254. fu540_ddr_setup_range_protection(denali_ctl, priv->info.size);
  255. /* Mask off port command error interrupt DENALI_CTL_136 */
  256. setbits_le32(DENALI_CTL_136 + denali_ctl,
  257. 1 << PORT_COMMAND_CHANNEL_ERROR_OFFSET);
  258. fu540_ddr_start(denali_ctl, priv->physical_filter_ctrl, ddr_end);
  259. fu540_ddr_phy_fixup(denali_phy);
  260. /* check size */
  261. priv->info.size = get_ram_size((long *)priv->info.base,
  262. ddr_size);
  263. debug("%s : %lx\n", __func__, (uintptr_t)priv->info.size);
  264. /* check memory access for all memory */
  265. if (priv->info.size != ddr_size) {
  266. printf("DDR invalid size : 0x%lx, expected 0x%lx\n",
  267. (uintptr_t)priv->info.size, (uintptr_t)ddr_size);
  268. return -EINVAL;
  269. }
  270. return 0;
  271. }
  272. #endif
  273. static int fu540_ddr_probe(struct udevice *dev)
  274. {
  275. struct fu540_ddr_info *priv = dev_get_priv(dev);
  276. /* Read memory base and size from DT */
  277. fdtdec_setup_mem_size_base();
  278. priv->info.base = gd->ram_base;
  279. priv->info.size = gd->ram_size;
  280. #if defined(CONFIG_SPL_BUILD)
  281. struct regmap *map;
  282. int ret;
  283. u32 clock = 0;
  284. debug("FU540 DDR probe\n");
  285. priv->dev = dev;
  286. ret = regmap_init_mem(dev_ofnode(dev), &map);
  287. if (ret)
  288. return ret;
  289. ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
  290. if (ret) {
  291. debug("clk get failed %d\n", ret);
  292. return ret;
  293. }
  294. ret = dev_read_u32(dev, "clock-frequency", &clock);
  295. if (ret) {
  296. debug("clock-frequency not found in dt %d\n", ret);
  297. return ret;
  298. } else {
  299. ret = clk_set_rate(&priv->ddr_clk, clock);
  300. if (ret < 0) {
  301. debug("Could not set DDR clock\n");
  302. return ret;
  303. }
  304. }
  305. ret = clk_enable(&priv->ddr_clk);
  306. priv->ctl = regmap_get_range(map, 0);
  307. priv->phy = regmap_get_range(map, 1);
  308. priv->physical_filter_ctrl = regmap_get_range(map, 2);
  309. return fu540_ddr_setup(dev);
  310. #endif
  311. return 0;
  312. }
  313. static int fu540_ddr_get_info(struct udevice *dev, struct ram_info *info)
  314. {
  315. struct fu540_ddr_info *priv = dev_get_priv(dev);
  316. *info = priv->info;
  317. return 0;
  318. }
  319. static struct ram_ops fu540_ddr_ops = {
  320. .get_info = fu540_ddr_get_info,
  321. };
  322. static const struct udevice_id fu540_ddr_ids[] = {
  323. { .compatible = "sifive,fu540-c000-ddr" },
  324. { }
  325. };
  326. U_BOOT_DRIVER(fu540_ddr) = {
  327. .name = "fu540_ddr",
  328. .id = UCLASS_RAM,
  329. .of_match = fu540_ddr_ids,
  330. .ops = &fu540_ddr_ops,
  331. .probe = fu540_ddr_probe,
  332. .priv_auto_alloc_size = sizeof(struct fu540_ddr_info),
  333. #if defined(CONFIG_SPL_BUILD)
  334. .platdata_auto_alloc_size = sizeof(struct sifive_dmc_plat),
  335. #endif
  336. };