t208xqds.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2009-2013 Freescale Semiconductor, Inc.
  4. * Copyright 2020 NXP
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <env.h>
  9. #include <fdt_support.h>
  10. #include <i2c.h>
  11. #include <image.h>
  12. #include <init.h>
  13. #include <log.h>
  14. #include <netdev.h>
  15. #include <linux/compiler.h>
  16. #include <asm/mmu.h>
  17. #include <asm/processor.h>
  18. #include <asm/immap_85xx.h>
  19. #include <asm/fsl_law.h>
  20. #include <asm/fsl_serdes.h>
  21. #include <asm/fsl_liodn.h>
  22. #include <fm_eth.h>
  23. #include "../common/qixis.h"
  24. #include "../common/vsc3316_3308.h"
  25. #include "../common/vid.h"
  26. #include "t208xqds.h"
  27. #include "t208xqds_qixis.h"
  28. DECLARE_GLOBAL_DATA_PTR;
  29. int checkboard(void)
  30. {
  31. char buf[64];
  32. u8 sw;
  33. struct cpu_type *cpu = gd->arch.cpu;
  34. static const char *freq[4] = {
  35. "100.00MHZ(from 8T49N222A)", "125.00MHz",
  36. "156.25MHZ", "100.00MHz"
  37. };
  38. printf("Board: %sQDS, ", cpu->name);
  39. sw = QIXIS_READ(arch);
  40. printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
  41. printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  42. #ifdef CONFIG_SDCARD
  43. puts("SD/MMC\n");
  44. #elif CONFIG_SPIFLASH
  45. puts("SPI\n");
  46. #else
  47. sw = QIXIS_READ(brdcfg[0]);
  48. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  49. if (sw < 0x8)
  50. printf("vBank%d\n", sw);
  51. else if (sw == 0x8)
  52. puts("Promjet\n");
  53. else if (sw == 0x9)
  54. puts("NAND\n");
  55. else
  56. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  57. #endif
  58. printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
  59. qixis_read_tag(buf), (int)qixis_read_minor());
  60. /* the timestamp string contains "\n" at the end */
  61. printf(" on %s", qixis_read_time(buf));
  62. puts("SERDES Reference Clocks:\n");
  63. sw = QIXIS_READ(brdcfg[2]);
  64. printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6],
  65. freq[(sw >> 4) & 0x3]);
  66. printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2],
  67. freq[sw & 0x3]);
  68. return 0;
  69. }
  70. int select_i2c_ch_pca9547(u8 ch, int bus_num)
  71. {
  72. int ret;
  73. #ifdef CONFIG_DM_I2C
  74. struct udevice *dev;
  75. ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
  76. if (ret) {
  77. printf("%s: Cannot find udev for a bus %d\n", __func__,
  78. bus_num);
  79. return ret;
  80. }
  81. ret = dm_i2c_write(dev, 0, &ch, 1);
  82. #else
  83. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  84. #endif
  85. if (ret) {
  86. puts("PCA: failed to select proper channel\n");
  87. return ret;
  88. }
  89. return 0;
  90. }
  91. int i2c_multiplexer_select_vid_channel(u8 channel)
  92. {
  93. return select_i2c_ch_pca9547(channel, 0);
  94. }
  95. int brd_mux_lane_to_slot(void)
  96. {
  97. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  98. u32 srds_prtcl_s1;
  99. srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
  100. FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  101. srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  102. #if defined(CONFIG_TARGET_T2080QDS)
  103. u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
  104. FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
  105. srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
  106. #endif
  107. switch (srds_prtcl_s1) {
  108. case 0:
  109. /* SerDes1 is not enabled */
  110. break;
  111. #if defined(CONFIG_TARGET_T2080QDS)
  112. case 0x1b:
  113. case 0x1c:
  114. case 0xa2:
  115. /* SD1(A:D) => SLOT3 SGMII
  116. * SD1(G:H) => SLOT1 SGMII
  117. */
  118. QIXIS_WRITE(brdcfg[12], 0x1a);
  119. break;
  120. case 0x94:
  121. case 0x95:
  122. /* SD1(A:B) => SLOT3 SGMII@1.25bps
  123. * SD1(C:D) => SFP Module, SGMII@3.125bps
  124. * SD1(E:H) => SLOT1 SGMII@1.25bps
  125. */
  126. case 0x96:
  127. /* SD1(A:B) => SLOT3 SGMII@1.25bps
  128. * SD1(C) => SFP Module, SGMII@3.125bps
  129. * SD1(D) => SFP Module, SGMII@1.25bps
  130. * SD1(E:H) => SLOT1 PCIe4 x4
  131. */
  132. QIXIS_WRITE(brdcfg[12], 0x3a);
  133. break;
  134. case 0x50:
  135. case 0x51:
  136. /* SD1(A:D) => SLOT3 XAUI
  137. * SD1(E) => SLOT1 PCIe4
  138. * SD1(F:H) => SLOT2 SGMII
  139. */
  140. QIXIS_WRITE(brdcfg[12], 0x15);
  141. break;
  142. case 0x66:
  143. case 0x67:
  144. /* SD1(A:D) => XFI cage
  145. * SD1(E:H) => SLOT1 PCIe4
  146. */
  147. QIXIS_WRITE(brdcfg[12], 0xfe);
  148. break;
  149. case 0x6a:
  150. case 0x6b:
  151. /* SD1(A:D) => XFI cage
  152. * SD1(E) => SLOT1 PCIe4
  153. * SD1(F:H) => SLOT2 SGMII
  154. */
  155. QIXIS_WRITE(brdcfg[12], 0xf1);
  156. break;
  157. case 0x6c:
  158. case 0x6d:
  159. /* SD1(A:B) => XFI cage
  160. * SD1(C:D) => SLOT3 SGMII
  161. * SD1(E:H) => SLOT1 PCIe4
  162. */
  163. QIXIS_WRITE(brdcfg[12], 0xda);
  164. break;
  165. case 0x6e:
  166. /* SD1(A:B) => SFP Module, XFI
  167. * SD1(C:D) => SLOT3 SGMII
  168. * SD1(E:F) => SLOT1 PCIe4 x2
  169. * SD1(G:H) => SLOT2 SGMII
  170. */
  171. QIXIS_WRITE(brdcfg[12], 0xd9);
  172. break;
  173. case 0xda:
  174. /* SD1(A:H) => SLOT3 PCIe3 x8
  175. */
  176. QIXIS_WRITE(brdcfg[12], 0x0);
  177. break;
  178. case 0xc8:
  179. /* SD1(A) => SLOT3 PCIe3 x1
  180. * SD1(B) => SFP Module, SGMII@1.25bps
  181. * SD1(C:D) => SFP Module, SGMII@3.125bps
  182. * SD1(E:F) => SLOT1 PCIe4 x2
  183. * SD1(G:H) => SLOT2 SGMII
  184. */
  185. QIXIS_WRITE(brdcfg[12], 0x79);
  186. break;
  187. case 0xab:
  188. /* SD1(A:D) => SLOT3 PCIe3 x4
  189. * SD1(E:H) => SLOT1 PCIe4 x4
  190. */
  191. QIXIS_WRITE(brdcfg[12], 0x1a);
  192. break;
  193. #elif defined(CONFIG_TARGET_T2081QDS)
  194. case 0x50:
  195. case 0x51:
  196. /* SD1(A:D) => SLOT2 XAUI
  197. * SD1(E) => SLOT1 PCIe4 x1
  198. * SD1(F:H) => SLOT3 SGMII
  199. */
  200. QIXIS_WRITE(brdcfg[12], 0x98);
  201. QIXIS_WRITE(brdcfg[13], 0x70);
  202. break;
  203. case 0x6a:
  204. case 0x6b:
  205. /* SD1(A:D) => XFI SFP Module
  206. * SD1(E) => SLOT1 PCIe4 x1
  207. * SD1(F:H) => SLOT3 SGMII
  208. */
  209. QIXIS_WRITE(brdcfg[12], 0x80);
  210. QIXIS_WRITE(brdcfg[13], 0x70);
  211. break;
  212. case 0x6c:
  213. case 0x6d:
  214. /* SD1(A:B) => XFI SFP Module
  215. * SD1(C:D) => SLOT2 SGMII
  216. * SD1(E:H) => SLOT1 PCIe4 x4
  217. */
  218. QIXIS_WRITE(brdcfg[12], 0xe8);
  219. QIXIS_WRITE(brdcfg[13], 0x0);
  220. break;
  221. case 0xaa:
  222. case 0xab:
  223. /* SD1(A:D) => SLOT2 PCIe3 x4
  224. * SD1(F:H) => SLOT1 SGMI4 x4
  225. */
  226. QIXIS_WRITE(brdcfg[12], 0xf8);
  227. QIXIS_WRITE(brdcfg[13], 0x0);
  228. break;
  229. case 0xca:
  230. case 0xcb:
  231. /* SD1(A) => SLOT2 PCIe3 x1
  232. * SD1(B) => SLOT7 SGMII
  233. * SD1(C) => SLOT6 SGMII
  234. * SD1(D) => SLOT5 SGMII
  235. * SD1(E) => SLOT1 PCIe4 x1
  236. * SD1(F:H) => SLOT3 SGMII
  237. */
  238. QIXIS_WRITE(brdcfg[12], 0x80);
  239. QIXIS_WRITE(brdcfg[13], 0x70);
  240. break;
  241. case 0xde:
  242. case 0xdf:
  243. /* SD1(A:D) => SLOT2 PCIe3 x4
  244. * SD1(E) => SLOT1 PCIe4 x1
  245. * SD1(F) => SLOT4 PCIe1 x1
  246. * SD1(G) => SLOT3 PCIe2 x1
  247. * SD1(H) => SLOT7 SGMII
  248. */
  249. QIXIS_WRITE(brdcfg[12], 0x98);
  250. QIXIS_WRITE(brdcfg[13], 0x25);
  251. break;
  252. case 0xf2:
  253. /* SD1(A) => SLOT2 PCIe3 x1
  254. * SD1(B:D) => SLOT7 SGMII
  255. * SD1(E) => SLOT1 PCIe4 x1
  256. * SD1(F) => SLOT4 PCIe1 x1
  257. * SD1(G) => SLOT3 PCIe2 x1
  258. * SD1(H) => SLOT7 SGMII
  259. */
  260. QIXIS_WRITE(brdcfg[12], 0x81);
  261. QIXIS_WRITE(brdcfg[13], 0xa5);
  262. break;
  263. #endif
  264. default:
  265. printf("WARNING: unsupported for SerDes1 Protocol %d\n",
  266. srds_prtcl_s1);
  267. return -1;
  268. }
  269. #ifdef CONFIG_TARGET_T2080QDS
  270. switch (srds_prtcl_s2) {
  271. case 0:
  272. /* SerDes2 is not enabled */
  273. break;
  274. case 0x01:
  275. case 0x02:
  276. /* SD2(A:H) => SLOT4 PCIe1 */
  277. QIXIS_WRITE(brdcfg[13], 0x10);
  278. break;
  279. case 0x15:
  280. case 0x16:
  281. /*
  282. * SD2(A:D) => SLOT4 PCIe1
  283. * SD2(E:F) => SLOT5 PCIe2
  284. * SD2(G:H) => SATA1,SATA2
  285. */
  286. QIXIS_WRITE(brdcfg[13], 0xb0);
  287. break;
  288. case 0x18:
  289. /*
  290. * SD2(A:D) => SLOT4 PCIe1
  291. * SD2(E:F) => SLOT5 Aurora
  292. * SD2(G:H) => SATA1,SATA2
  293. */
  294. QIXIS_WRITE(brdcfg[13], 0x78);
  295. break;
  296. case 0x1f:
  297. /*
  298. * SD2(A:D) => SLOT4 PCIe1
  299. * SD2(E:H) => SLOT5 PCIe2
  300. */
  301. QIXIS_WRITE(brdcfg[13], 0xa0);
  302. break;
  303. case 0x29:
  304. case 0x2d:
  305. case 0x2e:
  306. /*
  307. * SD2(A:D) => SLOT4 SRIO2
  308. * SD2(E:H) => SLOT5 SRIO1
  309. */
  310. QIXIS_WRITE(brdcfg[13], 0xa0);
  311. break;
  312. case 0x36:
  313. /*
  314. * SD2(A:D) => SLOT4 SRIO2
  315. * SD2(E:F) => Aurora
  316. * SD2(G:H) => SATA1,SATA2
  317. */
  318. QIXIS_WRITE(brdcfg[13], 0x78);
  319. break;
  320. default:
  321. printf("WARNING: unsupported for SerDes2 Protocol %d\n",
  322. srds_prtcl_s2);
  323. return -1;
  324. }
  325. #endif
  326. return 0;
  327. }
  328. static void esdhc_adapter_card_ident(void)
  329. {
  330. u8 card_id, value;
  331. card_id = QIXIS_READ(present) & QIXIS_SDID_MASK;
  332. switch (card_id) {
  333. case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45:
  334. value = QIXIS_READ(brdcfg[5]);
  335. value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7);
  336. QIXIS_WRITE(brdcfg[5], value);
  337. break;
  338. case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY:
  339. value = QIXIS_READ(pwr_ctl[1]);
  340. value |= QIXIS_EVDD_BY_SDHC_VS;
  341. QIXIS_WRITE(pwr_ctl[1], value);
  342. break;
  343. case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44:
  344. value = QIXIS_READ(brdcfg[5]);
  345. value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT);
  346. QIXIS_WRITE(brdcfg[5], value);
  347. break;
  348. default:
  349. break;
  350. }
  351. }
  352. int board_early_init_r(void)
  353. {
  354. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  355. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  356. /*
  357. * Remap Boot flash + PROMJET region to caching-inhibited
  358. * so that flash can be erased properly.
  359. */
  360. /* Flush d-cache and invalidate i-cache of any FLASH data */
  361. flush_dcache();
  362. invalidate_icache();
  363. if (flash_esel == -1) {
  364. /* very unlikely unless something is messed up */
  365. puts("Error: Could not find TLB for FLASH BASE\n");
  366. flash_esel = 2; /* give our best effort to continue */
  367. } else {
  368. /* invalidate existing TLB entry for flash + promjet */
  369. disable_tlb(flash_esel);
  370. }
  371. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  372. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  373. 0, flash_esel, BOOKE_PAGESZ_256M, 1);
  374. /* Disable remote I2C connection to qixis fpga */
  375. QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
  376. /*
  377. * Adjust core voltage according to voltage ID
  378. * This function changes I2C mux to channel 2.
  379. */
  380. if (adjust_vdd(0))
  381. printf("Warning: Adjusting core voltage failed.\n");
  382. brd_mux_lane_to_slot();
  383. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
  384. esdhc_adapter_card_ident();
  385. return 0;
  386. }
  387. unsigned long get_board_sys_clk(void)
  388. {
  389. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  390. #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
  391. /* use accurate clock measurement */
  392. int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
  393. int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
  394. u32 val;
  395. val = freq * base;
  396. if (val) {
  397. debug("SYS Clock measurement is: %d\n", val);
  398. return val;
  399. } else {
  400. printf("Warning: SYS clock measurement is invalid, ");
  401. printf("using value from brdcfg1.\n");
  402. }
  403. #endif
  404. switch (sysclk_conf & 0x0F) {
  405. case QIXIS_SYSCLK_83:
  406. return 83333333;
  407. case QIXIS_SYSCLK_100:
  408. return 100000000;
  409. case QIXIS_SYSCLK_125:
  410. return 125000000;
  411. case QIXIS_SYSCLK_133:
  412. return 133333333;
  413. case QIXIS_SYSCLK_150:
  414. return 150000000;
  415. case QIXIS_SYSCLK_160:
  416. return 160000000;
  417. case QIXIS_SYSCLK_166:
  418. return 166666666;
  419. }
  420. return 66666666;
  421. }
  422. unsigned long get_board_ddr_clk(void)
  423. {
  424. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  425. #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
  426. /* use accurate clock measurement */
  427. int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
  428. int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
  429. u32 val;
  430. val = freq * base;
  431. if (val) {
  432. debug("DDR Clock measurement is: %d\n", val);
  433. return val;
  434. } else {
  435. printf("Warning: DDR clock measurement is invalid, ");
  436. printf("using value from brdcfg1.\n");
  437. }
  438. #endif
  439. switch ((ddrclk_conf & 0x30) >> 4) {
  440. case QIXIS_DDRCLK_100:
  441. return 100000000;
  442. case QIXIS_DDRCLK_125:
  443. return 125000000;
  444. case QIXIS_DDRCLK_133:
  445. return 133333333;
  446. }
  447. return 66666666;
  448. }
  449. int misc_init_r(void)
  450. {
  451. return 0;
  452. }
  453. int ft_board_setup(void *blob, struct bd_info *bd)
  454. {
  455. phys_addr_t base;
  456. phys_size_t size;
  457. ft_cpu_setup(blob, bd);
  458. base = env_get_bootm_low();
  459. size = env_get_bootm_size();
  460. fdt_fixup_memory(blob, (u64)base, (u64)size);
  461. #ifdef CONFIG_PCI
  462. pci_of_setup(blob, bd);
  463. #endif
  464. fdt_fixup_liodn(blob);
  465. fsl_fdt_fixup_dr_usb(blob, bd);
  466. #ifdef CONFIG_SYS_DPAA_FMAN
  467. #ifndef CONFIG_DM_ETH
  468. fdt_fixup_fman_ethernet(blob);
  469. #endif
  470. fdt_fixup_board_enet(blob);
  471. #endif
  472. return 0;
  473. }