hardware.h 3.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (c) 2013 Xilinx Inc.
  4. */
  5. #ifndef _ASM_ARCH_HARDWARE_H
  6. #define _ASM_ARCH_HARDWARE_H
  7. #define ZYNQ_SYS_CTRL_BASEADDR 0xF8000000
  8. #define ZYNQ_DEV_CFG_APB_BASEADDR 0xF8007000
  9. #define ZYNQ_SCU_BASEADDR 0xF8F00000
  10. #define ZYNQ_GEM_BASEADDR0 0xE000B000
  11. #define ZYNQ_GEM_BASEADDR1 0xE000C000
  12. #define ZYNQ_I2C_BASEADDR0 0xE0004000
  13. #define ZYNQ_I2C_BASEADDR1 0xE0005000
  14. #define ZYNQ_QSPI_BASEADDR 0xE000D000
  15. #define ZYNQ_SMC_BASEADDR 0xE000E000
  16. #define ZYNQ_NAND_BASEADDR 0xE1000000
  17. #define ZYNQ_DDRC_BASEADDR 0xF8006000
  18. #define ZYNQ_EFUSE_BASEADDR 0xF800D000
  19. #define ZYNQ_USB_BASEADDR0 0xE0002000
  20. #define ZYNQ_USB_BASEADDR1 0xE0003000
  21. #define ZYNQ_OCM_BASEADDR 0xFFFC0000
  22. /* Bootmode setting values */
  23. #define ZYNQ_BM_MASK 0x7
  24. #define ZYNQ_BM_QSPI 0x1
  25. #define ZYNQ_BM_NOR 0x2
  26. #define ZYNQ_BM_NAND 0x4
  27. #define ZYNQ_BM_SD 0x5
  28. #define ZYNQ_BM_JTAG 0x0
  29. /* Reflect slcr offsets */
  30. struct slcr_regs {
  31. u32 scl; /* 0x0 */
  32. u32 slcr_lock; /* 0x4 */
  33. u32 slcr_unlock; /* 0x8 */
  34. u32 reserved0_1[61];
  35. u32 arm_pll_ctrl; /* 0x100 */
  36. u32 ddr_pll_ctrl; /* 0x104 */
  37. u32 io_pll_ctrl; /* 0x108 */
  38. u32 reserved0_2[5];
  39. u32 arm_clk_ctrl; /* 0x120 */
  40. u32 ddr_clk_ctrl; /* 0x124 */
  41. u32 dci_clk_ctrl; /* 0x128 */
  42. u32 aper_clk_ctrl; /* 0x12c */
  43. u32 reserved0_3[2];
  44. u32 gem0_rclk_ctrl; /* 0x138 */
  45. u32 gem1_rclk_ctrl; /* 0x13c */
  46. u32 gem0_clk_ctrl; /* 0x140 */
  47. u32 gem1_clk_ctrl; /* 0x144 */
  48. u32 smc_clk_ctrl; /* 0x148 */
  49. u32 lqspi_clk_ctrl; /* 0x14c */
  50. u32 sdio_clk_ctrl; /* 0x150 */
  51. u32 uart_clk_ctrl; /* 0x154 */
  52. u32 spi_clk_ctrl; /* 0x158 */
  53. u32 can_clk_ctrl; /* 0x15c */
  54. u32 can_mioclk_ctrl; /* 0x160 */
  55. u32 dbg_clk_ctrl; /* 0x164 */
  56. u32 pcap_clk_ctrl; /* 0x168 */
  57. u32 reserved0_4[1];
  58. u32 fpga0_clk_ctrl; /* 0x170 */
  59. u32 reserved0_5[3];
  60. u32 fpga1_clk_ctrl; /* 0x180 */
  61. u32 reserved0_6[3];
  62. u32 fpga2_clk_ctrl; /* 0x190 */
  63. u32 reserved0_7[3];
  64. u32 fpga3_clk_ctrl; /* 0x1a0 */
  65. u32 reserved0_8[8];
  66. u32 clk_621_true; /* 0x1c4 */
  67. u32 reserved1[14];
  68. u32 pss_rst_ctrl; /* 0x200 */
  69. u32 reserved2[15];
  70. u32 fpga_rst_ctrl; /* 0x240 */
  71. u32 reserved3[5];
  72. u32 reboot_status; /* 0x258 */
  73. u32 boot_mode; /* 0x25c */
  74. u32 reserved4[116];
  75. u32 trust_zone; /* 0x430 */ /* FIXME */
  76. u32 reserved5_1[63];
  77. u32 pss_idcode; /* 0x530 */
  78. u32 reserved5_2[51];
  79. u32 ddr_urgent; /* 0x600 */
  80. u32 reserved6[6];
  81. u32 ddr_urgent_sel; /* 0x61c */
  82. u32 reserved7[56];
  83. u32 mio_pin[54]; /* 0x700 - 0x7D4 */
  84. u32 reserved8[74];
  85. u32 lvl_shftr_en; /* 0x900 */
  86. u32 reserved9[3];
  87. u32 ocm_cfg; /* 0x910 */
  88. };
  89. #define slcr_base ((struct slcr_regs *)ZYNQ_SYS_CTRL_BASEADDR)
  90. struct devcfg_regs {
  91. u32 ctrl; /* 0x0 */
  92. u32 lock; /* 0x4 */
  93. u32 cfg; /* 0x8 */
  94. u32 int_sts; /* 0xc */
  95. u32 int_mask; /* 0x10 */
  96. u32 status; /* 0x14 */
  97. u32 dma_src_addr; /* 0x18 */
  98. u32 dma_dst_addr; /* 0x1c */
  99. u32 dma_src_len; /* 0x20 */
  100. u32 dma_dst_len; /* 0x24 */
  101. u32 rom_shadow; /* 0x28 */
  102. u32 reserved1[2];
  103. u32 unlock; /* 0x34 */
  104. u32 reserved2[18];
  105. u32 mctrl; /* 0x80 */
  106. u32 reserved3;
  107. u32 write_count; /* 0x88 */
  108. u32 read_count; /* 0x8c */
  109. };
  110. #define devcfg_base ((struct devcfg_regs *)ZYNQ_DEV_CFG_APB_BASEADDR)
  111. struct scu_regs {
  112. u32 reserved1[16];
  113. u32 filter_start; /* 0x40 */
  114. u32 filter_end; /* 0x44 */
  115. };
  116. #define scu_base ((struct scu_regs *)ZYNQ_SCU_BASEADDR)
  117. struct ddrc_regs {
  118. u32 ddrc_ctrl; /* 0x0 */
  119. u32 reserved[60];
  120. u32 ecc_scrub; /* 0xF4 */
  121. };
  122. #define ddrc_base ((struct ddrc_regs *)ZYNQ_DDRC_BASEADDR)
  123. struct efuse_reg {
  124. u32 reserved1[4];
  125. u32 status;
  126. u32 reserved2[3];
  127. };
  128. #define efuse_base ((struct efuse_reg *)ZYNQ_EFUSE_BASEADDR)
  129. #endif /* _ASM_ARCH_HARDWARE_H */