lowlevel_init.S 6.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (c) 2018 Stefan Roese <sr@denx.de>
  4. *
  5. * This code is mostly based on the code extracted from this MediaTek
  6. * github repository:
  7. *
  8. * https://github.com/MediaTek-Labs/linkit-smart-uboot.git
  9. *
  10. * I was not able to find a specific license or other developers
  11. * copyrights here, so I can't add them here.
  12. */
  13. #include <config.h>
  14. #include <asm/regdef.h>
  15. #include <asm/mipsregs.h>
  16. #include <asm/addrspace.h>
  17. #include <asm/asm.h>
  18. #include "mt76xx.h"
  19. #ifndef BIT
  20. #define BIT(nr) (1 << (nr))
  21. #endif
  22. #define DELAY_USEC(us) ((us) / 100)
  23. #define DDR_CFG1_CHIP_WIDTH_MASK (0x3 << 16)
  24. #define DDR_CFG1_BUS_WIDTH_MASK (0x3 << 12)
  25. #if defined(CONFIG_ONBOARD_DDR2_SIZE_256MBIT)
  26. #define DDR_CFG1_SIZE_VAL 0x222e2323
  27. #define DDR_CFG4_SIZE_VAL 7
  28. #endif
  29. #if defined(CONFIG_ONBOARD_DDR2_SIZE_512MBIT)
  30. #define DDR_CFG1_SIZE_VAL 0x22322323
  31. #define DDR_CFG4_SIZE_VAL 9
  32. #endif
  33. #if defined(CONFIG_ONBOARD_DDR2_SIZE_1024MBIT)
  34. #define DDR_CFG1_SIZE_VAL 0x22362323
  35. #define DDR_CFG4_SIZE_VAL 9
  36. #endif
  37. #if defined(CONFIG_ONBOARD_DDR2_SIZE_2048MBIT)
  38. #define DDR_CFG1_SIZE_VAL 0x223a2323
  39. #define DDR_CFG4_SIZE_VAL 9
  40. #endif
  41. #if defined(CONFIG_ONBOARD_DDR2_CHIP_WIDTH_8BIT)
  42. #define DDR_CFG1_CHIP_WIDTH_VAL (0x1 << 16)
  43. #endif
  44. #if defined(CONFIG_ONBOARD_DDR2_CHIP_WIDTH_16BIT)
  45. #define DDR_CFG1_CHIP_WIDTH_VAL (0x2 << 16)
  46. #endif
  47. #if defined(CONFIG_ONBOARD_DDR2_BUS_WIDTH_16BIT)
  48. #define DDR_CFG1_BUS_WIDTH_VAL (0x2 << 12)
  49. #endif
  50. #if defined(CONFIG_ONBOARD_DDR2_BUS_WIDTH_32BIT)
  51. #define DDR_CFG1_BUS_WIDTH_VAL (0x3 << 12)
  52. #endif
  53. .set noreorder
  54. LEAF(lowlevel_init)
  55. /* Load base addresses as physical addresses for later usage */
  56. li s0, CKSEG1ADDR(MT76XX_SYSCTL_BASE)
  57. li s1, CKSEG1ADDR(MT76XX_MEMCTRL_BASE)
  58. li s2, CKSEG1ADDR(MT76XX_RGCTRL_BASE)
  59. /* polling CPLL is ready */
  60. li t1, DELAY_USEC(1000000)
  61. la t5, MT76XX_ROM_STATUS_REG
  62. 1:
  63. lw t2, 0(t5)
  64. andi t2, t2, 0x1
  65. bnez t2, CPLL_READY
  66. subu t1, t1, 1
  67. bgtz t1, 1b
  68. nop
  69. la t0, MT76XX_CLKCFG0_REG
  70. lw t3, 0(t0)
  71. ori t3, t3, 0x1
  72. sw t3, 0(t0)
  73. b CPLL_DONE
  74. nop
  75. CPLL_READY:
  76. la t0, MT76XX_CLKCFG0_REG
  77. lw t1, 0(t0)
  78. li t2, ~0x0c
  79. and t1, t1, t2
  80. ori t1, t1, 0xc
  81. sw t1, 0(t0)
  82. la t0, MT76XX_DYN_CFG0_REG
  83. lw t3, 0(t0)
  84. li t5, ~((0x0f << 8) | (0x0f << 0))
  85. and t3, t3, t5
  86. li t5, (10 << 8) | (1 << 0)
  87. or t3, t3, t5
  88. sw t3, 0(t0)
  89. la t0, MT76XX_CLKCFG0_REG
  90. lw t3, 0(t0)
  91. li t4, ~0x0F
  92. and t3, t3, t4
  93. ori t3, t3, 0xc
  94. sw t3, 0(t0)
  95. lw t3, 0(t0)
  96. ori t3, t3, 0x08
  97. sw t3, 0(t0)
  98. CPLL_DONE:
  99. /* Reset MC */
  100. lw t2, 0x34(s0)
  101. ori t2, BIT(10)
  102. sw t2, 0x34(s0)
  103. nop
  104. /*
  105. * SDR and DDR initialization: delay 200us
  106. */
  107. li t0, DELAY_USEC(200 + 40)
  108. li t1, 0x1
  109. 1:
  110. sub t0, t0, t1
  111. bnez t0, 1b
  112. nop
  113. /* set DRAM IO PAD for MT7628IC */
  114. /* DDR LDO Enable */
  115. lw t4, 0x100(s2)
  116. li t2, BIT(31)
  117. or t4, t4, t2
  118. sw t4, 0x100(s2)
  119. lw t4, 0x10c(s2)
  120. j LDO_1P8V
  121. nop
  122. LDO_1P8V:
  123. li t2, ~BIT(6)
  124. and t4, t4, t2
  125. sw t4, 0x10c(s2)
  126. j DDRLDO_SOFT_START
  127. LDO_2P5V:
  128. /* suppose external DDR1 LDO 2.5V */
  129. li t2, BIT(6)
  130. or t4, t4, t2
  131. sw t4, 0x10c(s2)
  132. DDRLDO_SOFT_START:
  133. lw t2, 0x10c(s2)
  134. li t3, BIT(16)
  135. or t2, t2, t3
  136. sw t2, 0x10c(s2)
  137. li t3, DELAY_USEC(250*50)
  138. LDO_DELAY:
  139. subu t3, t3, 1
  140. bnez t3, LDO_DELAY
  141. nop
  142. lw t2, 0x10c(s2)
  143. li t3, BIT(18)
  144. or t2, t2, t3
  145. sw t2, 0x10c(s2)
  146. SET_RG_BUCK_FPWM:
  147. lw t2, 0x104(s2)
  148. ori t2, t2, BIT(10)
  149. sw t2, 0x104(s2)
  150. DDR_PAD_CFG:
  151. /* clean CLK PAD */
  152. lw t2, 0x704(s2)
  153. li t8, 0xfffff0f0
  154. and t2, t2, t8
  155. /* clean CMD PAD */
  156. lw t3, 0x70c(s2)
  157. li t8, 0xfffff0f0
  158. and t3, t3, t8
  159. /* clean DQ IPAD */
  160. lw t4, 0x710(s2)
  161. li t8, 0xfffff8ff
  162. and t4, t4, t8
  163. /* clean DQ OPAD */
  164. lw t5, 0x714(s2)
  165. li t8, 0xfffff0f0
  166. and t5, t5, t8
  167. /* clean DQS IPAD */
  168. lw t6, 0x718(s2)
  169. li t8, 0xfffff8ff
  170. and t6, t6, t8
  171. /* clean DQS OPAD */
  172. lw t7, 0x71c(s2)
  173. li t8, 0xfffff0f0
  174. and t7, t7, t8
  175. lw t9, 0xc(s0)
  176. srl t9, t9, 16
  177. andi t9, t9, 0x1
  178. bnez t9, MT7628_AN_DDR1_PAD
  179. MT7628_KN_PAD:
  180. li t8, 0x00000303
  181. or t2, t2, t8
  182. or t3, t3, t8
  183. or t5, t5, t8
  184. or t7, t7, t8
  185. li t8, 0x00000000
  186. or t4, t4, t8
  187. or t6, t6, t8
  188. j SET_PAD_CFG
  189. MT7628_AN_DDR1_PAD:
  190. lw t1, 0x10(s0)
  191. andi t1, t1, 0x1
  192. beqz t1, MT7628_AN_DDR2_PAD
  193. li t8, 0x00000c0c
  194. or t2, t2, t8
  195. li t8, 0x00000202
  196. or t3, t3, t8
  197. li t8, 0x00000707
  198. or t5, t5, t8
  199. li t8, 0x00000c0c
  200. or t7, t7, t8
  201. li t8, 0x00000000
  202. or t4, t4, t8
  203. or t6, t6, t8
  204. j SET_PAD_CFG
  205. MT7628_AN_DDR2_PAD:
  206. li t8, 0x00000c0c
  207. or t2, t2, t8
  208. li t8, 0x00000202
  209. or t3, t3, t8
  210. li t8, 0x00000404
  211. or t5, t5, t8
  212. li t8, 0x00000c0c
  213. or t7, t7, t8
  214. li t8, 0x00000000 /* ODT off */
  215. or t4, t4, t8
  216. or t6, t6, t8
  217. SET_PAD_CFG:
  218. sw t2, 0x704(s2)
  219. sw t3, 0x70c(s2)
  220. sw t4, 0x710(s2)
  221. sw t5, 0x714(s2)
  222. sw t6, 0x718(s2)
  223. sw t7, 0x71c(s2)
  224. /*
  225. * DDR initialization: reset pin to 0
  226. */
  227. lw t2, 0x34(s0)
  228. and t2, ~BIT(10)
  229. sw t2, 0x34(s0)
  230. nop
  231. /*
  232. * DDR initialization: wait til reg DDR_CFG1 bit 21 equal to 1 (ready)
  233. */
  234. DDR_READY:
  235. li t1, DDR_CFG1_REG
  236. lw t0, 0(t1)
  237. nop
  238. and t2, t0, BIT(21)
  239. beqz t2, DDR_READY
  240. nop
  241. /*
  242. * DDR initialization
  243. *
  244. * Only DDR2 supported right now. DDR2 support can be added, once
  245. * boards using it will get added to mainline U-Boot.
  246. */
  247. li t1, DDR_CFG2_REG
  248. lw t0, 0(t1)
  249. nop
  250. and t0, ~BIT(30)
  251. and t0, ~(7 << 4)
  252. or t0, (4 << 4)
  253. or t0, BIT(30)
  254. or t0, BIT(11)
  255. sw t0, 0(t1)
  256. nop
  257. li t1, DDR_CFG3_REG
  258. lw t2, 0(t1)
  259. /* Disable ODT; reference board ok, ev board fail */
  260. and t2, ~BIT(6)
  261. or t2, BIT(2)
  262. li t0, DDR_CFG4_REG
  263. lw t1, 0(t0)
  264. li t2, ~(0x01f | 0x0f0)
  265. and t1, t1, t2
  266. ori t1, t1, DDR_CFG4_SIZE_VAL
  267. sw t1, 0(t0)
  268. nop
  269. /*
  270. * DDR initialization: config size and width on reg DDR_CFG1
  271. */
  272. li t6, DDR_CFG1_SIZE_VAL
  273. and t6, ~DDR_CFG1_CHIP_WIDTH_MASK
  274. or t6, DDR_CFG1_CHIP_WIDTH_VAL
  275. /* CONFIG DDR_CFG1[13:12] about TOTAL WIDTH */
  276. and t6, ~DDR_CFG1_BUS_WIDTH_MASK
  277. or t6, DDR_CFG1_BUS_WIDTH_VAL
  278. li t5, DDR_CFG1_REG
  279. sw t6, 0(t5)
  280. nop
  281. /*
  282. * DDR: enable self auto refresh for power saving
  283. * enable it by default for both RAM and ROM version (for CoC)
  284. */
  285. lw t1, 0x14(s1)
  286. nop
  287. and t1, 0xff000000
  288. or t1, 0x01
  289. sw t1, 0x14(s1)
  290. nop
  291. lw t1, 0x10(s1)
  292. nop
  293. or t1, 0x10
  294. sw t1, 0x10(s1)
  295. nop
  296. jr ra
  297. nop
  298. END(lowlevel_init)