t4240qds.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2009-2012 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <env.h>
  8. #include <i2c.h>
  9. #include <irq_func.h>
  10. #include <netdev.h>
  11. #include <linux/compiler.h>
  12. #include <asm/mmu.h>
  13. #include <asm/processor.h>
  14. #include <asm/cache.h>
  15. #include <asm/immap_85xx.h>
  16. #include <asm/fsl_law.h>
  17. #include <asm/fsl_serdes.h>
  18. #include <asm/fsl_liodn.h>
  19. #include <fm_eth.h>
  20. #include "../common/qixis.h"
  21. #include "../common/vsc3316_3308.h"
  22. #include "t4qds.h"
  23. #include "t4240qds_qixis.h"
  24. DECLARE_GLOBAL_DATA_PTR;
  25. static int8_t vsc3316_fsm1_tx[8][2] = { {0, 0}, {1, 1}, {6, 6}, {7, 7},
  26. {8, 8}, {9, 9}, {14, 14}, {15, 15} };
  27. static int8_t vsc3316_fsm2_tx[8][2] = { {2, 2}, {3, 3}, {4, 4}, {5, 5},
  28. {10, 10}, {11, 11}, {12, 12}, {13, 13} };
  29. static int8_t vsc3316_fsm1_rx[8][2] = { {2, 12}, {3, 13}, {4, 5}, {5, 4},
  30. {10, 11}, {11, 10}, {12, 2}, {13, 3} };
  31. static int8_t vsc3316_fsm2_rx[8][2] = { {0, 15}, {1, 14}, {6, 7}, {7, 6},
  32. {8, 9}, {9, 8}, {14, 1}, {15, 0} };
  33. int checkboard(void)
  34. {
  35. char buf[64];
  36. u8 sw;
  37. struct cpu_type *cpu = gd->arch.cpu;
  38. unsigned int i;
  39. printf("Board: %sQDS, ", cpu->name);
  40. printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
  41. QIXIS_READ(id), QIXIS_READ(arch));
  42. sw = QIXIS_READ(brdcfg[0]);
  43. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  44. if (sw < 0x8)
  45. printf("vBank: %d\n", sw);
  46. else if (sw == 0x8)
  47. puts("Promjet\n");
  48. else if (sw == 0x9)
  49. puts("NAND\n");
  50. else
  51. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  52. printf("FPGA: v%d (%s), build %d",
  53. (int)QIXIS_READ(scver), qixis_read_tag(buf),
  54. (int)qixis_read_minor());
  55. /* the timestamp string contains "\n" at the end */
  56. printf(" on %s", qixis_read_time(buf));
  57. /*
  58. * Display the actual SERDES reference clocks as configured by the
  59. * dip switches on the board. Note that the SWx registers could
  60. * technically be set to force the reference clocks to match the
  61. * values that the SERDES expects (or vice versa). For now, however,
  62. * we just display both values and hope the user notices when they
  63. * don't match.
  64. */
  65. puts("SERDES Reference Clocks: ");
  66. sw = QIXIS_READ(brdcfg[2]);
  67. for (i = 0; i < MAX_SERDES; i++) {
  68. static const char * const freq[] = {
  69. "100", "125", "156.25", "161.1328125"};
  70. unsigned int clock = (sw >> (6 - 2 * i)) & 3;
  71. printf("SERDES%u=%sMHz ", i+1, freq[clock]);
  72. }
  73. puts("\n");
  74. return 0;
  75. }
  76. int select_i2c_ch_pca9547(u8 ch)
  77. {
  78. int ret;
  79. ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  80. if (ret) {
  81. puts("PCA: failed to select proper channel\n");
  82. return ret;
  83. }
  84. return 0;
  85. }
  86. /*
  87. * read_voltage from sensor on I2C bus
  88. * We use average of 4 readings, waiting for 532us befor another reading
  89. */
  90. #define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */
  91. #define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */
  92. static inline int read_voltage(void)
  93. {
  94. int i, ret, voltage_read = 0;
  95. u16 vol_mon;
  96. for (i = 0; i < NUM_READINGS; i++) {
  97. ret = i2c_read(I2C_VOL_MONITOR_ADDR,
  98. I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
  99. if (ret) {
  100. printf("VID: failed to read core voltage\n");
  101. return ret;
  102. }
  103. if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
  104. printf("VID: Core voltage sensor error\n");
  105. return -1;
  106. }
  107. debug("VID: bus voltage reads 0x%04x\n", vol_mon);
  108. /* LSB = 4mv */
  109. voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
  110. udelay(WAIT_FOR_ADC);
  111. }
  112. /* calculate the average */
  113. voltage_read /= NUM_READINGS;
  114. return voltage_read;
  115. }
  116. /*
  117. * We need to calculate how long before the voltage starts to drop or increase
  118. * It returns with the loop count. Each loop takes several readings (532us)
  119. */
  120. static inline int wait_for_voltage_change(int vdd_last)
  121. {
  122. int timeout, vdd_current;
  123. vdd_current = read_voltage();
  124. /* wait until voltage starts to drop */
  125. for (timeout = 0; abs(vdd_last - vdd_current) <= 4 &&
  126. timeout < 100; timeout++) {
  127. vdd_current = read_voltage();
  128. }
  129. if (timeout >= 100) {
  130. printf("VID: Voltage adjustment timeout\n");
  131. return -1;
  132. }
  133. return timeout;
  134. }
  135. /*
  136. * argument 'wait' is the time we know the voltage difference can be measured
  137. * this function keeps reading the voltage until it is stable
  138. */
  139. static inline int wait_for_voltage_stable(int wait)
  140. {
  141. int timeout, vdd_current, vdd_last;
  142. vdd_last = read_voltage();
  143. udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
  144. /* wait until voltage is stable */
  145. vdd_current = read_voltage();
  146. for (timeout = 0; abs(vdd_last - vdd_current) >= 4 &&
  147. timeout < 100; timeout++) {
  148. vdd_last = vdd_current;
  149. udelay(wait * NUM_READINGS * WAIT_FOR_ADC);
  150. vdd_current = read_voltage();
  151. }
  152. if (timeout >= 100) {
  153. printf("VID: Voltage adjustment timeout\n");
  154. return -1;
  155. }
  156. return vdd_current;
  157. }
  158. static inline int set_voltage(u8 vid)
  159. {
  160. int wait, vdd_last;
  161. vdd_last = read_voltage();
  162. QIXIS_WRITE(brdcfg[6], vid);
  163. wait = wait_for_voltage_change(vdd_last);
  164. if (wait < 0)
  165. return -1;
  166. debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC);
  167. wait = wait ? wait : 1;
  168. vdd_last = wait_for_voltage_stable(wait);
  169. if (vdd_last < 0)
  170. return -1;
  171. debug("VID: Current voltage is %d mV\n", vdd_last);
  172. return vdd_last;
  173. }
  174. static int adjust_vdd(ulong vdd_override)
  175. {
  176. int re_enable = disable_interrupts();
  177. ccsr_gur_t __iomem *gur =
  178. (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  179. u32 fusesr;
  180. u8 vid, vid_current;
  181. int vdd_target, vdd_current, vdd_last;
  182. int ret;
  183. unsigned long vdd_string_override;
  184. char *vdd_string;
  185. static const uint16_t vdd[32] = {
  186. 0, /* unused */
  187. 9875, /* 0.9875V */
  188. 9750,
  189. 9625,
  190. 9500,
  191. 9375,
  192. 9250,
  193. 9125,
  194. 9000,
  195. 8875,
  196. 8750,
  197. 8625,
  198. 8500,
  199. 8375,
  200. 8250,
  201. 8125,
  202. 10000, /* 1.0000V */
  203. 10125,
  204. 10250,
  205. 10375,
  206. 10500,
  207. 10625,
  208. 10750,
  209. 10875,
  210. 11000,
  211. 0, /* reserved */
  212. };
  213. struct vdd_drive {
  214. u8 vid;
  215. unsigned voltage;
  216. };
  217. ret = select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR);
  218. if (ret) {
  219. debug("VID: I2c failed to switch channel\n");
  220. ret = -1;
  221. goto exit;
  222. }
  223. /* get the voltage ID from fuse status register */
  224. fusesr = in_be32(&gur->dcfg_fusesr);
  225. vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
  226. FSL_CORENET_DCFG_FUSESR_VID_MASK;
  227. if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
  228. vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
  229. FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
  230. }
  231. vdd_target = vdd[vid];
  232. /* check override variable for overriding VDD */
  233. vdd_string = env_get("t4240qds_vdd_mv");
  234. if (vdd_override == 0 && vdd_string &&
  235. !strict_strtoul(vdd_string, 10, &vdd_string_override))
  236. vdd_override = vdd_string_override;
  237. if (vdd_override >= 819 && vdd_override <= 1212) {
  238. vdd_target = vdd_override * 10; /* convert to 1/10 mV */
  239. debug("VDD override is %lu\n", vdd_override);
  240. } else if (vdd_override != 0) {
  241. printf("Invalid value.\n");
  242. }
  243. if (vdd_target == 0) {
  244. debug("VID: VID not used\n");
  245. ret = 0;
  246. goto exit;
  247. } else {
  248. /* round up and divice by 10 to get a value in mV */
  249. vdd_target = DIV_ROUND_UP(vdd_target, 10);
  250. debug("VID: vid = %d mV\n", vdd_target);
  251. }
  252. /*
  253. * Check current board VID setting
  254. * Voltage regulator support output to 6.250mv step
  255. * The highes voltage allowed for this board is (vid=0x40) 1.21250V
  256. * the lowest is (vid=0x7f) 0.81875V
  257. */
  258. vid_current = QIXIS_READ(brdcfg[6]);
  259. vdd_current = 121250 - (vid_current - 0x40) * 625;
  260. debug("VID: Current vid setting is (0x%x) %d mV\n",
  261. vid_current, vdd_current/100);
  262. /*
  263. * Read voltage monitor to check real voltage.
  264. * Voltage monitor LSB is 4mv.
  265. */
  266. vdd_last = read_voltage();
  267. if (vdd_last < 0) {
  268. printf("VID: Could not read voltage sensor abort VID adjustment\n");
  269. ret = -1;
  270. goto exit;
  271. }
  272. debug("VID: Core voltage is at %d mV\n", vdd_last);
  273. /*
  274. * Adjust voltage to at or 8mV above target.
  275. * Each step of adjustment is 6.25mV.
  276. * Stepping down too fast may cause over current.
  277. */
  278. while (vdd_last > 0 && vid_current < 0x80 &&
  279. vdd_last > (vdd_target + 8)) {
  280. vid_current++;
  281. vdd_last = set_voltage(vid_current);
  282. }
  283. /*
  284. * Check if we need to step up
  285. * This happens when board voltage switch was set too low
  286. */
  287. while (vdd_last > 0 && vid_current >= 0x40 &&
  288. vdd_last < vdd_target + 2) {
  289. vid_current--;
  290. vdd_last = set_voltage(vid_current);
  291. }
  292. if (vdd_last > 0)
  293. printf("VID: Core voltage %d mV\n", vdd_last);
  294. else
  295. ret = -1;
  296. exit:
  297. if (re_enable)
  298. enable_interrupts();
  299. return ret;
  300. }
  301. /* Configure Crossbar switches for Front-Side SerDes Ports */
  302. int config_frontside_crossbar_vsc3316(void)
  303. {
  304. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  305. u32 srds_prtcl_s1, srds_prtcl_s2;
  306. int ret;
  307. ret = select_i2c_ch_pca9547(I2C_MUX_CH_VSC3316_FS);
  308. if (ret)
  309. return ret;
  310. srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
  311. FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  312. srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  313. switch (srds_prtcl_s1) {
  314. case 37:
  315. case 38:
  316. /* swap first lane and third lane on slot1 */
  317. vsc3316_fsm1_tx[0][1] = 14;
  318. vsc3316_fsm1_tx[6][1] = 0;
  319. vsc3316_fsm1_rx[1][1] = 2;
  320. vsc3316_fsm1_rx[6][1] = 13;
  321. case 39:
  322. case 40:
  323. case 45:
  324. case 46:
  325. case 47:
  326. case 48:
  327. /* swap first lane and third lane on slot2 */
  328. vsc3316_fsm1_tx[2][1] = 8;
  329. vsc3316_fsm1_tx[4][1] = 6;
  330. vsc3316_fsm1_rx[2][1] = 10;
  331. vsc3316_fsm1_rx[5][1] = 5;
  332. default:
  333. ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm1_tx, 8);
  334. if (ret)
  335. return ret;
  336. ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm1_rx, 8);
  337. if (ret)
  338. return ret;
  339. break;
  340. }
  341. srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
  342. FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
  343. srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
  344. switch (srds_prtcl_s2) {
  345. case 37:
  346. case 38:
  347. /* swap first lane and third lane on slot3 */
  348. vsc3316_fsm2_tx[2][1] = 11;
  349. vsc3316_fsm2_tx[5][1] = 4;
  350. vsc3316_fsm2_rx[2][1] = 9;
  351. vsc3316_fsm2_rx[4][1] = 7;
  352. case 39:
  353. case 40:
  354. case 45:
  355. case 46:
  356. case 47:
  357. case 48:
  358. case 49:
  359. case 50:
  360. case 51:
  361. case 52:
  362. case 53:
  363. case 54:
  364. /* swap first lane and third lane on slot4 */
  365. vsc3316_fsm2_tx[6][1] = 3;
  366. vsc3316_fsm2_tx[1][1] = 12;
  367. vsc3316_fsm2_rx[0][1] = 1;
  368. vsc3316_fsm2_rx[6][1] = 15;
  369. default:
  370. ret = vsc3316_config(VSC3316_FSM_TX_ADDR, vsc3316_fsm2_tx, 8);
  371. if (ret)
  372. return ret;
  373. ret = vsc3316_config(VSC3316_FSM_RX_ADDR, vsc3316_fsm2_rx, 8);
  374. if (ret)
  375. return ret;
  376. break;
  377. }
  378. return 0;
  379. }
  380. int config_backside_crossbar_mux(void)
  381. {
  382. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  383. u32 srds_prtcl_s3, srds_prtcl_s4;
  384. u8 brdcfg;
  385. srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) &
  386. FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
  387. srds_prtcl_s3 >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
  388. switch (srds_prtcl_s3) {
  389. case 0:
  390. /* SerDes3 is not enabled */
  391. break;
  392. case 1:
  393. case 2:
  394. case 9:
  395. case 10:
  396. /* SD3(0:7) => SLOT5(0:7) */
  397. brdcfg = QIXIS_READ(brdcfg[12]);
  398. brdcfg &= ~BRDCFG12_SD3MX_MASK;
  399. brdcfg |= BRDCFG12_SD3MX_SLOT5;
  400. QIXIS_WRITE(brdcfg[12], brdcfg);
  401. break;
  402. case 3:
  403. case 4:
  404. case 5:
  405. case 6:
  406. case 7:
  407. case 8:
  408. case 11:
  409. case 12:
  410. case 13:
  411. case 14:
  412. case 15:
  413. case 16:
  414. case 17:
  415. case 18:
  416. case 19:
  417. case 20:
  418. /* SD3(4:7) => SLOT6(0:3) */
  419. brdcfg = QIXIS_READ(brdcfg[12]);
  420. brdcfg &= ~BRDCFG12_SD3MX_MASK;
  421. brdcfg |= BRDCFG12_SD3MX_SLOT6;
  422. QIXIS_WRITE(brdcfg[12], brdcfg);
  423. break;
  424. default:
  425. printf("WARNING: unsupported for SerDes3 Protocol %d\n",
  426. srds_prtcl_s3);
  427. return -1;
  428. }
  429. srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
  430. FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
  431. srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
  432. switch (srds_prtcl_s4) {
  433. case 0:
  434. /* SerDes4 is not enabled */
  435. break;
  436. case 1:
  437. case 2:
  438. /* 10b, SD4(0:7) => SLOT7(0:7) */
  439. brdcfg = QIXIS_READ(brdcfg[12]);
  440. brdcfg &= ~BRDCFG12_SD4MX_MASK;
  441. brdcfg |= BRDCFG12_SD4MX_SLOT7;
  442. QIXIS_WRITE(brdcfg[12], brdcfg);
  443. break;
  444. case 3:
  445. case 4:
  446. case 5:
  447. case 6:
  448. case 7:
  449. case 8:
  450. /* x1b, SD4(4:7) => SLOT8(0:3) */
  451. brdcfg = QIXIS_READ(brdcfg[12]);
  452. brdcfg &= ~BRDCFG12_SD4MX_MASK;
  453. brdcfg |= BRDCFG12_SD4MX_SLOT8;
  454. QIXIS_WRITE(brdcfg[12], brdcfg);
  455. break;
  456. case 9:
  457. case 10:
  458. case 11:
  459. case 12:
  460. case 13:
  461. case 14:
  462. case 15:
  463. case 16:
  464. case 18:
  465. /* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */
  466. brdcfg = QIXIS_READ(brdcfg[12]);
  467. brdcfg &= ~BRDCFG12_SD4MX_MASK;
  468. brdcfg |= BRDCFG12_SD4MX_AURO_SATA;
  469. QIXIS_WRITE(brdcfg[12], brdcfg);
  470. break;
  471. default:
  472. printf("WARNING: unsupported for SerDes4 Protocol %d\n",
  473. srds_prtcl_s4);
  474. return -1;
  475. }
  476. return 0;
  477. }
  478. int board_early_init_r(void)
  479. {
  480. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  481. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  482. /*
  483. * Remap Boot flash + PROMJET region to caching-inhibited
  484. * so that flash can be erased properly.
  485. */
  486. /* Flush d-cache and invalidate i-cache of any FLASH data */
  487. flush_dcache();
  488. invalidate_icache();
  489. if (flash_esel == -1) {
  490. /* very unlikely unless something is messed up */
  491. puts("Error: Could not find TLB for FLASH BASE\n");
  492. flash_esel = 2; /* give our best effort to continue */
  493. } else {
  494. /* invalidate existing TLB entry for flash + promjet */
  495. disable_tlb(flash_esel);
  496. }
  497. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  498. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  499. 0, flash_esel, BOOKE_PAGESZ_256M, 1);
  500. /* Disable remote I2C connection to qixis fpga */
  501. QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
  502. /*
  503. * Adjust core voltage according to voltage ID
  504. * This function changes I2C mux to channel 2.
  505. */
  506. if (adjust_vdd(0))
  507. printf("Warning: Adjusting core voltage failed.\n");
  508. /* Configure board SERDES ports crossbar */
  509. config_frontside_crossbar_vsc3316();
  510. config_backside_crossbar_mux();
  511. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  512. return 0;
  513. }
  514. unsigned long get_board_sys_clk(void)
  515. {
  516. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  517. #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
  518. /* use accurate clock measurement */
  519. int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
  520. int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
  521. u32 val;
  522. val = freq * base;
  523. if (val) {
  524. debug("SYS Clock measurement is: %d\n", val);
  525. return val;
  526. } else {
  527. printf("Warning: SYS clock measurement is invalid, using value from brdcfg1.\n");
  528. }
  529. #endif
  530. switch (sysclk_conf & 0x0F) {
  531. case QIXIS_SYSCLK_83:
  532. return 83333333;
  533. case QIXIS_SYSCLK_100:
  534. return 100000000;
  535. case QIXIS_SYSCLK_125:
  536. return 125000000;
  537. case QIXIS_SYSCLK_133:
  538. return 133333333;
  539. case QIXIS_SYSCLK_150:
  540. return 150000000;
  541. case QIXIS_SYSCLK_160:
  542. return 160000000;
  543. case QIXIS_SYSCLK_166:
  544. return 166666666;
  545. }
  546. return 66666666;
  547. }
  548. unsigned long get_board_ddr_clk(void)
  549. {
  550. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  551. #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
  552. /* use accurate clock measurement */
  553. int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
  554. int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
  555. u32 val;
  556. val = freq * base;
  557. if (val) {
  558. debug("DDR Clock measurement is: %d\n", val);
  559. return val;
  560. } else {
  561. printf("Warning: DDR clock measurement is invalid, using value from brdcfg1.\n");
  562. }
  563. #endif
  564. switch ((ddrclk_conf & 0x30) >> 4) {
  565. case QIXIS_DDRCLK_100:
  566. return 100000000;
  567. case QIXIS_DDRCLK_125:
  568. return 125000000;
  569. case QIXIS_DDRCLK_133:
  570. return 133333333;
  571. }
  572. return 66666666;
  573. }
  574. int misc_init_r(void)
  575. {
  576. u8 sw;
  577. void *srds_base = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  578. serdes_corenet_t *srds_regs;
  579. u32 actual[MAX_SERDES];
  580. u32 pllcr0, expected;
  581. unsigned int i;
  582. sw = QIXIS_READ(brdcfg[2]);
  583. for (i = 0; i < MAX_SERDES; i++) {
  584. unsigned int clock = (sw >> (6 - 2 * i)) & 3;
  585. switch (clock) {
  586. case 0:
  587. actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
  588. break;
  589. case 1:
  590. actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
  591. break;
  592. case 2:
  593. actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
  594. break;
  595. case 3:
  596. actual[i] = SRDS_PLLCR0_RFCK_SEL_161_13;
  597. break;
  598. }
  599. }
  600. for (i = 0; i < MAX_SERDES; i++) {
  601. srds_regs = srds_base + i * 0x1000;
  602. pllcr0 = srds_regs->bank[0].pllcr0;
  603. expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
  604. if (expected != actual[i]) {
  605. printf("Warning: SERDES%u expects reference clock %sMHz, but actual is %sMHz\n",
  606. i + 1, serdes_clock_to_string(expected),
  607. serdes_clock_to_string(actual[i]));
  608. }
  609. }
  610. return 0;
  611. }
  612. int ft_board_setup(void *blob, bd_t *bd)
  613. {
  614. phys_addr_t base;
  615. phys_size_t size;
  616. ft_cpu_setup(blob, bd);
  617. base = env_get_bootm_low();
  618. size = env_get_bootm_size();
  619. fdt_fixup_memory(blob, (u64)base, (u64)size);
  620. #ifdef CONFIG_PCI
  621. pci_of_setup(blob, bd);
  622. #endif
  623. fdt_fixup_liodn(blob);
  624. fsl_fdt_fixup_dr_usb(blob, bd);
  625. #ifdef CONFIG_SYS_DPAA_FMAN
  626. fdt_fixup_fman_ethernet(blob);
  627. fdt_fixup_board_enet(blob);
  628. #endif
  629. return 0;
  630. }
  631. /*
  632. * This function is called by bdinfo to print detail board information.
  633. * As an exmaple for future board, we organize the messages into
  634. * several sections. If applicable, the message is in the format of
  635. * <name> = <value>
  636. * It should aligned with normal output of bdinfo command.
  637. *
  638. * Voltage: Core, DDR and another configurable voltages
  639. * Clock : Critical clocks which are not printed already
  640. * RCW : RCW source if not printed already
  641. * Misc : Other important information not in above catagories
  642. */
  643. void board_detail(void)
  644. {
  645. int i;
  646. u8 brdcfg[16], dutcfg[16], rst_ctl;
  647. int vdd, rcwsrc;
  648. static const char * const clk[] = {"66.67", "100", "125", "133.33"};
  649. for (i = 0; i < 16; i++) {
  650. brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
  651. dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
  652. }
  653. /* Voltage secion */
  654. if (!select_i2c_ch_pca9547(I2C_MUX_CH_VOL_MONITOR)) {
  655. vdd = read_voltage();
  656. if (vdd > 0)
  657. printf("Core voltage= %d mV\n", vdd);
  658. select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
  659. }
  660. printf("XVDD = 1.%d V\n", ((brdcfg[8] & 0xf) - 4) * 5 + 25);
  661. /* clock section */
  662. printf("SYSCLK = %s MHz\nDDRCLK = %s MHz\n",
  663. clk[(brdcfg[11] >> 2) & 0x3], clk[brdcfg[11] & 3]);
  664. /* RCW section */
  665. rcwsrc = (dutcfg[0] << 1) + (dutcfg[1] & 1);
  666. puts("RCW source = ");
  667. switch (rcwsrc) {
  668. case 0x017:
  669. case 0x01f:
  670. puts("8-bit NOR\n");
  671. break;
  672. case 0x027:
  673. case 0x02F:
  674. puts("16-bit NOR\n");
  675. break;
  676. case 0x040:
  677. puts("SDHC/eMMC\n");
  678. break;
  679. case 0x044:
  680. puts("SPI 16-bit addressing\n");
  681. break;
  682. case 0x045:
  683. puts("SPI 24-bit addressing\n");
  684. break;
  685. case 0x048:
  686. puts("I2C normal addressing\n");
  687. break;
  688. case 0x049:
  689. puts("I2C extended addressing\n");
  690. break;
  691. case 0x108:
  692. case 0x109:
  693. case 0x10a:
  694. case 0x10b:
  695. puts("8-bit NAND, 2KB\n");
  696. break;
  697. default:
  698. if ((rcwsrc >= 0x080) && (rcwsrc <= 0x09f))
  699. puts("Hard-coded RCW\n");
  700. else if ((rcwsrc >= 0x110) && (rcwsrc <= 0x11f))
  701. puts("8-bit NAND, 4KB\n");
  702. else
  703. puts("unknown\n");
  704. break;
  705. }
  706. /* Misc section */
  707. rst_ctl = QIXIS_READ(rst_ctl);
  708. puts("HRESET_REQ = ");
  709. switch (rst_ctl & 0x30) {
  710. case 0x00:
  711. puts("Ignored\n");
  712. break;
  713. case 0x10:
  714. puts("Assert HRESET\n");
  715. break;
  716. case 0x30:
  717. puts("Reset system\n");
  718. break;
  719. default:
  720. puts("N/A\n");
  721. break;
  722. }
  723. }
  724. /*
  725. * Reverse engineering switch settings.
  726. * Some bits cannot be figured out. They will be displayed as
  727. * underscore in binary format. mask[] has those bits.
  728. * Some bits are calculated differently than the actual switches
  729. * if booting with overriding by FPGA.
  730. */
  731. void qixis_dump_switch(void)
  732. {
  733. int i;
  734. u8 sw[9];
  735. /*
  736. * Any bit with 1 means that bit cannot be reverse engineered.
  737. * It will be displayed as _ in binary format.
  738. */
  739. static const u8 mask[] = {0, 0, 0, 0, 0, 0x1, 0xcf, 0x3f, 0x1f};
  740. char buf[10];
  741. u8 brdcfg[16], dutcfg[16];
  742. for (i = 0; i < 16; i++) {
  743. brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
  744. dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
  745. }
  746. sw[0] = dutcfg[0];
  747. sw[1] = (dutcfg[1] << 0x07) |
  748. ((dutcfg[12] & 0xC0) >> 1) |
  749. ((dutcfg[11] & 0xE0) >> 3) |
  750. ((dutcfg[6] & 0x80) >> 6) |
  751. ((dutcfg[1] & 0x80) >> 7);
  752. sw[2] = ((brdcfg[1] & 0x0f) << 4) |
  753. ((brdcfg[1] & 0x30) >> 2) |
  754. ((brdcfg[1] & 0x40) >> 5) |
  755. ((brdcfg[1] & 0x80) >> 7);
  756. sw[3] = brdcfg[2];
  757. sw[4] = ((dutcfg[2] & 0x01) << 7) |
  758. ((dutcfg[2] & 0x06) << 4) |
  759. ((~QIXIS_READ(present)) & 0x10) |
  760. ((brdcfg[3] & 0x80) >> 4) |
  761. ((brdcfg[3] & 0x01) << 2) |
  762. ((brdcfg[6] == 0x62) ? 3 :
  763. ((brdcfg[6] == 0x5a) ? 2 :
  764. ((brdcfg[6] == 0x5e) ? 1 : 0)));
  765. sw[5] = ((brdcfg[0] & 0x0f) << 4) |
  766. ((QIXIS_READ(rst_ctl) & 0x30) >> 2) |
  767. ((brdcfg[0] & 0x40) >> 5);
  768. sw[6] = (brdcfg[11] & 0x20) |
  769. ((brdcfg[5] & 0x02) << 3);
  770. sw[7] = (((~QIXIS_READ(rst_ctl)) & 0x40) << 1) |
  771. ((brdcfg[5] & 0x10) << 2);
  772. sw[8] = ((brdcfg[12] & 0x08) << 4) |
  773. ((brdcfg[12] & 0x03) << 5);
  774. puts("DIP switch (reverse-engineering)\n");
  775. for (i = 0; i < 9; i++) {
  776. printf("SW%d = 0b%s (0x%02x)\n",
  777. i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
  778. }
  779. }
  780. static int do_vdd_adjust(cmd_tbl_t *cmdtp,
  781. int flag, int argc,
  782. char * const argv[])
  783. {
  784. ulong override;
  785. if (argc < 2)
  786. return CMD_RET_USAGE;
  787. if (!strict_strtoul(argv[1], 10, &override))
  788. adjust_vdd(override); /* the value is checked by callee */
  789. else
  790. return CMD_RET_USAGE;
  791. return 0;
  792. }
  793. U_BOOT_CMD(
  794. vdd_override, 2, 0, do_vdd_adjust,
  795. "Override VDD",
  796. "- override with the voltage specified in mV, eg. 1050"
  797. );