pxa2xx.c 6.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2002
  4. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  5. * Marius Groeger <mgroeger@sysgo.de>
  6. *
  7. * (C) Copyright 2002
  8. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  9. * Alex Zuepke <azu@sysgo.de>
  10. */
  11. #include <common.h>
  12. #include <cpu_func.h>
  13. #include <irq_func.h>
  14. #include <asm/arch/pxa-regs.h>
  15. #include <asm/io.h>
  16. #include <asm/system.h>
  17. #include <command.h>
  18. /* Flush I/D-cache */
  19. static void cache_flush(void)
  20. {
  21. unsigned long i = 0;
  22. asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i));
  23. }
  24. int cleanup_before_linux(void)
  25. {
  26. /*
  27. * This function is called just before we call Linux. It prepares
  28. * the processor for Linux by just disabling everything that can
  29. * disturb booting Linux.
  30. */
  31. disable_interrupts();
  32. icache_disable();
  33. dcache_disable();
  34. cache_flush();
  35. return 0;
  36. }
  37. inline void writelrb(uint32_t val, uint32_t addr)
  38. {
  39. writel(val, addr);
  40. asm volatile("" : : : "memory");
  41. readl(addr);
  42. asm volatile("" : : : "memory");
  43. }
  44. void pxa2xx_dram_init(void)
  45. {
  46. uint32_t tmp;
  47. int i;
  48. /*
  49. * 1) Initialize Asynchronous static memory controller
  50. */
  51. writelrb(CONFIG_SYS_MSC0_VAL, MSC0);
  52. writelrb(CONFIG_SYS_MSC1_VAL, MSC1);
  53. writelrb(CONFIG_SYS_MSC2_VAL, MSC2);
  54. /*
  55. * 2) Initialize Card Interface
  56. */
  57. /* MECR: Memory Expansion Card Register */
  58. writelrb(CONFIG_SYS_MECR_VAL, MECR);
  59. /* MCMEM0: Card Interface slot 0 timing */
  60. writelrb(CONFIG_SYS_MCMEM0_VAL, MCMEM0);
  61. /* MCMEM1: Card Interface slot 1 timing */
  62. writelrb(CONFIG_SYS_MCMEM1_VAL, MCMEM1);
  63. /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
  64. writelrb(CONFIG_SYS_MCATT0_VAL, MCATT0);
  65. /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
  66. writelrb(CONFIG_SYS_MCATT1_VAL, MCATT1);
  67. /* MCIO0: Card Interface I/O Space Timing, slot 0 */
  68. writelrb(CONFIG_SYS_MCIO0_VAL, MCIO0);
  69. /* MCIO1: Card Interface I/O Space Timing, slot 1 */
  70. writelrb(CONFIG_SYS_MCIO1_VAL, MCIO1);
  71. /*
  72. * 3) Configure Fly-By DMA register
  73. */
  74. writelrb(CONFIG_SYS_FLYCNFG_VAL, FLYCNFG);
  75. /*
  76. * 4) Initialize Timing for Sync Memory (SDCLK0)
  77. */
  78. /*
  79. * Before accessing MDREFR we need a valid DRI field, so we set
  80. * this to power on defaults + DRI field.
  81. */
  82. /* Read current MDREFR config and zero out DRI */
  83. tmp = readl(MDREFR) & ~0xfff;
  84. /* Add user-specified DRI */
  85. tmp |= CONFIG_SYS_MDREFR_VAL & 0xfff;
  86. /* Configure important bits */
  87. tmp |= MDREFR_K0RUN | MDREFR_SLFRSH;
  88. tmp &= ~(MDREFR_APD | MDREFR_E1PIN);
  89. /* Write MDREFR back */
  90. writelrb(tmp, MDREFR);
  91. /*
  92. * 5) Initialize Synchronous Static Memory (Flash/Peripherals)
  93. */
  94. /* Initialize SXCNFG register. Assert the enable bits.
  95. *
  96. * Write SXMRS to cause an MRS command to all enabled banks of
  97. * synchronous static memory. Note that SXLCR need not be written
  98. * at this time.
  99. */
  100. writelrb(CONFIG_SYS_SXCNFG_VAL, SXCNFG);
  101. /*
  102. * 6) Initialize SDRAM
  103. */
  104. writelrb(CONFIG_SYS_MDREFR_VAL & ~MDREFR_SLFRSH, MDREFR);
  105. writelrb(CONFIG_SYS_MDREFR_VAL | MDREFR_E1PIN, MDREFR);
  106. /*
  107. * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
  108. * but not enable each SDRAM partition pair.
  109. */
  110. writelrb(CONFIG_SYS_MDCNFG_VAL &
  111. ~(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3), MDCNFG);
  112. /* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
  113. writel(0, OSCR);
  114. while (readl(OSCR) < 0x300)
  115. asm volatile("" : : : "memory");
  116. /*
  117. * 8) Trigger a number (usually 8) refresh cycles by attempting
  118. * non-burst read or write accesses to disabled SDRAM, as commonly
  119. * specified in the power up sequence documented in SDRAM data
  120. * sheets. The address(es) used for this purpose must not be
  121. * cacheable.
  122. */
  123. for (i = 9; i >= 0; i--) {
  124. writel(i, 0xa0000000);
  125. asm volatile("" : : : "memory");
  126. }
  127. /*
  128. * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
  129. */
  130. tmp = CONFIG_SYS_MDCNFG_VAL &
  131. (MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3);
  132. tmp |= readl(MDCNFG);
  133. writelrb(tmp, MDCNFG);
  134. /*
  135. * 10) Write MDMRS.
  136. */
  137. writelrb(CONFIG_SYS_MDMRS_VAL, MDMRS);
  138. /*
  139. * 11) Enable APD
  140. */
  141. if (CONFIG_SYS_MDREFR_VAL & MDREFR_APD) {
  142. tmp = readl(MDREFR);
  143. tmp |= MDREFR_APD;
  144. writelrb(tmp, MDREFR);
  145. }
  146. }
  147. void pxa_gpio_setup(void)
  148. {
  149. writel(CONFIG_SYS_GPSR0_VAL, GPSR0);
  150. writel(CONFIG_SYS_GPSR1_VAL, GPSR1);
  151. writel(CONFIG_SYS_GPSR2_VAL, GPSR2);
  152. #if defined(CONFIG_CPU_PXA27X)
  153. writel(CONFIG_SYS_GPSR3_VAL, GPSR3);
  154. #endif
  155. writel(CONFIG_SYS_GPCR0_VAL, GPCR0);
  156. writel(CONFIG_SYS_GPCR1_VAL, GPCR1);
  157. writel(CONFIG_SYS_GPCR2_VAL, GPCR2);
  158. #if defined(CONFIG_CPU_PXA27X)
  159. writel(CONFIG_SYS_GPCR3_VAL, GPCR3);
  160. #endif
  161. writel(CONFIG_SYS_GPDR0_VAL, GPDR0);
  162. writel(CONFIG_SYS_GPDR1_VAL, GPDR1);
  163. writel(CONFIG_SYS_GPDR2_VAL, GPDR2);
  164. #if defined(CONFIG_CPU_PXA27X)
  165. writel(CONFIG_SYS_GPDR3_VAL, GPDR3);
  166. #endif
  167. writel(CONFIG_SYS_GAFR0_L_VAL, GAFR0_L);
  168. writel(CONFIG_SYS_GAFR0_U_VAL, GAFR0_U);
  169. writel(CONFIG_SYS_GAFR1_L_VAL, GAFR1_L);
  170. writel(CONFIG_SYS_GAFR1_U_VAL, GAFR1_U);
  171. writel(CONFIG_SYS_GAFR2_L_VAL, GAFR2_L);
  172. writel(CONFIG_SYS_GAFR2_U_VAL, GAFR2_U);
  173. #if defined(CONFIG_CPU_PXA27X)
  174. writel(CONFIG_SYS_GAFR3_L_VAL, GAFR3_L);
  175. writel(CONFIG_SYS_GAFR3_U_VAL, GAFR3_U);
  176. #endif
  177. writel(CONFIG_SYS_PSSR_VAL, PSSR);
  178. }
  179. void pxa_interrupt_setup(void)
  180. {
  181. writel(0, ICLR);
  182. writel(0, ICMR);
  183. #if defined(CONFIG_CPU_PXA27X)
  184. writel(0, ICLR2);
  185. writel(0, ICMR2);
  186. #endif
  187. }
  188. void pxa_clock_setup(void)
  189. {
  190. writel(CONFIG_SYS_CKEN, CKEN);
  191. writel(CONFIG_SYS_CCCR, CCCR);
  192. asm volatile("mcr p14, 0, %0, c6, c0, 0" : : "r"(0x0b));
  193. /* enable the 32Khz oscillator for RTC and PowerManager */
  194. writel(OSCC_OON, OSCC);
  195. while (!(readl(OSCC) & OSCC_OOK))
  196. asm volatile("" : : : "memory");
  197. }
  198. void pxa_wakeup(void)
  199. {
  200. uint32_t rcsr;
  201. rcsr = readl(RCSR);
  202. writel(rcsr & (RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR), RCSR);
  203. /* Wakeup */
  204. if (rcsr & RCSR_SMR) {
  205. writel(PSSR_PH, PSSR);
  206. pxa2xx_dram_init();
  207. icache_disable();
  208. dcache_disable();
  209. asm volatile("mov pc, %0" : : "r"(readl(PSPR)));
  210. }
  211. }
  212. int arch_cpu_init(void)
  213. {
  214. pxa_gpio_setup();
  215. pxa_wakeup();
  216. pxa_interrupt_setup();
  217. pxa_clock_setup();
  218. return 0;
  219. }
  220. void i2c_clk_enable(void)
  221. {
  222. /* Set the global I2C clock on */
  223. writel(readl(CKEN) | CKEN14_I2C, CKEN);
  224. }
  225. void __attribute__((weak)) reset_cpu(ulong ignored) __attribute__((noreturn));
  226. void reset_cpu(ulong ignored)
  227. {
  228. uint32_t tmp;
  229. setbits_le32(OWER, OWER_WME);
  230. tmp = readl(OSCR);
  231. tmp += 0x1000;
  232. writel(tmp, OSMR3);
  233. writel(MDREFR_SLFRSH, MDREFR);
  234. for (;;)
  235. ;
  236. }
  237. void enable_caches(void)
  238. {
  239. #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
  240. icache_enable();
  241. #endif
  242. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  243. dcache_enable();
  244. #endif
  245. }