zynqpl.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2012-2013, Xilinx, Michal Simek
  4. *
  5. * (C) Copyright 2012
  6. * Joe Hershberger <joe.hershberger@ni.com>
  7. */
  8. #include <common.h>
  9. #include <console.h>
  10. #include <cpu_func.h>
  11. #include <log.h>
  12. #include <asm/cache.h>
  13. #include <asm/io.h>
  14. #include <fs.h>
  15. #include <zynqpl.h>
  16. #include <linux/delay.h>
  17. #include <linux/sizes.h>
  18. #include <asm/arch/hardware.h>
  19. #include <asm/arch/sys_proto.h>
  20. #define DEVCFG_CTRL_PCFG_PROG_B 0x40000000
  21. #define DEVCFG_CTRL_PCFG_AES_EFUSE_MASK 0x00001000
  22. #define DEVCFG_CTRL_PCAP_RATE_EN_MASK 0x02000000
  23. #define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040
  24. #define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840
  25. #define DEVCFG_ISR_RX_FIFO_OV 0x00040000
  26. #define DEVCFG_ISR_DMA_DONE 0x00002000
  27. #define DEVCFG_ISR_PCFG_DONE 0x00000004
  28. #define DEVCFG_STATUS_DMA_CMD_Q_F 0x80000000
  29. #define DEVCFG_STATUS_DMA_CMD_Q_E 0x40000000
  30. #define DEVCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000
  31. #define DEVCFG_STATUS_PCFG_INIT 0x00000010
  32. #define DEVCFG_MCTRL_PCAP_LPBK 0x00000010
  33. #define DEVCFG_MCTRL_RFIFO_FLUSH 0x00000002
  34. #define DEVCFG_MCTRL_WFIFO_FLUSH 0x00000001
  35. #ifndef CONFIG_SYS_FPGA_WAIT
  36. #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
  37. #endif
  38. #ifndef CONFIG_SYS_FPGA_PROG_TIME
  39. #define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */
  40. #endif
  41. #define DUMMY_WORD 0xffffffff
  42. /* Xilinx binary format header */
  43. static const u32 bin_format[] = {
  44. DUMMY_WORD, /* Dummy words */
  45. DUMMY_WORD,
  46. DUMMY_WORD,
  47. DUMMY_WORD,
  48. DUMMY_WORD,
  49. DUMMY_WORD,
  50. DUMMY_WORD,
  51. DUMMY_WORD,
  52. 0x000000bb, /* Sync word */
  53. 0x11220044, /* Sync word */
  54. DUMMY_WORD,
  55. DUMMY_WORD,
  56. 0xaa995566, /* Sync word */
  57. };
  58. #define SWAP_NO 1
  59. #define SWAP_DONE 2
  60. /*
  61. * Load the whole word from unaligned buffer
  62. * Keep in your mind that it is byte loading on little-endian system
  63. */
  64. static u32 load_word(const void *buf, u32 swap)
  65. {
  66. u32 word = 0;
  67. u8 *bitc = (u8 *)buf;
  68. int p;
  69. if (swap == SWAP_NO) {
  70. for (p = 0; p < 4; p++) {
  71. word <<= 8;
  72. word |= bitc[p];
  73. }
  74. } else {
  75. for (p = 3; p >= 0; p--) {
  76. word <<= 8;
  77. word |= bitc[p];
  78. }
  79. }
  80. return word;
  81. }
  82. static u32 check_header(const void *buf)
  83. {
  84. u32 i, pattern;
  85. int swap = SWAP_NO;
  86. u32 *test = (u32 *)buf;
  87. debug("%s: Let's check bitstream header\n", __func__);
  88. /* Checking that passing bin is not a bitstream */
  89. for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
  90. pattern = load_word(&test[i], swap);
  91. /*
  92. * Bitstreams in binary format are swapped
  93. * compare to regular bistream.
  94. * Do not swap dummy word but if swap is done assume
  95. * that parsing buffer is binary format
  96. */
  97. if ((__swab32(pattern) != DUMMY_WORD) &&
  98. (__swab32(pattern) == bin_format[i])) {
  99. pattern = __swab32(pattern);
  100. swap = SWAP_DONE;
  101. debug("%s: data swapped - let's swap\n", __func__);
  102. }
  103. debug("%s: %d/%x: pattern %x/%x bin_format\n", __func__, i,
  104. (u32)&test[i], pattern, bin_format[i]);
  105. if (pattern != bin_format[i]) {
  106. debug("%s: Bitstream is not recognized\n", __func__);
  107. return 0;
  108. }
  109. }
  110. debug("%s: Found bitstream header at %x %s swapinng\n", __func__,
  111. (u32)buf, swap == SWAP_NO ? "without" : "with");
  112. return swap;
  113. }
  114. static void *check_data(u8 *buf, size_t bsize, u32 *swap)
  115. {
  116. u32 word, p = 0; /* possition */
  117. /* Because buf doesn't need to be aligned let's read it by chars */
  118. for (p = 0; p < bsize; p++) {
  119. word = load_word(&buf[p], SWAP_NO);
  120. debug("%s: word %x %x/%x\n", __func__, word, p, (u32)&buf[p]);
  121. /* Find the first bitstream dummy word */
  122. if (word == DUMMY_WORD) {
  123. debug("%s: Found dummy word at position %x/%x\n",
  124. __func__, p, (u32)&buf[p]);
  125. *swap = check_header(&buf[p]);
  126. if (*swap) {
  127. /* FIXME add full bitstream checking here */
  128. return &buf[p];
  129. }
  130. }
  131. /* Loop can be huge - support CTRL + C */
  132. if (ctrlc())
  133. return NULL;
  134. }
  135. return NULL;
  136. }
  137. static int zynq_dma_transfer(u32 srcbuf, u32 srclen, u32 dstbuf, u32 dstlen)
  138. {
  139. unsigned long ts;
  140. u32 isr_status;
  141. /* Set up the transfer */
  142. writel((u32)srcbuf, &devcfg_base->dma_src_addr);
  143. writel(dstbuf, &devcfg_base->dma_dst_addr);
  144. writel(srclen, &devcfg_base->dma_src_len);
  145. writel(dstlen, &devcfg_base->dma_dst_len);
  146. isr_status = readl(&devcfg_base->int_sts);
  147. /* Polling the PCAP_INIT status for Set */
  148. ts = get_timer(0);
  149. while (!(isr_status & DEVCFG_ISR_DMA_DONE)) {
  150. if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) {
  151. debug("%s: Error: isr = 0x%08X\n", __func__,
  152. isr_status);
  153. debug("%s: Write count = 0x%08X\n", __func__,
  154. readl(&devcfg_base->write_count));
  155. debug("%s: Read count = 0x%08X\n", __func__,
  156. readl(&devcfg_base->read_count));
  157. return FPGA_FAIL;
  158. }
  159. if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) {
  160. printf("%s: Timeout wait for DMA to complete\n",
  161. __func__);
  162. return FPGA_FAIL;
  163. }
  164. isr_status = readl(&devcfg_base->int_sts);
  165. }
  166. debug("%s: DMA transfer is done\n", __func__);
  167. /* Clear out the DMA status */
  168. writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
  169. return FPGA_SUCCESS;
  170. }
  171. static int zynq_dma_xfer_init(bitstream_type bstype)
  172. {
  173. u32 status, control, isr_status;
  174. unsigned long ts;
  175. /* Clear loopback bit */
  176. clrbits_le32(&devcfg_base->mctrl, DEVCFG_MCTRL_PCAP_LPBK);
  177. if (bstype != BIT_PARTIAL && bstype != BIT_NONE) {
  178. zynq_slcr_devcfg_disable();
  179. /* Setting PCFG_PROG_B signal to high */
  180. control = readl(&devcfg_base->ctrl);
  181. writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
  182. /*
  183. * Delay is required if AES efuse is selected as
  184. * key source.
  185. */
  186. if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK)
  187. mdelay(5);
  188. /* Setting PCFG_PROG_B signal to low */
  189. writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
  190. /*
  191. * Delay is required if AES efuse is selected as
  192. * key source.
  193. */
  194. if (control & DEVCFG_CTRL_PCFG_AES_EFUSE_MASK)
  195. mdelay(5);
  196. /* Polling the PCAP_INIT status for Reset */
  197. ts = get_timer(0);
  198. while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) {
  199. if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
  200. printf("%s: Timeout wait for INIT to clear\n",
  201. __func__);
  202. return FPGA_FAIL;
  203. }
  204. }
  205. /* Setting PCFG_PROG_B signal to high */
  206. writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
  207. /* Polling the PCAP_INIT status for Set */
  208. ts = get_timer(0);
  209. while (!(readl(&devcfg_base->status) &
  210. DEVCFG_STATUS_PCFG_INIT)) {
  211. if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
  212. printf("%s: Timeout wait for INIT to set\n",
  213. __func__);
  214. return FPGA_FAIL;
  215. }
  216. }
  217. }
  218. isr_status = readl(&devcfg_base->int_sts);
  219. /* Clear it all, so if Boot ROM comes back, it can proceed */
  220. writel(0xFFFFFFFF, &devcfg_base->int_sts);
  221. if (isr_status & DEVCFG_ISR_FATAL_ERROR_MASK) {
  222. debug("%s: Fatal errors in PCAP 0x%X\n", __func__, isr_status);
  223. /* If RX FIFO overflow, need to flush RX FIFO first */
  224. if (isr_status & DEVCFG_ISR_RX_FIFO_OV) {
  225. writel(DEVCFG_MCTRL_RFIFO_FLUSH, &devcfg_base->mctrl);
  226. writel(0xFFFFFFFF, &devcfg_base->int_sts);
  227. }
  228. return FPGA_FAIL;
  229. }
  230. status = readl(&devcfg_base->status);
  231. debug("%s: Status = 0x%08X\n", __func__, status);
  232. if (status & DEVCFG_STATUS_DMA_CMD_Q_F) {
  233. debug("%s: Error: device busy\n", __func__);
  234. return FPGA_FAIL;
  235. }
  236. debug("%s: Device ready\n", __func__);
  237. if (!(status & DEVCFG_STATUS_DMA_CMD_Q_E)) {
  238. if (!(readl(&devcfg_base->int_sts) & DEVCFG_ISR_DMA_DONE)) {
  239. /* Error state, transfer cannot occur */
  240. debug("%s: ISR indicates error\n", __func__);
  241. return FPGA_FAIL;
  242. } else {
  243. /* Clear out the status */
  244. writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
  245. }
  246. }
  247. if (status & DEVCFG_STATUS_DMA_DONE_CNT_MASK) {
  248. /* Clear the count of completed DMA transfers */
  249. writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status);
  250. }
  251. return FPGA_SUCCESS;
  252. }
  253. static u32 *zynq_align_dma_buffer(u32 *buf, u32 len, u32 swap)
  254. {
  255. u32 *new_buf;
  256. u32 i;
  257. if ((u32)buf != ALIGN((u32)buf, ARCH_DMA_MINALIGN)) {
  258. new_buf = (u32 *)ALIGN((u32)buf, ARCH_DMA_MINALIGN);
  259. /*
  260. * This might be dangerous but permits to flash if
  261. * ARCH_DMA_MINALIGN is greater than header size
  262. */
  263. if (new_buf > buf) {
  264. debug("%s: Aligned buffer is after buffer start\n",
  265. __func__);
  266. new_buf -= ARCH_DMA_MINALIGN;
  267. }
  268. printf("%s: Align buffer at %x to %x(swap %d)\n", __func__,
  269. (u32)buf, (u32)new_buf, swap);
  270. for (i = 0; i < (len/4); i++)
  271. new_buf[i] = load_word(&buf[i], swap);
  272. buf = new_buf;
  273. } else if (swap != SWAP_DONE) {
  274. /* For bitstream which are aligned */
  275. u32 *new_buf = (u32 *)buf;
  276. printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
  277. swap);
  278. for (i = 0; i < (len/4); i++)
  279. new_buf[i] = load_word(&buf[i], swap);
  280. }
  281. return buf;
  282. }
  283. static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf,
  284. size_t bsize, u32 blocksize, u32 *swap,
  285. bitstream_type *bstype)
  286. {
  287. u32 *buf_start;
  288. u32 diff;
  289. buf_start = check_data((u8 *)buf, blocksize, swap);
  290. if (!buf_start)
  291. return FPGA_FAIL;
  292. /* Check if data is postpone from start */
  293. diff = (u32)buf_start - (u32)buf;
  294. if (diff) {
  295. printf("%s: Bitstream is not validated yet (diff %x)\n",
  296. __func__, diff);
  297. return FPGA_FAIL;
  298. }
  299. if ((u32)buf < SZ_1M) {
  300. printf("%s: Bitstream has to be placed up to 1MB (%x)\n",
  301. __func__, (u32)buf);
  302. return FPGA_FAIL;
  303. }
  304. if (zynq_dma_xfer_init(*bstype))
  305. return FPGA_FAIL;
  306. return 0;
  307. }
  308. static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize,
  309. bitstream_type bstype)
  310. {
  311. unsigned long ts; /* Timestamp */
  312. u32 isr_status, swap;
  313. /*
  314. * send bsize inplace of blocksize as it was not a bitstream
  315. * in chunks
  316. */
  317. if (zynq_validate_bitstream(desc, buf, bsize, bsize, &swap,
  318. &bstype))
  319. return FPGA_FAIL;
  320. buf = zynq_align_dma_buffer((u32 *)buf, bsize, swap);
  321. debug("%s: Source = 0x%08X\n", __func__, (u32)buf);
  322. debug("%s: Size = %zu\n", __func__, bsize);
  323. /* flush(clean & invalidate) d-cache range buf */
  324. flush_dcache_range((u32)buf, (u32)buf +
  325. roundup(bsize, ARCH_DMA_MINALIGN));
  326. if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0))
  327. return FPGA_FAIL;
  328. isr_status = readl(&devcfg_base->int_sts);
  329. /* Check FPGA configuration completion */
  330. ts = get_timer(0);
  331. while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
  332. if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
  333. printf("%s: Timeout wait for FPGA to config\n",
  334. __func__);
  335. return FPGA_FAIL;
  336. }
  337. isr_status = readl(&devcfg_base->int_sts);
  338. }
  339. debug("%s: FPGA config done\n", __func__);
  340. if (bstype != BIT_PARTIAL)
  341. zynq_slcr_devcfg_enable();
  342. puts("INFO:post config was not run, please run manually if needed\n");
  343. return FPGA_SUCCESS;
  344. }
  345. #if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_SPL_BUILD)
  346. static int zynq_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
  347. fpga_fs_info *fsinfo)
  348. {
  349. unsigned long ts; /* Timestamp */
  350. u32 isr_status, swap;
  351. u32 partialbit = 0;
  352. loff_t blocksize, actread;
  353. loff_t pos = 0;
  354. int fstype;
  355. char *interface, *dev_part;
  356. const char *filename;
  357. blocksize = fsinfo->blocksize;
  358. interface = fsinfo->interface;
  359. dev_part = fsinfo->dev_part;
  360. filename = fsinfo->filename;
  361. fstype = fsinfo->fstype;
  362. if (fs_set_blk_dev(interface, dev_part, fstype))
  363. return FPGA_FAIL;
  364. if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0)
  365. return FPGA_FAIL;
  366. if (zynq_validate_bitstream(desc, buf, bsize, blocksize, &swap,
  367. &partialbit))
  368. return FPGA_FAIL;
  369. dcache_disable();
  370. do {
  371. buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap);
  372. if (zynq_dma_transfer((u32)buf | 1, blocksize >> 2,
  373. 0xffffffff, 0))
  374. return FPGA_FAIL;
  375. bsize -= blocksize;
  376. pos += blocksize;
  377. if (fs_set_blk_dev(interface, dev_part, fstype))
  378. return FPGA_FAIL;
  379. if (bsize > blocksize) {
  380. if (fs_read(filename, (u32) buf, pos, blocksize, &actread) < 0)
  381. return FPGA_FAIL;
  382. } else {
  383. if (fs_read(filename, (u32) buf, pos, bsize, &actread) < 0)
  384. return FPGA_FAIL;
  385. }
  386. } while (bsize > blocksize);
  387. buf = zynq_align_dma_buffer((u32 *)buf, blocksize, swap);
  388. if (zynq_dma_transfer((u32)buf | 1, bsize >> 2, 0xffffffff, 0))
  389. return FPGA_FAIL;
  390. dcache_enable();
  391. isr_status = readl(&devcfg_base->int_sts);
  392. /* Check FPGA configuration completion */
  393. ts = get_timer(0);
  394. while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
  395. if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
  396. printf("%s: Timeout wait for FPGA to config\n",
  397. __func__);
  398. return FPGA_FAIL;
  399. }
  400. isr_status = readl(&devcfg_base->int_sts);
  401. }
  402. debug("%s: FPGA config done\n", __func__);
  403. if (!partialbit)
  404. zynq_slcr_devcfg_enable();
  405. return FPGA_SUCCESS;
  406. }
  407. #endif
  408. struct xilinx_fpga_op zynq_op = {
  409. .load = zynq_load,
  410. #if defined(CONFIG_CMD_FPGA_LOADFS) && !defined(CONFIG_SPL_BUILD)
  411. .loadfs = zynq_loadfs,
  412. #endif
  413. };
  414. #ifdef CONFIG_CMD_ZYNQ_AES
  415. /*
  416. * Load the encrypted image from src addr and decrypt the image and
  417. * place it back the decrypted image into dstaddr.
  418. */
  419. int zynq_decrypt_load(u32 srcaddr, u32 srclen, u32 dstaddr, u32 dstlen,
  420. u8 bstype)
  421. {
  422. if (srcaddr < SZ_1M || dstaddr < SZ_1M) {
  423. printf("%s: src and dst addr should be > 1M\n",
  424. __func__);
  425. return FPGA_FAIL;
  426. }
  427. if (zynq_dma_xfer_init(bstype)) {
  428. printf("%s: zynq_dma_xfer_init FAIL\n", __func__);
  429. return FPGA_FAIL;
  430. }
  431. writel((readl(&devcfg_base->ctrl) | DEVCFG_CTRL_PCAP_RATE_EN_MASK),
  432. &devcfg_base->ctrl);
  433. debug("%s: Source = 0x%08X\n", __func__, (u32)srcaddr);
  434. debug("%s: Size = %zu\n", __func__, srclen);
  435. /* flush(clean & invalidate) d-cache range buf */
  436. flush_dcache_range((u32)srcaddr, (u32)srcaddr +
  437. roundup(srclen << 2, ARCH_DMA_MINALIGN));
  438. /*
  439. * Flush destination address range only if image is not
  440. * bitstream.
  441. */
  442. flush_dcache_range((u32)dstaddr, (u32)dstaddr +
  443. roundup(dstlen << 2, ARCH_DMA_MINALIGN));
  444. if (zynq_dma_transfer(srcaddr | 1, srclen, dstaddr | 1, dstlen))
  445. return FPGA_FAIL;
  446. writel((readl(&devcfg_base->ctrl) & ~DEVCFG_CTRL_PCAP_RATE_EN_MASK),
  447. &devcfg_base->ctrl);
  448. return FPGA_SUCCESS;
  449. }
  450. #endif