spi-sifive.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2018 SiFive, Inc.
  4. * Copyright 2019 Bhargav Shah <bhargavshah1988@gmail.com>
  5. *
  6. * SiFive SPI controller driver (master mode only)
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <dm/device_compat.h>
  11. #include <malloc.h>
  12. #include <spi.h>
  13. #include <spi-mem.h>
  14. #include <wait_bit.h>
  15. #include <asm/io.h>
  16. #include <linux/bitops.h>
  17. #include <linux/log2.h>
  18. #include <clk.h>
  19. #define SIFIVE_SPI_MAX_CS 32
  20. #define SIFIVE_SPI_DEFAULT_DEPTH 8
  21. #define SIFIVE_SPI_DEFAULT_BITS 8
  22. /* register offsets */
  23. #define SIFIVE_SPI_REG_SCKDIV 0x00 /* Serial clock divisor */
  24. #define SIFIVE_SPI_REG_SCKMODE 0x04 /* Serial clock mode */
  25. #define SIFIVE_SPI_REG_CSID 0x10 /* Chip select ID */
  26. #define SIFIVE_SPI_REG_CSDEF 0x14 /* Chip select default */
  27. #define SIFIVE_SPI_REG_CSMODE 0x18 /* Chip select mode */
  28. #define SIFIVE_SPI_REG_DELAY0 0x28 /* Delay control 0 */
  29. #define SIFIVE_SPI_REG_DELAY1 0x2c /* Delay control 1 */
  30. #define SIFIVE_SPI_REG_FMT 0x40 /* Frame format */
  31. #define SIFIVE_SPI_REG_TXDATA 0x48 /* Tx FIFO data */
  32. #define SIFIVE_SPI_REG_RXDATA 0x4c /* Rx FIFO data */
  33. #define SIFIVE_SPI_REG_TXMARK 0x50 /* Tx FIFO watermark */
  34. #define SIFIVE_SPI_REG_RXMARK 0x54 /* Rx FIFO watermark */
  35. #define SIFIVE_SPI_REG_FCTRL 0x60 /* SPI flash interface control */
  36. #define SIFIVE_SPI_REG_FFMT 0x64 /* SPI flash instruction format */
  37. #define SIFIVE_SPI_REG_IE 0x70 /* Interrupt Enable Register */
  38. #define SIFIVE_SPI_REG_IP 0x74 /* Interrupt Pendings Register */
  39. /* sckdiv bits */
  40. #define SIFIVE_SPI_SCKDIV_DIV_MASK 0xfffU
  41. /* sckmode bits */
  42. #define SIFIVE_SPI_SCKMODE_PHA BIT(0)
  43. #define SIFIVE_SPI_SCKMODE_POL BIT(1)
  44. #define SIFIVE_SPI_SCKMODE_MODE_MASK (SIFIVE_SPI_SCKMODE_PHA | \
  45. SIFIVE_SPI_SCKMODE_POL)
  46. /* csmode bits */
  47. #define SIFIVE_SPI_CSMODE_MODE_AUTO 0U
  48. #define SIFIVE_SPI_CSMODE_MODE_HOLD 2U
  49. #define SIFIVE_SPI_CSMODE_MODE_OFF 3U
  50. /* delay0 bits */
  51. #define SIFIVE_SPI_DELAY0_CSSCK(x) ((u32)(x))
  52. #define SIFIVE_SPI_DELAY0_CSSCK_MASK 0xffU
  53. #define SIFIVE_SPI_DELAY0_SCKCS(x) ((u32)(x) << 16)
  54. #define SIFIVE_SPI_DELAY0_SCKCS_MASK (0xffU << 16)
  55. /* delay1 bits */
  56. #define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x))
  57. #define SIFIVE_SPI_DELAY1_INTERCS_MASK 0xffU
  58. #define SIFIVE_SPI_DELAY1_INTERXFR(x) ((u32)(x) << 16)
  59. #define SIFIVE_SPI_DELAY1_INTERXFR_MASK (0xffU << 16)
  60. /* fmt bits */
  61. #define SIFIVE_SPI_FMT_PROTO_SINGLE 0U
  62. #define SIFIVE_SPI_FMT_PROTO_DUAL 1U
  63. #define SIFIVE_SPI_FMT_PROTO_QUAD 2U
  64. #define SIFIVE_SPI_FMT_PROTO_MASK 3U
  65. #define SIFIVE_SPI_FMT_ENDIAN BIT(2)
  66. #define SIFIVE_SPI_FMT_DIR BIT(3)
  67. #define SIFIVE_SPI_FMT_LEN(x) ((u32)(x) << 16)
  68. #define SIFIVE_SPI_FMT_LEN_MASK (0xfU << 16)
  69. /* txdata bits */
  70. #define SIFIVE_SPI_TXDATA_DATA_MASK 0xffU
  71. #define SIFIVE_SPI_TXDATA_FULL BIT(31)
  72. /* rxdata bits */
  73. #define SIFIVE_SPI_RXDATA_DATA_MASK 0xffU
  74. #define SIFIVE_SPI_RXDATA_EMPTY BIT(31)
  75. /* ie and ip bits */
  76. #define SIFIVE_SPI_IP_TXWM BIT(0)
  77. #define SIFIVE_SPI_IP_RXWM BIT(1)
  78. /* format protocol */
  79. #define SIFIVE_SPI_PROTO_QUAD 4 /* 4 lines I/O protocol transfer */
  80. #define SIFIVE_SPI_PROTO_DUAL 2 /* 2 lines I/O protocol transfer */
  81. #define SIFIVE_SPI_PROTO_SINGLE 1 /* 1 line I/O protocol transfer */
  82. struct sifive_spi {
  83. void *regs; /* base address of the registers */
  84. u32 fifo_depth;
  85. u32 bits_per_word;
  86. u32 cs_inactive; /* Level of the CS pins when inactive*/
  87. u32 freq;
  88. u32 num_cs;
  89. u8 fmt_proto;
  90. };
  91. static void sifive_spi_prep_device(struct sifive_spi *spi,
  92. struct dm_spi_slave_platdata *slave_plat)
  93. {
  94. /* Update the chip select polarity */
  95. if (slave_plat->mode & SPI_CS_HIGH)
  96. spi->cs_inactive &= ~BIT(slave_plat->cs);
  97. else
  98. spi->cs_inactive |= BIT(slave_plat->cs);
  99. writel(spi->cs_inactive, spi->regs + SIFIVE_SPI_REG_CSDEF);
  100. /* Select the correct device */
  101. writel(slave_plat->cs, spi->regs + SIFIVE_SPI_REG_CSID);
  102. }
  103. static int sifive_spi_set_cs(struct sifive_spi *spi,
  104. struct dm_spi_slave_platdata *slave_plat)
  105. {
  106. u32 cs_mode = SIFIVE_SPI_CSMODE_MODE_HOLD;
  107. if (slave_plat->mode & SPI_CS_HIGH)
  108. cs_mode = SIFIVE_SPI_CSMODE_MODE_AUTO;
  109. writel(cs_mode, spi->regs + SIFIVE_SPI_REG_CSMODE);
  110. return 0;
  111. }
  112. static void sifive_spi_clear_cs(struct sifive_spi *spi)
  113. {
  114. writel(SIFIVE_SPI_CSMODE_MODE_AUTO, spi->regs + SIFIVE_SPI_REG_CSMODE);
  115. }
  116. static void sifive_spi_prep_transfer(struct sifive_spi *spi,
  117. struct dm_spi_slave_platdata *slave_plat,
  118. u8 *rx_ptr)
  119. {
  120. u32 cr;
  121. /* Modify the SPI protocol mode */
  122. cr = readl(spi->regs + SIFIVE_SPI_REG_FMT);
  123. /* Bits per word ? */
  124. cr &= ~SIFIVE_SPI_FMT_LEN_MASK;
  125. cr |= SIFIVE_SPI_FMT_LEN(spi->bits_per_word);
  126. /* LSB first? */
  127. cr &= ~SIFIVE_SPI_FMT_ENDIAN;
  128. if (slave_plat->mode & SPI_LSB_FIRST)
  129. cr |= SIFIVE_SPI_FMT_ENDIAN;
  130. /* Number of wires ? */
  131. cr &= ~SIFIVE_SPI_FMT_PROTO_MASK;
  132. switch (spi->fmt_proto) {
  133. case SIFIVE_SPI_PROTO_QUAD:
  134. cr |= SIFIVE_SPI_FMT_PROTO_QUAD;
  135. break;
  136. case SIFIVE_SPI_PROTO_DUAL:
  137. cr |= SIFIVE_SPI_FMT_PROTO_DUAL;
  138. break;
  139. default:
  140. cr |= SIFIVE_SPI_FMT_PROTO_SINGLE;
  141. break;
  142. }
  143. /* SPI direction in/out ? */
  144. cr &= ~SIFIVE_SPI_FMT_DIR;
  145. if (!rx_ptr)
  146. cr |= SIFIVE_SPI_FMT_DIR;
  147. writel(cr, spi->regs + SIFIVE_SPI_REG_FMT);
  148. }
  149. static void sifive_spi_rx(struct sifive_spi *spi, u8 *rx_ptr)
  150. {
  151. u32 data;
  152. do {
  153. data = readl(spi->regs + SIFIVE_SPI_REG_RXDATA);
  154. } while (data & SIFIVE_SPI_RXDATA_EMPTY);
  155. if (rx_ptr)
  156. *rx_ptr = data & SIFIVE_SPI_RXDATA_DATA_MASK;
  157. }
  158. static void sifive_spi_tx(struct sifive_spi *spi, const u8 *tx_ptr)
  159. {
  160. u32 data;
  161. u8 tx_data = (tx_ptr) ? *tx_ptr & SIFIVE_SPI_TXDATA_DATA_MASK :
  162. SIFIVE_SPI_TXDATA_DATA_MASK;
  163. do {
  164. data = readl(spi->regs + SIFIVE_SPI_REG_TXDATA);
  165. } while (data & SIFIVE_SPI_TXDATA_FULL);
  166. writel(tx_data, spi->regs + SIFIVE_SPI_REG_TXDATA);
  167. }
  168. static int sifive_spi_wait(struct sifive_spi *spi, u32 bit)
  169. {
  170. return wait_for_bit_le32(spi->regs + SIFIVE_SPI_REG_IP,
  171. bit, true, 100, false);
  172. }
  173. static int sifive_spi_xfer(struct udevice *dev, unsigned int bitlen,
  174. const void *dout, void *din, unsigned long flags)
  175. {
  176. struct udevice *bus = dev->parent;
  177. struct sifive_spi *spi = dev_get_priv(bus);
  178. struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
  179. const u8 *tx_ptr = dout;
  180. u8 *rx_ptr = din;
  181. u32 remaining_len;
  182. int ret;
  183. if (flags & SPI_XFER_BEGIN) {
  184. sifive_spi_prep_device(spi, slave_plat);
  185. ret = sifive_spi_set_cs(spi, slave_plat);
  186. if (ret)
  187. return ret;
  188. }
  189. sifive_spi_prep_transfer(spi, slave_plat, rx_ptr);
  190. remaining_len = bitlen / 8;
  191. while (remaining_len) {
  192. unsigned int n_words = min(remaining_len, spi->fifo_depth);
  193. unsigned int tx_words, rx_words;
  194. /* Enqueue n_words for transmission */
  195. for (tx_words = 0; tx_words < n_words; tx_words++) {
  196. if (!tx_ptr)
  197. sifive_spi_tx(spi, NULL);
  198. else
  199. sifive_spi_tx(spi, tx_ptr++);
  200. }
  201. if (rx_ptr) {
  202. /* Wait for transmission + reception to complete */
  203. writel(n_words - 1, spi->regs + SIFIVE_SPI_REG_RXMARK);
  204. ret = sifive_spi_wait(spi, SIFIVE_SPI_IP_RXWM);
  205. if (ret)
  206. return ret;
  207. /* Read out all the data from the RX FIFO */
  208. for (rx_words = 0; rx_words < n_words; rx_words++)
  209. sifive_spi_rx(spi, rx_ptr++);
  210. } else {
  211. /* Wait for transmission to complete */
  212. ret = sifive_spi_wait(spi, SIFIVE_SPI_IP_TXWM);
  213. if (ret)
  214. return ret;
  215. }
  216. remaining_len -= n_words;
  217. }
  218. if (flags & SPI_XFER_END)
  219. sifive_spi_clear_cs(spi);
  220. return 0;
  221. }
  222. static int sifive_spi_exec_op(struct spi_slave *slave,
  223. const struct spi_mem_op *op)
  224. {
  225. struct udevice *dev = slave->dev;
  226. struct sifive_spi *spi = dev_get_priv(dev->parent);
  227. unsigned long flags = SPI_XFER_BEGIN;
  228. u8 opcode = op->cmd.opcode;
  229. unsigned int pos = 0;
  230. const void *tx_buf = NULL;
  231. void *rx_buf = NULL;
  232. int op_len, i;
  233. int ret;
  234. if (!op->addr.nbytes && !op->dummy.nbytes && !op->data.nbytes)
  235. flags |= SPI_XFER_END;
  236. spi->fmt_proto = op->cmd.buswidth;
  237. /* send the opcode */
  238. ret = sifive_spi_xfer(dev, 8, (void *)&opcode, NULL, flags);
  239. if (ret < 0) {
  240. dev_err(dev, "failed to xfer opcode\n");
  241. return ret;
  242. }
  243. op_len = op->addr.nbytes + op->dummy.nbytes;
  244. u8 op_buf[op_len];
  245. /* send the addr + dummy */
  246. if (op->addr.nbytes) {
  247. /* fill address */
  248. for (i = 0; i < op->addr.nbytes; i++)
  249. op_buf[pos + i] = op->addr.val >>
  250. (8 * (op->addr.nbytes - i - 1));
  251. pos += op->addr.nbytes;
  252. /* fill dummy */
  253. if (op->dummy.nbytes)
  254. memset(op_buf + pos, 0xff, op->dummy.nbytes);
  255. /* make sure to set end flag, if no data bytes */
  256. if (!op->data.nbytes)
  257. flags |= SPI_XFER_END;
  258. spi->fmt_proto = op->addr.buswidth;
  259. ret = sifive_spi_xfer(dev, op_len * 8, op_buf, NULL, flags);
  260. if (ret < 0) {
  261. dev_err(dev, "failed to xfer addr + dummy\n");
  262. return ret;
  263. }
  264. }
  265. /* send/received the data */
  266. if (op->data.nbytes) {
  267. if (op->data.dir == SPI_MEM_DATA_IN)
  268. rx_buf = op->data.buf.in;
  269. else
  270. tx_buf = op->data.buf.out;
  271. spi->fmt_proto = op->data.buswidth;
  272. ret = sifive_spi_xfer(dev, op->data.nbytes * 8,
  273. tx_buf, rx_buf, SPI_XFER_END);
  274. if (ret) {
  275. dev_err(dev, "failed to xfer data\n");
  276. return ret;
  277. }
  278. }
  279. return 0;
  280. }
  281. static int sifive_spi_set_speed(struct udevice *bus, uint speed)
  282. {
  283. struct sifive_spi *spi = dev_get_priv(bus);
  284. u32 scale;
  285. if (speed > spi->freq)
  286. speed = spi->freq;
  287. /* Cofigure max speed */
  288. scale = (DIV_ROUND_UP(spi->freq >> 1, speed) - 1)
  289. & SIFIVE_SPI_SCKDIV_DIV_MASK;
  290. writel(scale, spi->regs + SIFIVE_SPI_REG_SCKDIV);
  291. return 0;
  292. }
  293. static int sifive_spi_set_mode(struct udevice *bus, uint mode)
  294. {
  295. struct sifive_spi *spi = dev_get_priv(bus);
  296. u32 cr;
  297. /* Switch clock mode bits */
  298. cr = readl(spi->regs + SIFIVE_SPI_REG_SCKMODE) &
  299. ~SIFIVE_SPI_SCKMODE_MODE_MASK;
  300. if (mode & SPI_CPHA)
  301. cr |= SIFIVE_SPI_SCKMODE_PHA;
  302. if (mode & SPI_CPOL)
  303. cr |= SIFIVE_SPI_SCKMODE_POL;
  304. writel(cr, spi->regs + SIFIVE_SPI_REG_SCKMODE);
  305. return 0;
  306. }
  307. static int sifive_spi_cs_info(struct udevice *bus, uint cs,
  308. struct spi_cs_info *info)
  309. {
  310. struct sifive_spi *spi = dev_get_priv(bus);
  311. if (cs >= spi->num_cs)
  312. return -EINVAL;
  313. return 0;
  314. }
  315. static void sifive_spi_init_hw(struct sifive_spi *spi)
  316. {
  317. u32 cs_bits;
  318. /* probe the number of CS lines */
  319. spi->cs_inactive = readl(spi->regs + SIFIVE_SPI_REG_CSDEF);
  320. writel(0xffffffffU, spi->regs + SIFIVE_SPI_REG_CSDEF);
  321. cs_bits = readl(spi->regs + SIFIVE_SPI_REG_CSDEF);
  322. writel(spi->cs_inactive, spi->regs + SIFIVE_SPI_REG_CSDEF);
  323. if (!cs_bits) {
  324. printf("Could not auto probe CS lines\n");
  325. return;
  326. }
  327. spi->num_cs = ilog2(cs_bits) + 1;
  328. if (spi->num_cs > SIFIVE_SPI_MAX_CS) {
  329. printf("Invalid number of spi slaves\n");
  330. return;
  331. }
  332. /* Watermark interrupts are disabled by default */
  333. writel(0, spi->regs + SIFIVE_SPI_REG_IE);
  334. /* Default watermark FIFO threshold values */
  335. writel(1, spi->regs + SIFIVE_SPI_REG_TXMARK);
  336. writel(0, spi->regs + SIFIVE_SPI_REG_RXMARK);
  337. /* Set CS/SCK Delays and Inactive Time to defaults */
  338. writel(SIFIVE_SPI_DELAY0_CSSCK(1) | SIFIVE_SPI_DELAY0_SCKCS(1),
  339. spi->regs + SIFIVE_SPI_REG_DELAY0);
  340. writel(SIFIVE_SPI_DELAY1_INTERCS(1) | SIFIVE_SPI_DELAY1_INTERXFR(0),
  341. spi->regs + SIFIVE_SPI_REG_DELAY1);
  342. /* Exit specialized memory-mapped SPI flash mode */
  343. writel(0, spi->regs + SIFIVE_SPI_REG_FCTRL);
  344. }
  345. static int sifive_spi_probe(struct udevice *bus)
  346. {
  347. struct sifive_spi *spi = dev_get_priv(bus);
  348. struct clk clkdev;
  349. int ret;
  350. spi->regs = (void *)(ulong)dev_remap_addr(bus);
  351. if (!spi->regs)
  352. return -ENODEV;
  353. spi->fifo_depth = dev_read_u32_default(bus,
  354. "sifive,fifo-depth",
  355. SIFIVE_SPI_DEFAULT_DEPTH);
  356. spi->bits_per_word = dev_read_u32_default(bus,
  357. "sifive,max-bits-per-word",
  358. SIFIVE_SPI_DEFAULT_BITS);
  359. ret = clk_get_by_index(bus, 0, &clkdev);
  360. if (ret)
  361. return ret;
  362. spi->freq = clk_get_rate(&clkdev);
  363. /* init the sifive spi hw */
  364. sifive_spi_init_hw(spi);
  365. return 0;
  366. }
  367. static const struct spi_controller_mem_ops sifive_spi_mem_ops = {
  368. .exec_op = sifive_spi_exec_op,
  369. };
  370. static const struct dm_spi_ops sifive_spi_ops = {
  371. .xfer = sifive_spi_xfer,
  372. .set_speed = sifive_spi_set_speed,
  373. .set_mode = sifive_spi_set_mode,
  374. .cs_info = sifive_spi_cs_info,
  375. .mem_ops = &sifive_spi_mem_ops,
  376. };
  377. static const struct udevice_id sifive_spi_ids[] = {
  378. { .compatible = "sifive,spi0" },
  379. { }
  380. };
  381. U_BOOT_DRIVER(sifive_spi) = {
  382. .name = "sifive_spi",
  383. .id = UCLASS_SPI,
  384. .of_match = sifive_spi_ids,
  385. .ops = &sifive_spi_ops,
  386. .priv_auto_alloc_size = sizeof(struct sifive_spi),
  387. .probe = sifive_spi_probe,
  388. };