sdram_soc64.c 7.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
  4. *
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <dm.h>
  9. #include <errno.h>
  10. #include <div64.h>
  11. #include <fdtdec.h>
  12. #include <hang.h>
  13. #include <ram.h>
  14. #include <reset.h>
  15. #include "sdram_soc64.h"
  16. #include <wait_bit.h>
  17. #include <asm/arch/firewall.h>
  18. #include <asm/arch/system_manager.h>
  19. #include <asm/arch/reset_manager.h>
  20. #include <asm/io.h>
  21. #include <dm/device_compat.h>
  22. #include <linux/sizes.h>
  23. #define PGTABLE_OFF 0x4000
  24. u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg)
  25. {
  26. return readl(plat->iomhc + reg);
  27. }
  28. u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg)
  29. {
  30. return readl(plat->hmc + reg);
  31. }
  32. u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
  33. u32 data, u32 reg)
  34. {
  35. return writel(data, plat->hmc + reg);
  36. }
  37. u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
  38. u32 reg)
  39. {
  40. return writel(data, plat->ddr_sch + reg);
  41. }
  42. int emif_clear(struct altera_sdram_platdata *plat)
  43. {
  44. hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL);
  45. return wait_for_bit_le32((const void *)(plat->hmc +
  46. RSTHANDSHAKESTAT),
  47. DDR_HMC_RSTHANDSHAKE_MASK,
  48. false, 1000, false);
  49. }
  50. int emif_reset(struct altera_sdram_platdata *plat)
  51. {
  52. u32 c2s, s2c, ret;
  53. c2s = hmc_ecc_readl(plat, RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK;
  54. s2c = hmc_ecc_readl(plat, RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK;
  55. debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
  56. c2s, s2c, hmc_readl(plat, NIOSRESERVED0),
  57. hmc_readl(plat, NIOSRESERVED1), hmc_readl(plat, NIOSRESERVED2),
  58. hmc_readl(plat, DRAMSTS));
  59. if (s2c && emif_clear(plat)) {
  60. printf("DDR: emif_clear() failed\n");
  61. return -1;
  62. }
  63. debug("DDR: Triggerring emif reset\n");
  64. hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);
  65. /* if seq2core[3] = 0, we are good */
  66. ret = wait_for_bit_le32((const void *)(plat->hmc +
  67. RSTHANDSHAKESTAT),
  68. DDR_HMC_SEQ2CORE_INT_RESP_MASK,
  69. false, 1000, false);
  70. if (ret) {
  71. printf("DDR: failed to get ack from EMIF\n");
  72. return ret;
  73. }
  74. ret = emif_clear(plat);
  75. if (ret) {
  76. printf("DDR: emif_clear() failed\n");
  77. return ret;
  78. }
  79. debug("DDR: %s triggered successly\n", __func__);
  80. return 0;
  81. }
  82. int poll_hmc_clock_status(void)
  83. {
  84. return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
  85. SYSMGR_SOC64_HMC_CLK),
  86. SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
  87. }
  88. void sdram_clear_mem(phys_addr_t addr, phys_size_t size)
  89. {
  90. phys_size_t i;
  91. if (addr % CONFIG_SYS_CACHELINE_SIZE) {
  92. printf("DDR: address 0x%llx is not cacheline size aligned.\n",
  93. addr);
  94. hang();
  95. }
  96. if (size % CONFIG_SYS_CACHELINE_SIZE) {
  97. printf("DDR: size 0x%llx is not multiple of cacheline size\n",
  98. size);
  99. hang();
  100. }
  101. /* Use DC ZVA instruction to clear memory to zeros by a cache line */
  102. for (i = 0; i < size; i = i + CONFIG_SYS_CACHELINE_SIZE) {
  103. asm volatile("dc zva, %0"
  104. :
  105. : "r"(addr)
  106. : "memory");
  107. addr += CONFIG_SYS_CACHELINE_SIZE;
  108. }
  109. }
  110. void sdram_init_ecc_bits(bd_t *bd)
  111. {
  112. phys_size_t size, size_init;
  113. phys_addr_t start_addr;
  114. int bank = 0;
  115. unsigned int start = get_timer(0);
  116. icache_enable();
  117. start_addr = bd->bi_dram[0].start;
  118. size = bd->bi_dram[0].size;
  119. /* Initialize small block for page table */
  120. memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF);
  121. gd->arch.tlb_addr = start_addr + PGTABLE_OFF;
  122. gd->arch.tlb_size = PGTABLE_SIZE;
  123. start_addr += PGTABLE_SIZE + PGTABLE_OFF;
  124. size -= (PGTABLE_OFF + PGTABLE_SIZE);
  125. dcache_enable();
  126. while (1) {
  127. while (size) {
  128. size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size);
  129. sdram_clear_mem(start_addr, size_init);
  130. size -= size_init;
  131. start_addr += size_init;
  132. WATCHDOG_RESET();
  133. }
  134. bank++;
  135. if (bank >= CONFIG_NR_DRAM_BANKS)
  136. break;
  137. start_addr = bd->bi_dram[bank].start;
  138. size = bd->bi_dram[bank].size;
  139. }
  140. dcache_disable();
  141. icache_disable();
  142. printf("SDRAM-ECC: Initialized success with %d ms\n",
  143. (unsigned int)get_timer(start));
  144. }
  145. void sdram_size_check(bd_t *bd)
  146. {
  147. phys_size_t total_ram_check = 0;
  148. phys_size_t ram_check = 0;
  149. phys_addr_t start = 0;
  150. int bank;
  151. /* Sanity check ensure correct SDRAM size specified */
  152. debug("DDR: Running SDRAM size sanity check\n");
  153. for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
  154. start = bd->bi_dram[bank].start;
  155. while (ram_check < bd->bi_dram[bank].size) {
  156. ram_check += get_ram_size((void *)(start + ram_check),
  157. (phys_size_t)SZ_1G);
  158. }
  159. total_ram_check += ram_check;
  160. ram_check = 0;
  161. }
  162. /* If the ram_size is 2GB smaller, we can assume the IO space is
  163. * not mapped in. gd->ram_size is the actual size of the dram
  164. * not the accessible size.
  165. */
  166. if (total_ram_check != gd->ram_size) {
  167. puts("DDR: SDRAM size check failed!\n");
  168. hang();
  169. }
  170. debug("DDR: SDRAM size check passed!\n");
  171. }
  172. /**
  173. * sdram_calculate_size() - Calculate SDRAM size
  174. *
  175. * Calculate SDRAM device size based on SDRAM controller parameters.
  176. * Size is specified in bytes.
  177. */
  178. phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat)
  179. {
  180. u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
  181. phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
  182. DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
  183. DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
  184. DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
  185. DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw));
  186. size *= (2 << (hmc_ecc_readl(plat, DDRIOCTRL) &
  187. DDR_HMC_DDRIOCTRL_IOSIZE_MSK));
  188. return size;
  189. }
  190. static int altera_sdram_ofdata_to_platdata(struct udevice *dev)
  191. {
  192. struct altera_sdram_platdata *plat = dev->platdata;
  193. fdt_addr_t addr;
  194. addr = dev_read_addr_index(dev, 0);
  195. if (addr == FDT_ADDR_T_NONE)
  196. return -EINVAL;
  197. plat->ddr_sch = (void __iomem *)addr;
  198. addr = dev_read_addr_index(dev, 1);
  199. if (addr == FDT_ADDR_T_NONE)
  200. return -EINVAL;
  201. plat->iomhc = (void __iomem *)addr;
  202. addr = dev_read_addr_index(dev, 2);
  203. if (addr == FDT_ADDR_T_NONE)
  204. return -EINVAL;
  205. plat->hmc = (void __iomem *)addr;
  206. return 0;
  207. }
  208. static int altera_sdram_probe(struct udevice *dev)
  209. {
  210. int ret;
  211. struct altera_sdram_priv *priv = dev_get_priv(dev);
  212. ret = reset_get_bulk(dev, &priv->resets);
  213. if (ret) {
  214. dev_err(dev, "Can't get reset: %d\n", ret);
  215. return -ENODEV;
  216. }
  217. reset_deassert_bulk(&priv->resets);
  218. if (sdram_mmr_init_full(dev) != 0) {
  219. puts("SDRAM init failed.\n");
  220. goto failed;
  221. }
  222. return 0;
  223. failed:
  224. reset_release_bulk(&priv->resets);
  225. return -ENODEV;
  226. }
  227. static int altera_sdram_get_info(struct udevice *dev,
  228. struct ram_info *info)
  229. {
  230. struct altera_sdram_priv *priv = dev_get_priv(dev);
  231. info->base = priv->info.base;
  232. info->size = priv->info.size;
  233. return 0;
  234. }
  235. static struct ram_ops altera_sdram_ops = {
  236. .get_info = altera_sdram_get_info,
  237. };
  238. static const struct udevice_id altera_sdram_ids[] = {
  239. { .compatible = "altr,sdr-ctl-s10" },
  240. { .compatible = "intel,sdr-ctl-agilex" },
  241. { /* sentinel */ }
  242. };
  243. U_BOOT_DRIVER(altera_sdram) = {
  244. .name = "altr_sdr_ctl",
  245. .id = UCLASS_RAM,
  246. .of_match = altera_sdram_ids,
  247. .ops = &altera_sdram_ops,
  248. .ofdata_to_platdata = altera_sdram_ofdata_to_platdata,
  249. .platdata_auto_alloc_size = sizeof(struct altera_sdram_platdata),
  250. .probe = altera_sdram_probe,
  251. .priv_auto_alloc_size = sizeof(struct altera_sdram_priv),
  252. };