tegra-car-clk.c 2.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2016, NVIDIA CORPORATION.
  4. */
  5. #include <common.h>
  6. #include <clk-uclass.h>
  7. #include <dm.h>
  8. #include <malloc.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch-tegra/clk_rst.h>
  11. static int tegra_car_clk_request(struct clk *clk)
  12. {
  13. debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
  14. clk->id);
  15. /*
  16. * Note that the first PERIPH_ID_COUNT clock IDs (where the value
  17. * varies per SoC) are the peripheral clocks, which use a numbering
  18. * scheme that matches HW registers 1:1. There are other clock IDs
  19. * beyond this that are assigned arbitrarily by the Tegra CAR DT
  20. * binding. Due to the implementation of this driver, it currently
  21. * only supports the peripheral IDs.
  22. */
  23. if (clk->id >= PERIPH_ID_COUNT)
  24. return -EINVAL;
  25. return 0;
  26. }
  27. static int tegra_car_clk_free(struct clk *clk)
  28. {
  29. debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
  30. clk->id);
  31. return 0;
  32. }
  33. static ulong tegra_car_clk_get_rate(struct clk *clk)
  34. {
  35. enum clock_id parent;
  36. debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
  37. clk->id);
  38. parent = clock_get_periph_parent(clk->id);
  39. return clock_get_periph_rate(clk->id, parent);
  40. }
  41. static ulong tegra_car_clk_set_rate(struct clk *clk, ulong rate)
  42. {
  43. enum clock_id parent;
  44. debug("%s(clk=%p, rate=%lu) (dev=%p, id=%lu)\n", __func__, clk, rate,
  45. clk->dev, clk->id);
  46. parent = clock_get_periph_parent(clk->id);
  47. return clock_adjust_periph_pll_div(clk->id, parent, rate, NULL);
  48. }
  49. static int tegra_car_clk_enable(struct clk *clk)
  50. {
  51. debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
  52. clk->id);
  53. clock_enable(clk->id);
  54. return 0;
  55. }
  56. static int tegra_car_clk_disable(struct clk *clk)
  57. {
  58. debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
  59. clk->id);
  60. clock_disable(clk->id);
  61. return 0;
  62. }
  63. static struct clk_ops tegra_car_clk_ops = {
  64. .request = tegra_car_clk_request,
  65. .rfree = tegra_car_clk_free,
  66. .get_rate = tegra_car_clk_get_rate,
  67. .set_rate = tegra_car_clk_set_rate,
  68. .enable = tegra_car_clk_enable,
  69. .disable = tegra_car_clk_disable,
  70. };
  71. static int tegra_car_clk_probe(struct udevice *dev)
  72. {
  73. debug("%s(dev=%p)\n", __func__, dev);
  74. return 0;
  75. }
  76. U_BOOT_DRIVER(tegra_car_clk) = {
  77. .name = "tegra_car_clk",
  78. .id = UCLASS_CLK,
  79. .probe = tegra_car_clk_probe,
  80. .ops = &tegra_car_clk_ops,
  81. };