clk_rv1108.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * (C) Copyright 2016 Rockchip Electronics Co., Ltd
  4. * Author: Andy Yan <andy.yan@rock-chips.com>
  5. */
  6. #include <common.h>
  7. #include <bitfield.h>
  8. #include <clk-uclass.h>
  9. #include <dm.h>
  10. #include <errno.h>
  11. #include <malloc.h>
  12. #include <syscon.h>
  13. #include <asm/io.h>
  14. #include <asm/arch-rockchip/clock.h>
  15. #include <asm/arch-rockchip/cru_rv1108.h>
  16. #include <asm/arch-rockchip/hardware.h>
  17. #include <dm/lists.h>
  18. #include <dt-bindings/clock/rv1108-cru.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. enum {
  21. VCO_MAX_HZ = 2400U * 1000000,
  22. VCO_MIN_HZ = 600 * 1000000,
  23. OUTPUT_MAX_HZ = 2400U * 1000000,
  24. OUTPUT_MIN_HZ = 24 * 1000000,
  25. };
  26. #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
  27. #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
  28. .refdiv = _refdiv,\
  29. .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\
  30. .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
  31. _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) *\
  32. OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz,\
  33. #hz "Hz cannot be hit with PLL "\
  34. "divisors on line " __stringify(__LINE__));
  35. static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
  36. static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
  37. /* use integer mode */
  38. static inline int rv1108_pll_id(enum rk_clk_id clk_id)
  39. {
  40. int id = 0;
  41. switch (clk_id) {
  42. case CLK_ARM:
  43. case CLK_DDR:
  44. id = clk_id - 1;
  45. break;
  46. case CLK_GENERAL:
  47. id = 2;
  48. break;
  49. default:
  50. printf("invalid pll id:%d\n", clk_id);
  51. id = -1;
  52. break;
  53. }
  54. return id;
  55. }
  56. static int rkclk_set_pll(struct rv1108_cru *cru, enum rk_clk_id clk_id,
  57. const struct pll_div *div)
  58. {
  59. int pll_id = rv1108_pll_id(clk_id);
  60. struct rv1108_pll *pll = &cru->pll[pll_id];
  61. /* All PLLs have same VCO and output frequency range restrictions. */
  62. uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
  63. uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
  64. debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n",
  65. pll, div->fbdiv, div->refdiv, div->postdiv1,
  66. div->postdiv2, vco_hz, output_hz);
  67. assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
  68. output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
  69. /*
  70. * When power on or changing PLL setting,
  71. * we must force PLL into slow mode to ensure output stable clock.
  72. */
  73. rk_clrsetreg(&pll->con3, WORK_MODE_MASK,
  74. WORK_MODE_SLOW << WORK_MODE_SHIFT);
  75. /* use integer mode */
  76. rk_setreg(&pll->con3, 1 << DSMPD_SHIFT);
  77. /* Power down */
  78. rk_setreg(&pll->con3, 1 << GLOBAL_POWER_DOWN_SHIFT);
  79. rk_clrsetreg(&pll->con0, FBDIV_MASK, div->fbdiv << FBDIV_SHIFT);
  80. rk_clrsetreg(&pll->con1, POSTDIV1_MASK | POSTDIV2_MASK | REFDIV_MASK,
  81. (div->postdiv1 << POSTDIV1_SHIFT |
  82. div->postdiv2 << POSTDIV2_SHIFT |
  83. div->refdiv << REFDIV_SHIFT));
  84. rk_clrsetreg(&pll->con2, FRACDIV_MASK,
  85. (div->refdiv << REFDIV_SHIFT));
  86. /* Power Up */
  87. rk_clrreg(&pll->con3, 1 << GLOBAL_POWER_DOWN_SHIFT);
  88. /* waiting for pll lock */
  89. while (readl(&pll->con2) & (1 << LOCK_STA_SHIFT))
  90. udelay(1);
  91. /*
  92. * set PLL into normal mode.
  93. */
  94. rk_clrsetreg(&pll->con3, WORK_MODE_MASK,
  95. WORK_MODE_NORMAL << WORK_MODE_SHIFT);
  96. return 0;
  97. }
  98. static uint32_t rkclk_pll_get_rate(struct rv1108_cru *cru,
  99. enum rk_clk_id clk_id)
  100. {
  101. uint32_t refdiv, fbdiv, postdiv1, postdiv2;
  102. uint32_t con0, con1, con3;
  103. int pll_id = rv1108_pll_id(clk_id);
  104. struct rv1108_pll *pll = &cru->pll[pll_id];
  105. uint32_t freq;
  106. con3 = readl(&pll->con3);
  107. if (con3 & WORK_MODE_MASK) {
  108. con0 = readl(&pll->con0);
  109. con1 = readl(&pll->con1);
  110. fbdiv = (con0 >> FBDIV_SHIFT) & FBDIV_MASK;
  111. postdiv1 = (con1 & POSTDIV1_MASK) >> POSTDIV1_SHIFT;
  112. postdiv2 = (con1 & POSTDIV2_MASK) >> POSTDIV2_SHIFT;
  113. refdiv = (con1 >> REFDIV_SHIFT) & REFDIV_MASK;
  114. freq = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
  115. } else {
  116. freq = OSC_HZ;
  117. }
  118. return freq;
  119. }
  120. static int rv1108_mac_set_clk(struct rv1108_cru *cru, ulong rate)
  121. {
  122. uint32_t con = readl(&cru->clksel_con[24]);
  123. ulong pll_rate;
  124. uint8_t div;
  125. if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_GPLL)
  126. pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
  127. else
  128. pll_rate = rkclk_pll_get_rate(cru, CLK_ARM);
  129. /*default set 50MHZ for gmac*/
  130. if (!rate)
  131. rate = 50000000;
  132. div = DIV_ROUND_UP(pll_rate, rate) - 1;
  133. if (div <= 0x1f)
  134. rk_clrsetreg(&cru->clksel_con[24], MAC_CLK_DIV_MASK,
  135. div << MAC_CLK_DIV_SHIFT);
  136. else
  137. debug("Unsupported div for gmac:%d\n", div);
  138. return DIV_TO_RATE(pll_rate, div);
  139. }
  140. static int rv1108_sfc_set_clk(struct rv1108_cru *cru, uint rate)
  141. {
  142. u32 con = readl(&cru->clksel_con[27]);
  143. u32 pll_rate;
  144. u32 div;
  145. if ((con >> SFC_PLL_SEL_SHIFT) && SFC_PLL_SEL_GPLL)
  146. pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
  147. else
  148. pll_rate = rkclk_pll_get_rate(cru, CLK_DDR);
  149. div = DIV_ROUND_UP(pll_rate, rate) - 1;
  150. if (div <= 0x3f)
  151. rk_clrsetreg(&cru->clksel_con[27], SFC_CLK_DIV_MASK,
  152. div << SFC_CLK_DIV_SHIFT);
  153. else
  154. debug("Unsupported sfc clk rate:%d\n", rate);
  155. return DIV_TO_RATE(pll_rate, div);
  156. }
  157. static ulong rv1108_saradc_get_clk(struct rv1108_cru *cru)
  158. {
  159. u32 div, val;
  160. val = readl(&cru->clksel_con[22]);
  161. div = bitfield_extract(val, CLK_SARADC_DIV_CON_SHIFT,
  162. CLK_SARADC_DIV_CON_WIDTH);
  163. return DIV_TO_RATE(OSC_HZ, div);
  164. }
  165. static ulong rv1108_saradc_set_clk(struct rv1108_cru *cru, uint hz)
  166. {
  167. int src_clk_div;
  168. src_clk_div = DIV_ROUND_UP(OSC_HZ, hz) - 1;
  169. assert(src_clk_div < 128);
  170. rk_clrsetreg(&cru->clksel_con[22],
  171. CLK_SARADC_DIV_CON_MASK,
  172. src_clk_div << CLK_SARADC_DIV_CON_SHIFT);
  173. return rv1108_saradc_get_clk(cru);
  174. }
  175. static ulong rv1108_aclk_vio1_get_clk(struct rv1108_cru *cru)
  176. {
  177. u32 div, val;
  178. val = readl(&cru->clksel_con[28]);
  179. div = bitfield_extract(val, ACLK_VIO1_CLK_DIV_SHIFT,
  180. CLK_VIO_DIV_CON_WIDTH);
  181. return DIV_TO_RATE(GPLL_HZ, div);
  182. }
  183. static ulong rv1108_aclk_vio1_set_clk(struct rv1108_cru *cru, uint hz)
  184. {
  185. int src_clk_div;
  186. src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
  187. assert(src_clk_div < 32);
  188. rk_clrsetreg(&cru->clksel_con[28],
  189. ACLK_VIO1_CLK_DIV_MASK | ACLK_VIO1_PLL_SEL_MASK,
  190. (src_clk_div << ACLK_VIO1_CLK_DIV_SHIFT) |
  191. (VIO_PLL_SEL_GPLL << ACLK_VIO1_PLL_SEL_SHIFT));
  192. return rv1108_aclk_vio1_get_clk(cru);
  193. }
  194. static ulong rv1108_aclk_vio0_get_clk(struct rv1108_cru *cru)
  195. {
  196. u32 div, val;
  197. val = readl(&cru->clksel_con[28]);
  198. div = bitfield_extract(val, ACLK_VIO0_CLK_DIV_SHIFT,
  199. CLK_VIO_DIV_CON_WIDTH);
  200. return DIV_TO_RATE(GPLL_HZ, div);
  201. }
  202. static ulong rv1108_aclk_vio0_set_clk(struct rv1108_cru *cru, uint hz)
  203. {
  204. int src_clk_div;
  205. src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
  206. assert(src_clk_div < 32);
  207. rk_clrsetreg(&cru->clksel_con[28],
  208. ACLK_VIO0_CLK_DIV_MASK | ACLK_VIO0_PLL_SEL_MASK,
  209. (src_clk_div << ACLK_VIO0_CLK_DIV_SHIFT) |
  210. (VIO_PLL_SEL_GPLL << ACLK_VIO0_PLL_SEL_SHIFT));
  211. /*HCLK_VIO default div = 4*/
  212. rk_clrsetreg(&cru->clksel_con[29],
  213. HCLK_VIO_CLK_DIV_MASK,
  214. 3 << HCLK_VIO_CLK_DIV_SHIFT);
  215. /*PCLK_VIO default div = 4*/
  216. rk_clrsetreg(&cru->clksel_con[29],
  217. PCLK_VIO_CLK_DIV_MASK,
  218. 3 << PCLK_VIO_CLK_DIV_SHIFT);
  219. return rv1108_aclk_vio0_get_clk(cru);
  220. }
  221. static ulong rv1108_dclk_vop_get_clk(struct rv1108_cru *cru)
  222. {
  223. u32 div, val;
  224. val = readl(&cru->clksel_con[32]);
  225. div = bitfield_extract(val, DCLK_VOP_CLK_DIV_SHIFT,
  226. DCLK_VOP_DIV_CON_WIDTH);
  227. return DIV_TO_RATE(GPLL_HZ, div);
  228. }
  229. static ulong rv1108_dclk_vop_set_clk(struct rv1108_cru *cru, uint hz)
  230. {
  231. int src_clk_div;
  232. src_clk_div = DIV_ROUND_UP(GPLL_HZ, hz) - 1;
  233. assert(src_clk_div < 64);
  234. rk_clrsetreg(&cru->clksel_con[32],
  235. DCLK_VOP_CLK_DIV_MASK | DCLK_VOP_PLL_SEL_MASK |
  236. DCLK_VOP_SEL_SHIFT,
  237. (src_clk_div << DCLK_VOP_CLK_DIV_SHIFT) |
  238. (DCLK_VOP_PLL_SEL_GPLL << DCLK_VOP_PLL_SEL_SHIFT) |
  239. (DCLK_VOP_SEL_PLL << DCLK_VOP_SEL_SHIFT));
  240. return rv1108_dclk_vop_get_clk(cru);
  241. }
  242. static ulong rv1108_aclk_bus_get_clk(struct rv1108_cru *cru)
  243. {
  244. u32 div, val;
  245. ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
  246. val = readl(&cru->clksel_con[2]);
  247. div = bitfield_extract(val, ACLK_BUS_DIV_CON_SHIFT,
  248. ACLK_BUS_DIV_CON_WIDTH);
  249. return DIV_TO_RATE(parent_rate, div);
  250. }
  251. static ulong rv1108_aclk_bus_set_clk(struct rv1108_cru *cru, uint hz)
  252. {
  253. int src_clk_div;
  254. ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
  255. src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1;
  256. assert(src_clk_div < 32);
  257. rk_clrsetreg(&cru->clksel_con[2],
  258. ACLK_BUS_DIV_CON_MASK | ACLK_BUS_PLL_SEL_MASK,
  259. (src_clk_div << ACLK_BUS_DIV_CON_SHIFT) |
  260. (ACLK_BUS_PLL_SEL_GPLL << ACLK_BUS_PLL_SEL_SHIFT));
  261. return rv1108_aclk_bus_get_clk(cru);
  262. }
  263. static ulong rv1108_aclk_peri_get_clk(struct rv1108_cru *cru)
  264. {
  265. u32 div, val;
  266. ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
  267. val = readl(&cru->clksel_con[23]);
  268. div = bitfield_extract(val, ACLK_PERI_DIV_CON_SHIFT,
  269. PERI_DIV_CON_WIDTH);
  270. return DIV_TO_RATE(parent_rate, div);
  271. }
  272. static ulong rv1108_hclk_peri_get_clk(struct rv1108_cru *cru)
  273. {
  274. u32 div, val;
  275. ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
  276. val = readl(&cru->clksel_con[23]);
  277. div = bitfield_extract(val, HCLK_PERI_DIV_CON_SHIFT,
  278. PERI_DIV_CON_WIDTH);
  279. return DIV_TO_RATE(parent_rate, div);
  280. }
  281. static ulong rv1108_pclk_peri_get_clk(struct rv1108_cru *cru)
  282. {
  283. u32 div, val;
  284. ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
  285. val = readl(&cru->clksel_con[23]);
  286. div = bitfield_extract(val, PCLK_PERI_DIV_CON_SHIFT,
  287. PERI_DIV_CON_WIDTH);
  288. return DIV_TO_RATE(parent_rate, div);
  289. }
  290. static ulong rv1108_aclk_peri_set_clk(struct rv1108_cru *cru, uint hz)
  291. {
  292. int src_clk_div;
  293. ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
  294. src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1;
  295. assert(src_clk_div < 32);
  296. rk_clrsetreg(&cru->clksel_con[23],
  297. ACLK_PERI_DIV_CON_MASK | ACLK_PERI_PLL_SEL_MASK,
  298. (src_clk_div << ACLK_PERI_DIV_CON_SHIFT) |
  299. (ACLK_PERI_PLL_SEL_GPLL << ACLK_PERI_PLL_SEL_SHIFT));
  300. return rv1108_aclk_peri_get_clk(cru);
  301. }
  302. static ulong rv1108_hclk_peri_set_clk(struct rv1108_cru *cru, uint hz)
  303. {
  304. int src_clk_div;
  305. ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
  306. src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1;
  307. assert(src_clk_div < 32);
  308. rk_clrsetreg(&cru->clksel_con[23],
  309. HCLK_PERI_DIV_CON_MASK,
  310. (src_clk_div << HCLK_PERI_DIV_CON_SHIFT));
  311. return rv1108_hclk_peri_get_clk(cru);
  312. }
  313. static ulong rv1108_pclk_peri_set_clk(struct rv1108_cru *cru, uint hz)
  314. {
  315. int src_clk_div;
  316. ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
  317. src_clk_div = DIV_ROUND_UP(parent_rate, hz) - 1;
  318. assert(src_clk_div < 32);
  319. rk_clrsetreg(&cru->clksel_con[23],
  320. PCLK_PERI_DIV_CON_MASK,
  321. (src_clk_div << PCLK_PERI_DIV_CON_SHIFT));
  322. return rv1108_pclk_peri_get_clk(cru);
  323. }
  324. static ulong rv1108_i2c_get_clk(struct rv1108_cru *cru, ulong clk_id)
  325. {
  326. u32 div, con;
  327. switch (clk_id) {
  328. case SCLK_I2C0_PMU:
  329. con = readl(&cru->clksel_con[19]);
  330. div = bitfield_extract(con, CLK_I2C0_DIV_CON_SHIFT,
  331. I2C_DIV_CON_WIDTH);
  332. break;
  333. case SCLK_I2C1:
  334. con = readl(&cru->clksel_con[19]);
  335. div = bitfield_extract(con, CLK_I2C1_DIV_CON_SHIFT,
  336. I2C_DIV_CON_WIDTH);
  337. break;
  338. case SCLK_I2C2:
  339. con = readl(&cru->clksel_con[20]);
  340. div = bitfield_extract(con, CLK_I2C2_DIV_CON_SHIFT,
  341. I2C_DIV_CON_WIDTH);
  342. break;
  343. case SCLK_I2C3:
  344. con = readl(&cru->clksel_con[20]);
  345. div = bitfield_extract(con, CLK_I2C3_DIV_CON_SHIFT,
  346. I2C_DIV_CON_WIDTH);
  347. break;
  348. default:
  349. printf("do not support this i2c bus\n");
  350. return -EINVAL;
  351. }
  352. return DIV_TO_RATE(GPLL_HZ, div);
  353. }
  354. static ulong rv1108_i2c_set_clk(struct rv1108_cru *cru, ulong clk_id, uint hz)
  355. {
  356. int src_clk_div;
  357. /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/
  358. src_clk_div = GPLL_HZ / hz;
  359. assert(src_clk_div - 1 <= 127);
  360. switch (clk_id) {
  361. case SCLK_I2C0_PMU:
  362. rk_clrsetreg(&cru->clksel_con[19],
  363. CLK_I2C0_DIV_CON_MASK | CLK_I2C1_PLL_SEL_MASK,
  364. (src_clk_div << CLK_I2C0_DIV_CON_SHIFT) |
  365. (CLK_I2C1_PLL_SEL_GPLL << CLK_I2C1_PLL_SEL_SHIFT));
  366. break;
  367. case SCLK_I2C1:
  368. rk_clrsetreg(&cru->clksel_con[19],
  369. CLK_I2C1_DIV_CON_MASK | CLK_I2C1_PLL_SEL_MASK,
  370. (src_clk_div << CLK_I2C1_DIV_CON_SHIFT) |
  371. (CLK_I2C1_PLL_SEL_GPLL << CLK_I2C1_PLL_SEL_SHIFT));
  372. break;
  373. case SCLK_I2C2:
  374. rk_clrsetreg(&cru->clksel_con[20],
  375. CLK_I2C2_DIV_CON_MASK | CLK_I2C3_PLL_SEL_MASK,
  376. (src_clk_div << CLK_I2C2_DIV_CON_SHIFT) |
  377. (CLK_I2C3_PLL_SEL_GPLL << CLK_I2C3_PLL_SEL_SHIFT));
  378. break;
  379. case SCLK_I2C3:
  380. rk_clrsetreg(&cru->clksel_con[20],
  381. CLK_I2C3_DIV_CON_MASK | CLK_I2C3_PLL_SEL_MASK,
  382. (src_clk_div << CLK_I2C3_DIV_CON_SHIFT) |
  383. (CLK_I2C3_PLL_SEL_GPLL << CLK_I2C3_PLL_SEL_SHIFT));
  384. break;
  385. default:
  386. printf("do not support this i2c bus\n");
  387. return -EINVAL;
  388. }
  389. return rv1108_i2c_get_clk(cru, clk_id);
  390. }
  391. static ulong rv1108_mmc_get_clk(struct rv1108_cru *cru)
  392. {
  393. u32 div, con;
  394. ulong mmc_clk;
  395. con = readl(&cru->clksel_con[26]);
  396. div = bitfield_extract(con, EMMC_CLK_DIV_SHIFT, 8);
  397. con = readl(&cru->clksel_con[25]);
  398. if ((con & EMMC_PLL_SEL_MASK) >> EMMC_PLL_SEL_SHIFT == EMMC_PLL_SEL_OSC)
  399. mmc_clk = DIV_TO_RATE(OSC_HZ, div) / 2;
  400. else
  401. mmc_clk = DIV_TO_RATE(GPLL_HZ, div) / 2;
  402. debug("%s div %d get_clk %ld\n", __func__, div, mmc_clk);
  403. return mmc_clk;
  404. }
  405. static ulong rv1108_mmc_set_clk(struct rv1108_cru *cru, ulong rate)
  406. {
  407. int div;
  408. u32 pll_rate;
  409. div = DIV_ROUND_UP(rkclk_pll_get_rate(cru, CLK_GENERAL), rate);
  410. if (div < 127) {
  411. debug("%s source gpll\n", __func__);
  412. rk_clrsetreg(&cru->clksel_con[25], EMMC_PLL_SEL_MASK,
  413. (EMMC_PLL_SEL_GPLL << EMMC_PLL_SEL_SHIFT));
  414. pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
  415. } else {
  416. debug("%s source 24m\n", __func__);
  417. rk_clrsetreg(&cru->clksel_con[25], EMMC_PLL_SEL_MASK,
  418. (EMMC_PLL_SEL_OSC << EMMC_PLL_SEL_SHIFT));
  419. pll_rate = OSC_HZ;
  420. }
  421. div = DIV_ROUND_UP(pll_rate / 2, rate);
  422. rk_clrsetreg(&cru->clksel_con[26], EMMC_CLK_DIV_MASK,
  423. ((div - 1) << EMMC_CLK_DIV_SHIFT));
  424. debug("%s set_rate %ld div %d\n", __func__, rate, div);
  425. return DIV_TO_RATE(pll_rate, div);
  426. }
  427. static ulong rv1108_clk_get_rate(struct clk *clk)
  428. {
  429. struct rv1108_clk_priv *priv = dev_get_priv(clk->dev);
  430. switch (clk->id) {
  431. case 0 ... 63:
  432. return rkclk_pll_get_rate(priv->cru, clk->id);
  433. case SCLK_SARADC:
  434. return rv1108_saradc_get_clk(priv->cru);
  435. case ACLK_VIO0:
  436. return rv1108_aclk_vio0_get_clk(priv->cru);
  437. case ACLK_VIO1:
  438. return rv1108_aclk_vio1_get_clk(priv->cru);
  439. case DCLK_VOP:
  440. return rv1108_dclk_vop_get_clk(priv->cru);
  441. case ACLK_PRE:
  442. return rv1108_aclk_bus_get_clk(priv->cru);
  443. case ACLK_PERI:
  444. return rv1108_aclk_peri_get_clk(priv->cru);
  445. case HCLK_PERI:
  446. return rv1108_hclk_peri_get_clk(priv->cru);
  447. case PCLK_PERI:
  448. return rv1108_pclk_peri_get_clk(priv->cru);
  449. case SCLK_I2C0_PMU:
  450. case SCLK_I2C1:
  451. case SCLK_I2C2:
  452. case SCLK_I2C3:
  453. return rv1108_i2c_get_clk(priv->cru, clk->id);
  454. case HCLK_EMMC:
  455. case SCLK_EMMC:
  456. case SCLK_EMMC_SAMPLE:
  457. return rv1108_mmc_get_clk(priv->cru);
  458. default:
  459. return -ENOENT;
  460. }
  461. }
  462. static ulong rv1108_clk_set_rate(struct clk *clk, ulong rate)
  463. {
  464. struct rv1108_clk_priv *priv = dev_get_priv(clk->dev);
  465. ulong new_rate;
  466. switch (clk->id) {
  467. case SCLK_MAC:
  468. new_rate = rv1108_mac_set_clk(priv->cru, rate);
  469. break;
  470. case SCLK_SFC:
  471. new_rate = rv1108_sfc_set_clk(priv->cru, rate);
  472. break;
  473. case SCLK_SARADC:
  474. new_rate = rv1108_saradc_set_clk(priv->cru, rate);
  475. break;
  476. case ACLK_VIO0:
  477. new_rate = rv1108_aclk_vio0_set_clk(priv->cru, rate);
  478. break;
  479. case ACLK_VIO1:
  480. new_rate = rv1108_aclk_vio1_set_clk(priv->cru, rate);
  481. break;
  482. case DCLK_VOP:
  483. new_rate = rv1108_dclk_vop_set_clk(priv->cru, rate);
  484. break;
  485. case ACLK_PRE:
  486. new_rate = rv1108_aclk_bus_set_clk(priv->cru, rate);
  487. break;
  488. case ACLK_PERI:
  489. new_rate = rv1108_aclk_peri_set_clk(priv->cru, rate);
  490. break;
  491. case HCLK_PERI:
  492. new_rate = rv1108_hclk_peri_set_clk(priv->cru, rate);
  493. break;
  494. case PCLK_PERI:
  495. new_rate = rv1108_pclk_peri_set_clk(priv->cru, rate);
  496. break;
  497. case SCLK_I2C0_PMU:
  498. case SCLK_I2C1:
  499. case SCLK_I2C2:
  500. case SCLK_I2C3:
  501. new_rate = rv1108_i2c_set_clk(priv->cru, clk->id, rate);
  502. break;
  503. case HCLK_EMMC:
  504. case SCLK_EMMC:
  505. new_rate = rv1108_mmc_set_clk(priv->cru, rate);
  506. break;
  507. default:
  508. return -ENOENT;
  509. }
  510. return new_rate;
  511. }
  512. static const struct clk_ops rv1108_clk_ops = {
  513. .get_rate = rv1108_clk_get_rate,
  514. .set_rate = rv1108_clk_set_rate,
  515. };
  516. static void rkclk_init(struct rv1108_cru *cru)
  517. {
  518. unsigned int apll, dpll, gpll;
  519. unsigned int aclk_bus, aclk_peri, hclk_peri, pclk_peri;
  520. aclk_bus = rv1108_aclk_bus_set_clk(cru, ACLK_BUS_HZ / 2);
  521. aclk_peri = rv1108_aclk_peri_set_clk(cru, ACLK_PERI_HZ / 2);
  522. hclk_peri = rv1108_hclk_peri_set_clk(cru, HCLK_PERI_HZ / 2);
  523. pclk_peri = rv1108_pclk_peri_set_clk(cru, PCLK_PERI_HZ / 2);
  524. rv1108_aclk_vio0_set_clk(cru, 297000000);
  525. rv1108_aclk_vio1_set_clk(cru, 297000000);
  526. /* configure apll */
  527. rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
  528. rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
  529. aclk_bus = rv1108_aclk_bus_set_clk(cru, ACLK_BUS_HZ);
  530. aclk_peri = rv1108_aclk_peri_set_clk(cru, ACLK_PERI_HZ);
  531. hclk_peri = rv1108_hclk_peri_set_clk(cru, HCLK_PERI_HZ);
  532. pclk_peri = rv1108_pclk_peri_set_clk(cru, PCLK_PERI_HZ);
  533. apll = rkclk_pll_get_rate(cru, CLK_ARM);
  534. dpll = rkclk_pll_get_rate(cru, CLK_DDR);
  535. gpll = rkclk_pll_get_rate(cru, CLK_GENERAL);
  536. rk_clrsetreg(&cru->clksel_con[0], CORE_CLK_DIV_MASK,
  537. 0 << MAC_CLK_DIV_SHIFT);
  538. printf("APLL: %d DPLL:%d GPLL:%d\n", apll, dpll, gpll);
  539. printf("ACLK_BUS: %d ACLK_PERI:%d HCLK_PERI:%d PCLK_PERI:%d\n",
  540. aclk_bus, aclk_peri, hclk_peri, pclk_peri);
  541. }
  542. static int rv1108_clk_ofdata_to_platdata(struct udevice *dev)
  543. {
  544. struct rv1108_clk_priv *priv = dev_get_priv(dev);
  545. priv->cru = dev_read_addr_ptr(dev);
  546. return 0;
  547. }
  548. static int rv1108_clk_probe(struct udevice *dev)
  549. {
  550. struct rv1108_clk_priv *priv = dev_get_priv(dev);
  551. rkclk_init(priv->cru);
  552. return 0;
  553. }
  554. static int rv1108_clk_bind(struct udevice *dev)
  555. {
  556. int ret;
  557. struct udevice *sys_child;
  558. struct sysreset_reg *priv;
  559. /* The reset driver does not have a device node, so bind it here */
  560. ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
  561. &sys_child);
  562. if (ret) {
  563. debug("Warning: No sysreset driver: ret=%d\n", ret);
  564. } else {
  565. priv = malloc(sizeof(struct sysreset_reg));
  566. priv->glb_srst_fst_value = offsetof(struct rv1108_cru,
  567. glb_srst_fst_val);
  568. priv->glb_srst_snd_value = offsetof(struct rv1108_cru,
  569. glb_srst_snd_val);
  570. sys_child->priv = priv;
  571. }
  572. #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
  573. ret = offsetof(struct rv1108_cru, softrst_con[0]);
  574. ret = rockchip_reset_bind(dev, ret, 13);
  575. if (ret)
  576. debug("Warning: software reset driver bind faile\n");
  577. #endif
  578. return 0;
  579. }
  580. static const struct udevice_id rv1108_clk_ids[] = {
  581. { .compatible = "rockchip,rv1108-cru" },
  582. { }
  583. };
  584. U_BOOT_DRIVER(clk_rv1108) = {
  585. .name = "clk_rv1108",
  586. .id = UCLASS_CLK,
  587. .of_match = rv1108_clk_ids,
  588. .priv_auto_alloc_size = sizeof(struct rv1108_clk_priv),
  589. .ops = &rv1108_clk_ops,
  590. .bind = rv1108_clk_bind,
  591. .ofdata_to_platdata = rv1108_clk_ofdata_to_platdata,
  592. .probe = rv1108_clk_probe,
  593. };