clk_zynq.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Weidmüller Interface GmbH & Co. KG
  4. * Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
  5. *
  6. * Copyright (C) 2013 Soren Brinkmann <soren.brinkmann@xilinx.com>
  7. * Copyright (C) 2013 Xilinx, Inc. All rights reserved.
  8. */
  9. #include <common.h>
  10. #include <clk-uclass.h>
  11. #include <dm.h>
  12. #include <dm/device_compat.h>
  13. #include <dm/lists.h>
  14. #include <errno.h>
  15. #include <asm/io.h>
  16. #include <asm/arch/clk.h>
  17. #include <asm/arch/hardware.h>
  18. #include <asm/arch/sys_proto.h>
  19. /* Register bitfield defines */
  20. #define PLLCTRL_FBDIV_MASK 0x7f000
  21. #define PLLCTRL_FBDIV_SHIFT 12
  22. #define PLLCTRL_BPFORCE_MASK (1 << 4)
  23. #define PLLCTRL_PWRDWN_MASK 2
  24. #define PLLCTRL_PWRDWN_SHIFT 1
  25. #define PLLCTRL_RESET_MASK 1
  26. #define PLLCTRL_RESET_SHIFT 0
  27. #define ZYNQ_CLK_MAXDIV 0x3f
  28. #define CLK_CTRL_DIV1_SHIFT 20
  29. #define CLK_CTRL_DIV1_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV1_SHIFT)
  30. #define CLK_CTRL_DIV0_SHIFT 8
  31. #define CLK_CTRL_DIV0_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV0_SHIFT)
  32. #define CLK_CTRL_SRCSEL_SHIFT 4
  33. #define CLK_CTRL_SRCSEL_MASK (0x3 << CLK_CTRL_SRCSEL_SHIFT)
  34. #define CLK_CTRL_DIV2X_SHIFT 26
  35. #define CLK_CTRL_DIV2X_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV2X_SHIFT)
  36. #define CLK_CTRL_DIV3X_SHIFT 20
  37. #define CLK_CTRL_DIV3X_MASK (ZYNQ_CLK_MAXDIV << CLK_CTRL_DIV3X_SHIFT)
  38. DECLARE_GLOBAL_DATA_PTR;
  39. #ifndef CONFIG_SPL_BUILD
  40. enum zynq_clk_rclk {mio_clk, emio_clk};
  41. #endif
  42. struct zynq_clk_priv {
  43. ulong ps_clk_freq;
  44. #ifndef CONFIG_SPL_BUILD
  45. struct clk gem_emio_clk[2];
  46. #endif
  47. };
  48. static void *zynq_clk_get_register(enum zynq_clk id)
  49. {
  50. switch (id) {
  51. case armpll_clk:
  52. return &slcr_base->arm_pll_ctrl;
  53. case ddrpll_clk:
  54. return &slcr_base->ddr_pll_ctrl;
  55. case iopll_clk:
  56. return &slcr_base->io_pll_ctrl;
  57. case lqspi_clk:
  58. return &slcr_base->lqspi_clk_ctrl;
  59. case smc_clk:
  60. return &slcr_base->smc_clk_ctrl;
  61. case pcap_clk:
  62. return &slcr_base->pcap_clk_ctrl;
  63. case sdio0_clk ... sdio1_clk:
  64. return &slcr_base->sdio_clk_ctrl;
  65. case uart0_clk ... uart1_clk:
  66. return &slcr_base->uart_clk_ctrl;
  67. case spi0_clk ... spi1_clk:
  68. return &slcr_base->spi_clk_ctrl;
  69. #ifndef CONFIG_SPL_BUILD
  70. case dci_clk:
  71. return &slcr_base->dci_clk_ctrl;
  72. case gem0_clk:
  73. return &slcr_base->gem0_clk_ctrl;
  74. case gem1_clk:
  75. return &slcr_base->gem1_clk_ctrl;
  76. case fclk0_clk:
  77. return &slcr_base->fpga0_clk_ctrl;
  78. case fclk1_clk:
  79. return &slcr_base->fpga1_clk_ctrl;
  80. case fclk2_clk:
  81. return &slcr_base->fpga2_clk_ctrl;
  82. case fclk3_clk:
  83. return &slcr_base->fpga3_clk_ctrl;
  84. case can0_clk ... can1_clk:
  85. return &slcr_base->can_clk_ctrl;
  86. case dbg_trc_clk ... dbg_apb_clk:
  87. /* fall through */
  88. #endif
  89. default:
  90. return &slcr_base->dbg_clk_ctrl;
  91. }
  92. }
  93. static enum zynq_clk zynq_clk_get_cpu_pll(u32 clk_ctrl)
  94. {
  95. u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
  96. switch (srcsel) {
  97. case 2:
  98. return ddrpll_clk;
  99. case 3:
  100. return iopll_clk;
  101. case 0 ... 1:
  102. default:
  103. return armpll_clk;
  104. }
  105. }
  106. static enum zynq_clk zynq_clk_get_peripheral_pll(u32 clk_ctrl)
  107. {
  108. u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
  109. switch (srcsel) {
  110. case 2:
  111. return armpll_clk;
  112. case 3:
  113. return ddrpll_clk;
  114. case 0 ... 1:
  115. default:
  116. return iopll_clk;
  117. }
  118. }
  119. static ulong zynq_clk_get_pll_rate(struct zynq_clk_priv *priv, enum zynq_clk id)
  120. {
  121. u32 clk_ctrl, reset, pwrdwn, mul, bypass;
  122. clk_ctrl = readl(zynq_clk_get_register(id));
  123. reset = (clk_ctrl & PLLCTRL_RESET_MASK) >> PLLCTRL_RESET_SHIFT;
  124. pwrdwn = (clk_ctrl & PLLCTRL_PWRDWN_MASK) >> PLLCTRL_PWRDWN_SHIFT;
  125. if (reset || pwrdwn)
  126. return 0;
  127. bypass = clk_ctrl & PLLCTRL_BPFORCE_MASK;
  128. if (bypass)
  129. mul = 1;
  130. else
  131. mul = (clk_ctrl & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT;
  132. return priv->ps_clk_freq * mul;
  133. }
  134. #ifndef CONFIG_SPL_BUILD
  135. static enum zynq_clk_rclk zynq_clk_get_gem_rclk(enum zynq_clk id)
  136. {
  137. u32 clk_ctrl, srcsel;
  138. if (id == gem0_clk)
  139. clk_ctrl = readl(&slcr_base->gem0_rclk_ctrl);
  140. else
  141. clk_ctrl = readl(&slcr_base->gem1_rclk_ctrl);
  142. srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT;
  143. if (srcsel)
  144. return emio_clk;
  145. else
  146. return mio_clk;
  147. }
  148. #endif
  149. static ulong zynq_clk_get_cpu_rate(struct zynq_clk_priv *priv, enum zynq_clk id)
  150. {
  151. u32 clk_621, clk_ctrl, div;
  152. enum zynq_clk pll;
  153. clk_ctrl = readl(&slcr_base->arm_clk_ctrl);
  154. div = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
  155. switch (id) {
  156. case cpu_1x_clk:
  157. div *= 2;
  158. /* fall through */
  159. case cpu_2x_clk:
  160. clk_621 = readl(&slcr_base->clk_621_true) & 1;
  161. div *= 2 + clk_621;
  162. break;
  163. case cpu_3or2x_clk:
  164. div *= 2;
  165. /* fall through */
  166. case cpu_6or4x_clk:
  167. break;
  168. default:
  169. return 0;
  170. }
  171. pll = zynq_clk_get_cpu_pll(clk_ctrl);
  172. return DIV_ROUND_CLOSEST(zynq_clk_get_pll_rate(priv, pll), div);
  173. }
  174. #ifndef CONFIG_SPL_BUILD
  175. static ulong zynq_clk_get_ddr2x_rate(struct zynq_clk_priv *priv)
  176. {
  177. u32 clk_ctrl, div;
  178. clk_ctrl = readl(&slcr_base->ddr_clk_ctrl);
  179. div = (clk_ctrl & CLK_CTRL_DIV2X_MASK) >> CLK_CTRL_DIV2X_SHIFT;
  180. return DIV_ROUND_CLOSEST(zynq_clk_get_pll_rate(priv, ddrpll_clk), div);
  181. }
  182. #endif
  183. static ulong zynq_clk_get_ddr3x_rate(struct zynq_clk_priv *priv)
  184. {
  185. u32 clk_ctrl, div;
  186. clk_ctrl = readl(&slcr_base->ddr_clk_ctrl);
  187. div = (clk_ctrl & CLK_CTRL_DIV3X_MASK) >> CLK_CTRL_DIV3X_SHIFT;
  188. return DIV_ROUND_CLOSEST(zynq_clk_get_pll_rate(priv, ddrpll_clk), div);
  189. }
  190. #ifndef CONFIG_SPL_BUILD
  191. static ulong zynq_clk_get_dci_rate(struct zynq_clk_priv *priv)
  192. {
  193. u32 clk_ctrl, div0, div1;
  194. clk_ctrl = readl(&slcr_base->dci_clk_ctrl);
  195. div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
  196. div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
  197. return DIV_ROUND_CLOSEST(DIV_ROUND_CLOSEST(
  198. zynq_clk_get_pll_rate(priv, ddrpll_clk), div0), div1);
  199. }
  200. #endif
  201. static ulong zynq_clk_get_peripheral_rate(struct zynq_clk_priv *priv,
  202. enum zynq_clk id, bool two_divs)
  203. {
  204. enum zynq_clk pll;
  205. u32 clk_ctrl, div0;
  206. u32 div1 = 1;
  207. clk_ctrl = readl(zynq_clk_get_register(id));
  208. div0 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
  209. if (!div0)
  210. div0 = 1;
  211. #ifndef CONFIG_SPL_BUILD
  212. if (two_divs) {
  213. div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
  214. if (!div1)
  215. div1 = 1;
  216. }
  217. #endif
  218. pll = zynq_clk_get_peripheral_pll(clk_ctrl);
  219. return
  220. DIV_ROUND_CLOSEST(
  221. DIV_ROUND_CLOSEST(
  222. zynq_clk_get_pll_rate(priv, pll), div0),
  223. div1);
  224. }
  225. #ifndef CONFIG_SPL_BUILD
  226. static ulong zynq_clk_get_gem_rate(struct zynq_clk_priv *priv, enum zynq_clk id)
  227. {
  228. struct clk *parent;
  229. if (zynq_clk_get_gem_rclk(id) == mio_clk)
  230. return zynq_clk_get_peripheral_rate(priv, id, true);
  231. parent = &priv->gem_emio_clk[id - gem0_clk];
  232. if (parent->dev)
  233. return clk_get_rate(parent);
  234. debug("%s: gem%d emio rx clock source unknown\n", __func__,
  235. id - gem0_clk);
  236. return -ENOSYS;
  237. }
  238. static unsigned long zynq_clk_calc_peripheral_two_divs(ulong rate,
  239. ulong pll_rate,
  240. u32 *div0, u32 *div1)
  241. {
  242. long new_err, best_err = (long)(~0UL >> 1);
  243. ulong new_rate, best_rate = 0;
  244. u32 d0, d1;
  245. for (d0 = 1; d0 <= ZYNQ_CLK_MAXDIV; d0++) {
  246. for (d1 = 1; d1 <= ZYNQ_CLK_MAXDIV >> 1; d1++) {
  247. new_rate = DIV_ROUND_CLOSEST(
  248. DIV_ROUND_CLOSEST(pll_rate, d0), d1);
  249. new_err = abs(new_rate - rate);
  250. if (new_err < best_err) {
  251. *div0 = d0;
  252. *div1 = d1;
  253. best_err = new_err;
  254. best_rate = new_rate;
  255. }
  256. }
  257. }
  258. return best_rate;
  259. }
  260. static ulong zynq_clk_set_peripheral_rate(struct zynq_clk_priv *priv,
  261. enum zynq_clk id, ulong rate,
  262. bool two_divs)
  263. {
  264. enum zynq_clk pll;
  265. u32 clk_ctrl, div0 = 0, div1 = 0;
  266. ulong pll_rate, new_rate;
  267. u32 *reg;
  268. reg = zynq_clk_get_register(id);
  269. clk_ctrl = readl(reg);
  270. pll = zynq_clk_get_peripheral_pll(clk_ctrl);
  271. pll_rate = zynq_clk_get_pll_rate(priv, pll);
  272. clk_ctrl &= ~CLK_CTRL_DIV0_MASK;
  273. if (two_divs) {
  274. clk_ctrl &= ~CLK_CTRL_DIV1_MASK;
  275. new_rate = zynq_clk_calc_peripheral_two_divs(rate, pll_rate,
  276. &div0, &div1);
  277. clk_ctrl |= div1 << CLK_CTRL_DIV1_SHIFT;
  278. } else {
  279. div0 = DIV_ROUND_CLOSEST(pll_rate, rate);
  280. if (div0 > ZYNQ_CLK_MAXDIV)
  281. div0 = ZYNQ_CLK_MAXDIV;
  282. new_rate = DIV_ROUND_CLOSEST(rate, div0);
  283. }
  284. clk_ctrl |= div0 << CLK_CTRL_DIV0_SHIFT;
  285. zynq_slcr_unlock();
  286. writel(clk_ctrl, reg);
  287. zynq_slcr_lock();
  288. return new_rate;
  289. }
  290. static ulong zynq_clk_set_gem_rate(struct zynq_clk_priv *priv, enum zynq_clk id,
  291. ulong rate)
  292. {
  293. struct clk *parent;
  294. if (zynq_clk_get_gem_rclk(id) == mio_clk)
  295. return zynq_clk_set_peripheral_rate(priv, id, rate, true);
  296. parent = &priv->gem_emio_clk[id - gem0_clk];
  297. if (parent->dev)
  298. return clk_set_rate(parent, rate);
  299. debug("%s: gem%d emio rx clock source unknown\n", __func__,
  300. id - gem0_clk);
  301. return -ENOSYS;
  302. }
  303. #endif
  304. #ifndef CONFIG_SPL_BUILD
  305. static ulong zynq_clk_get_rate(struct clk *clk)
  306. {
  307. struct zynq_clk_priv *priv = dev_get_priv(clk->dev);
  308. enum zynq_clk id = clk->id;
  309. bool two_divs = false;
  310. switch (id) {
  311. case armpll_clk ... iopll_clk:
  312. return zynq_clk_get_pll_rate(priv, id);
  313. case cpu_6or4x_clk ... cpu_1x_clk:
  314. return zynq_clk_get_cpu_rate(priv, id);
  315. case ddr2x_clk:
  316. return zynq_clk_get_ddr2x_rate(priv);
  317. case ddr3x_clk:
  318. return zynq_clk_get_ddr3x_rate(priv);
  319. case dci_clk:
  320. return zynq_clk_get_dci_rate(priv);
  321. case gem0_clk ... gem1_clk:
  322. return zynq_clk_get_gem_rate(priv, id);
  323. case fclk0_clk ... can1_clk:
  324. two_divs = true;
  325. /* fall through */
  326. case dbg_trc_clk ... dbg_apb_clk:
  327. case lqspi_clk ... pcap_clk:
  328. case sdio0_clk ... spi1_clk:
  329. return zynq_clk_get_peripheral_rate(priv, id, two_divs);
  330. case dma_clk:
  331. return zynq_clk_get_cpu_rate(priv, cpu_2x_clk);
  332. case usb0_aper_clk ... swdt_clk:
  333. return zynq_clk_get_cpu_rate(priv, cpu_1x_clk);
  334. default:
  335. return -ENXIO;
  336. }
  337. }
  338. static ulong zynq_clk_set_rate(struct clk *clk, ulong rate)
  339. {
  340. struct zynq_clk_priv *priv = dev_get_priv(clk->dev);
  341. enum zynq_clk id = clk->id;
  342. bool two_divs = false;
  343. switch (id) {
  344. case gem0_clk ... gem1_clk:
  345. return zynq_clk_set_gem_rate(priv, id, rate);
  346. case fclk0_clk ... can1_clk:
  347. two_divs = true;
  348. /* fall through */
  349. case lqspi_clk ... pcap_clk:
  350. case sdio0_clk ... spi1_clk:
  351. case dbg_trc_clk ... dbg_apb_clk:
  352. return zynq_clk_set_peripheral_rate(priv, id, rate, two_divs);
  353. default:
  354. return -ENXIO;
  355. }
  356. }
  357. #else
  358. static ulong zynq_clk_get_rate(struct clk *clk)
  359. {
  360. struct zynq_clk_priv *priv = dev_get_priv(clk->dev);
  361. enum zynq_clk id = clk->id;
  362. switch (id) {
  363. case cpu_6or4x_clk ... cpu_1x_clk:
  364. return zynq_clk_get_cpu_rate(priv, id);
  365. case ddr3x_clk:
  366. return zynq_clk_get_ddr3x_rate(priv);
  367. case lqspi_clk ... pcap_clk:
  368. case sdio0_clk ... spi1_clk:
  369. return zynq_clk_get_peripheral_rate(priv, id, 0);
  370. case i2c0_aper_clk ... i2c1_aper_clk:
  371. return zynq_clk_get_cpu_rate(priv, cpu_1x_clk);
  372. default:
  373. return -ENXIO;
  374. }
  375. }
  376. #endif
  377. static struct clk_ops zynq_clk_ops = {
  378. .get_rate = zynq_clk_get_rate,
  379. #ifndef CONFIG_SPL_BUILD
  380. .set_rate = zynq_clk_set_rate,
  381. #endif
  382. };
  383. static int zynq_clk_probe(struct udevice *dev)
  384. {
  385. struct zynq_clk_priv *priv = dev_get_priv(dev);
  386. #ifndef CONFIG_SPL_BUILD
  387. unsigned int i;
  388. char name[16];
  389. int ret;
  390. for (i = 0; i < 2; i++) {
  391. sprintf(name, "gem%d_emio_clk", i);
  392. ret = clk_get_by_name(dev, name, &priv->gem_emio_clk[i]);
  393. if (ret < 0 && ret != -ENODATA) {
  394. dev_err(dev, "failed to get %s clock\n", name);
  395. return ret;
  396. }
  397. }
  398. #endif
  399. priv->ps_clk_freq = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
  400. "ps-clk-frequency", 33333333UL);
  401. return 0;
  402. }
  403. static const struct udevice_id zynq_clk_ids[] = {
  404. { .compatible = "xlnx,ps7-clkc"},
  405. {}
  406. };
  407. U_BOOT_DRIVER(zynq_clk) = {
  408. .name = "zynq_clk",
  409. .id = UCLASS_CLK,
  410. .of_match = zynq_clk_ids,
  411. .ops = &zynq_clk_ops,
  412. .priv_auto_alloc_size = sizeof(struct zynq_clk_priv),
  413. .probe = zynq_clk_probe,
  414. };