clk_sandbox_ccf.c 6.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2019
  4. * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
  5. *
  6. * Common Clock Framework [CCF] driver for Sandbox
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <clk.h>
  11. #include <malloc.h>
  12. #include <asm/clk.h>
  13. #include <clk-uclass.h>
  14. #include <dm/devres.h>
  15. #include <linux/clk-provider.h>
  16. #include <sandbox-clk.h>
  17. #include <linux/err.h>
  18. /*
  19. * Sandbox implementation of CCF primitives necessary for clk-uclass testing
  20. *
  21. * --- Sandbox PLLv3 ---
  22. */
  23. struct clk_pllv3 {
  24. struct clk clk;
  25. u32 div_mask;
  26. u32 div_shift;
  27. };
  28. int sandbox_clk_enable_count(struct clk *clk)
  29. {
  30. struct clk *clkp = NULL;
  31. int ret;
  32. ret = clk_get_by_id(clk->id, &clkp);
  33. if (ret)
  34. return 0;
  35. return clkp->enable_count;
  36. }
  37. static ulong clk_pllv3_get_rate(struct clk *clk)
  38. {
  39. unsigned long parent_rate = clk_get_parent_rate(clk);
  40. return parent_rate * 24;
  41. }
  42. static const struct clk_ops clk_pllv3_generic_ops = {
  43. .get_rate = clk_pllv3_get_rate,
  44. };
  45. struct clk *sandbox_clk_pllv3(enum sandbox_pllv3_type type, const char *name,
  46. const char *parent_name, void __iomem *base,
  47. u32 div_mask)
  48. {
  49. struct clk_pllv3 *pll;
  50. struct clk *clk;
  51. char *drv_name = "sandbox_clk_pllv3";
  52. int ret;
  53. pll = kzalloc(sizeof(*pll), GFP_KERNEL);
  54. if (!pll)
  55. return ERR_PTR(-ENOMEM);
  56. pll->div_mask = div_mask;
  57. clk = &pll->clk;
  58. ret = clk_register(clk, drv_name, name, parent_name);
  59. if (ret) {
  60. kfree(pll);
  61. return ERR_PTR(ret);
  62. }
  63. return clk;
  64. }
  65. U_BOOT_DRIVER(sandbox_clk_pll_generic) = {
  66. .name = "sandbox_clk_pllv3",
  67. .id = UCLASS_CLK,
  68. .ops = &clk_pllv3_generic_ops,
  69. };
  70. /* --- Sandbox PLLv3 --- */
  71. /* --- Sandbox Gate --- */
  72. struct clk_gate2 {
  73. struct clk clk;
  74. bool state;
  75. };
  76. #define to_clk_gate2(_clk) container_of(_clk, struct clk_gate2, clk)
  77. static int clk_gate2_enable(struct clk *clk)
  78. {
  79. struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
  80. gate->state = 1;
  81. return 0;
  82. }
  83. static int clk_gate2_disable(struct clk *clk)
  84. {
  85. struct clk_gate2 *gate = to_clk_gate2(dev_get_clk_ptr(clk->dev));
  86. gate->state = 0;
  87. return 0;
  88. }
  89. static const struct clk_ops clk_gate2_ops = {
  90. .enable = clk_gate2_enable,
  91. .disable = clk_gate2_disable,
  92. .get_rate = clk_generic_get_rate,
  93. };
  94. struct clk *sandbox_clk_register_gate2(struct device *dev, const char *name,
  95. const char *parent_name,
  96. unsigned long flags, void __iomem *reg,
  97. u8 bit_idx, u8 cgr_val,
  98. u8 clk_gate2_flags)
  99. {
  100. struct clk_gate2 *gate;
  101. struct clk *clk;
  102. int ret;
  103. gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  104. if (!gate)
  105. return ERR_PTR(-ENOMEM);
  106. gate->state = 0;
  107. clk = &gate->clk;
  108. ret = clk_register(clk, "sandbox_clk_gate2", name, parent_name);
  109. if (ret) {
  110. kfree(gate);
  111. return ERR_PTR(ret);
  112. }
  113. return clk;
  114. }
  115. U_BOOT_DRIVER(sandbox_clk_gate2) = {
  116. .name = "sandbox_clk_gate2",
  117. .id = UCLASS_CLK,
  118. .ops = &clk_gate2_ops,
  119. };
  120. static unsigned long sandbox_clk_composite_divider_recalc_rate(struct clk *clk)
  121. {
  122. struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk);
  123. struct clk_composite *composite = (struct clk_composite *)clk->data;
  124. ulong parent_rate = clk_get_parent_rate(&composite->clk);
  125. unsigned int val;
  126. val = divider->io_divider_val;
  127. val >>= divider->shift;
  128. val &= clk_div_mask(divider->width);
  129. return divider_recalc_rate(clk, parent_rate, val, divider->table,
  130. divider->flags, divider->width);
  131. }
  132. static const struct clk_ops sandbox_clk_composite_divider_ops = {
  133. .get_rate = sandbox_clk_composite_divider_recalc_rate,
  134. };
  135. struct clk *sandbox_clk_composite(const char *name,
  136. const char * const *parent_names,
  137. int num_parents, void __iomem *reg,
  138. unsigned long flags)
  139. {
  140. struct clk *clk = ERR_PTR(-ENOMEM);
  141. struct clk_divider *div = NULL;
  142. struct clk_gate *gate = NULL;
  143. struct clk_mux *mux = NULL;
  144. mux = kzalloc(sizeof(*mux), GFP_KERNEL);
  145. if (!mux)
  146. goto fail;
  147. mux->reg = reg;
  148. mux->shift = 24;
  149. mux->mask = 0x7;
  150. mux->num_parents = num_parents;
  151. mux->flags = flags;
  152. mux->parent_names = parent_names;
  153. div = kzalloc(sizeof(*div), GFP_KERNEL);
  154. if (!div)
  155. goto fail;
  156. div->reg = reg;
  157. div->shift = 16;
  158. div->width = 3;
  159. div->flags = CLK_DIVIDER_ROUND_CLOSEST | flags;
  160. gate = kzalloc(sizeof(*gate), GFP_KERNEL);
  161. if (!gate)
  162. goto fail;
  163. gate->reg = reg;
  164. gate->bit_idx = 28;
  165. gate->flags = flags;
  166. clk = clk_register_composite(NULL, name,
  167. parent_names, num_parents,
  168. &mux->clk, &clk_mux_ops, &div->clk,
  169. &sandbox_clk_composite_divider_ops,
  170. &gate->clk, &clk_gate_ops, flags);
  171. if (IS_ERR(clk))
  172. goto fail;
  173. return clk;
  174. fail:
  175. kfree(gate);
  176. kfree(div);
  177. kfree(mux);
  178. return ERR_CAST(clk);
  179. }
  180. /* --- Sandbox Gate --- */
  181. /* The CCF core driver itself */
  182. static const struct udevice_id sandbox_clk_ccf_test_ids[] = {
  183. { .compatible = "sandbox,clk-ccf" },
  184. { }
  185. };
  186. static const char *const usdhc_sels[] = { "pll3_60m", "pll3_80m", };
  187. static const char *const i2c_sels[] = { "pll3_60m", "pll3_80m", };
  188. static int sandbox_clk_ccf_probe(struct udevice *dev)
  189. {
  190. void *base = NULL;
  191. u32 reg;
  192. clk_dm(SANDBOX_CLK_PLL3,
  193. sandbox_clk_pllv3(SANDBOX_PLLV3_USB, "pll3_usb_otg", "osc",
  194. base + 0x10, 0x3));
  195. clk_dm(SANDBOX_CLK_PLL3_60M,
  196. sandbox_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8));
  197. clk_dm(SANDBOX_CLK_PLL3_80M,
  198. sandbox_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6));
  199. /* The HW adds +1 to the divider value (2+1) is the divider */
  200. reg = (2 << 19);
  201. clk_dm(SANDBOX_CLK_ECSPI_ROOT,
  202. sandbox_clk_divider("ecspi_root", "pll3_60m", &reg, 19, 6));
  203. clk_dm(SANDBOX_CLK_ECSPI1,
  204. sandbox_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0));
  205. /* Select 'pll3_60m' */
  206. reg = 0;
  207. clk_dm(SANDBOX_CLK_USDHC1_SEL,
  208. sandbox_clk_mux("usdhc1_sel", &reg, 16, 1, usdhc_sels,
  209. ARRAY_SIZE(usdhc_sels)));
  210. /* Select 'pll3_80m' */
  211. reg = BIT(17);
  212. clk_dm(SANDBOX_CLK_USDHC2_SEL,
  213. sandbox_clk_mux("usdhc2_sel", &reg, 17, 1, usdhc_sels,
  214. ARRAY_SIZE(usdhc_sels)));
  215. reg = BIT(28) | BIT(24) | BIT(16);
  216. clk_dm(SANDBOX_CLK_I2C,
  217. sandbox_clk_composite("i2c", i2c_sels, ARRAY_SIZE(i2c_sels),
  218. &reg, 0));
  219. clk_dm(SANDBOX_CLK_I2C_ROOT,
  220. sandbox_clk_gate2("i2c_root", "i2c", base + 0x7c, 0));
  221. return 0;
  222. }
  223. U_BOOT_DRIVER(sandbox_clk_ccf) = {
  224. .name = "sandbox_clk_ccf",
  225. .id = UCLASS_CLK,
  226. .probe = sandbox_clk_ccf_probe,
  227. .of_match = sandbox_clk_ccf_test_ids,
  228. };