stm32-adc.c 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. * Author: Fabrice Gasnier <fabrice.gasnier@st.com>
  5. *
  6. * Originally based on the Linux kernel v4.18 drivers/iio/adc/stm32-adc.c.
  7. */
  8. #include <common.h>
  9. #include <adc.h>
  10. #include <asm/io.h>
  11. #include <dm/device_compat.h>
  12. #include <linux/iopoll.h>
  13. #include "stm32-adc-core.h"
  14. /* STM32H7 - Registers for each ADC instance */
  15. #define STM32H7_ADC_ISR 0x00
  16. #define STM32H7_ADC_CR 0x08
  17. #define STM32H7_ADC_CFGR 0x0C
  18. #define STM32H7_ADC_SMPR1 0x14
  19. #define STM32H7_ADC_SMPR2 0x18
  20. #define STM32H7_ADC_PCSEL 0x1C
  21. #define STM32H7_ADC_SQR1 0x30
  22. #define STM32H7_ADC_DR 0x40
  23. #define STM32H7_ADC_DIFSEL 0xC0
  24. /* STM32H7_ADC_ISR - bit fields */
  25. #define STM32MP1_VREGREADY BIT(12)
  26. #define STM32H7_EOC BIT(2)
  27. #define STM32H7_ADRDY BIT(0)
  28. /* STM32H7_ADC_CR - bit fields */
  29. #define STM32H7_DEEPPWD BIT(29)
  30. #define STM32H7_ADVREGEN BIT(28)
  31. #define STM32H7_BOOST BIT(8)
  32. #define STM32H7_ADSTART BIT(2)
  33. #define STM32H7_ADDIS BIT(1)
  34. #define STM32H7_ADEN BIT(0)
  35. /* STM32H7_ADC_CFGR bit fields */
  36. #define STM32H7_EXTEN GENMASK(11, 10)
  37. #define STM32H7_DMNGT GENMASK(1, 0)
  38. /* STM32H7_ADC_SQR1 - bit fields */
  39. #define STM32H7_SQ1_SHIFT 6
  40. /* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */
  41. #define STM32H7_BOOST_CLKRATE 20000000UL
  42. #define STM32_ADC_CH_MAX 20 /* max number of channels */
  43. #define STM32_ADC_TIMEOUT_US 100000
  44. struct stm32_adc_cfg {
  45. unsigned int max_channels;
  46. unsigned int num_bits;
  47. bool has_vregready;
  48. };
  49. struct stm32_adc {
  50. void __iomem *regs;
  51. int active_channel;
  52. const struct stm32_adc_cfg *cfg;
  53. };
  54. static int stm32_adc_stop(struct udevice *dev)
  55. {
  56. struct stm32_adc *adc = dev_get_priv(dev);
  57. setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADDIS);
  58. clrbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_BOOST);
  59. /* Setting DEEPPWD disables ADC vreg and clears ADVREGEN */
  60. setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_DEEPPWD);
  61. adc->active_channel = -1;
  62. return 0;
  63. }
  64. static int stm32_adc_start_channel(struct udevice *dev, int channel)
  65. {
  66. struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
  67. struct stm32_adc_common *common = dev_get_priv(dev_get_parent(dev));
  68. struct stm32_adc *adc = dev_get_priv(dev);
  69. int ret;
  70. u32 val;
  71. /* Exit deep power down, then enable ADC voltage regulator */
  72. clrbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_DEEPPWD);
  73. setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADVREGEN);
  74. if (common->rate > STM32H7_BOOST_CLKRATE)
  75. setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_BOOST);
  76. /* Wait for startup time */
  77. if (!adc->cfg->has_vregready) {
  78. udelay(20);
  79. } else {
  80. ret = readl_poll_timeout(adc->regs + STM32H7_ADC_ISR, val,
  81. val & STM32MP1_VREGREADY,
  82. STM32_ADC_TIMEOUT_US);
  83. if (ret < 0) {
  84. stm32_adc_stop(dev);
  85. dev_err(dev, "Failed to enable vreg: %d\n", ret);
  86. return ret;
  87. }
  88. }
  89. /* Only use single ended channels */
  90. writel(0, adc->regs + STM32H7_ADC_DIFSEL);
  91. /* Enable ADC, Poll for ADRDY to be set (after adc startup time) */
  92. setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADEN);
  93. ret = readl_poll_timeout(adc->regs + STM32H7_ADC_ISR, val,
  94. val & STM32H7_ADRDY, STM32_ADC_TIMEOUT_US);
  95. if (ret < 0) {
  96. stm32_adc_stop(dev);
  97. dev_err(dev, "Failed to enable ADC: %d\n", ret);
  98. return ret;
  99. }
  100. /* Preselect channels */
  101. writel(uc_pdata->channel_mask, adc->regs + STM32H7_ADC_PCSEL);
  102. /* Set sampling time to max value by default */
  103. writel(0xffffffff, adc->regs + STM32H7_ADC_SMPR1);
  104. writel(0xffffffff, adc->regs + STM32H7_ADC_SMPR2);
  105. /* Program regular sequence: chan in SQ1 & len = 0 for one channel */
  106. writel(channel << STM32H7_SQ1_SHIFT, adc->regs + STM32H7_ADC_SQR1);
  107. /* Trigger detection disabled (conversion can be launched in SW) */
  108. clrbits_le32(adc->regs + STM32H7_ADC_CFGR, STM32H7_EXTEN |
  109. STM32H7_DMNGT);
  110. adc->active_channel = channel;
  111. return 0;
  112. }
  113. static int stm32_adc_channel_data(struct udevice *dev, int channel,
  114. unsigned int *data)
  115. {
  116. struct stm32_adc *adc = dev_get_priv(dev);
  117. int ret;
  118. u32 val;
  119. if (channel != adc->active_channel) {
  120. dev_err(dev, "Requested channel is not active!\n");
  121. return -EINVAL;
  122. }
  123. setbits_le32(adc->regs + STM32H7_ADC_CR, STM32H7_ADSTART);
  124. ret = readl_poll_timeout(adc->regs + STM32H7_ADC_ISR, val,
  125. val & STM32H7_EOC, STM32_ADC_TIMEOUT_US);
  126. if (ret < 0) {
  127. dev_err(dev, "conversion timed out: %d\n", ret);
  128. return ret;
  129. }
  130. *data = readl(adc->regs + STM32H7_ADC_DR);
  131. return 0;
  132. }
  133. static int stm32_adc_chan_of_init(struct udevice *dev)
  134. {
  135. struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
  136. struct stm32_adc *adc = dev_get_priv(dev);
  137. u32 chans[STM32_ADC_CH_MAX];
  138. unsigned int i, num_channels;
  139. int ret;
  140. /* Retrieve single ended channels listed in device tree */
  141. ret = dev_read_size(dev, "st,adc-channels");
  142. if (ret < 0) {
  143. dev_err(dev, "can't get st,adc-channels: %d\n", ret);
  144. return ret;
  145. }
  146. num_channels = ret / sizeof(u32);
  147. if (num_channels > adc->cfg->max_channels) {
  148. dev_err(dev, "too many st,adc-channels: %d\n", num_channels);
  149. return -EINVAL;
  150. }
  151. ret = dev_read_u32_array(dev, "st,adc-channels", chans, num_channels);
  152. if (ret < 0) {
  153. dev_err(dev, "can't read st,adc-channels: %d\n", ret);
  154. return ret;
  155. }
  156. for (i = 0; i < num_channels; i++) {
  157. if (chans[i] >= adc->cfg->max_channels) {
  158. dev_err(dev, "bad channel %u\n", chans[i]);
  159. return -EINVAL;
  160. }
  161. uc_pdata->channel_mask |= 1 << chans[i];
  162. }
  163. uc_pdata->data_mask = (1 << adc->cfg->num_bits) - 1;
  164. uc_pdata->data_format = ADC_DATA_FORMAT_BIN;
  165. uc_pdata->data_timeout_us = 100000;
  166. return 0;
  167. }
  168. static int stm32_adc_probe(struct udevice *dev)
  169. {
  170. struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
  171. struct stm32_adc_common *common = dev_get_priv(dev_get_parent(dev));
  172. struct stm32_adc *adc = dev_get_priv(dev);
  173. int offset;
  174. offset = dev_read_u32_default(dev, "reg", -ENODATA);
  175. if (offset < 0) {
  176. dev_err(dev, "Can't read reg property\n");
  177. return offset;
  178. }
  179. adc->regs = common->base + offset;
  180. adc->cfg = (const struct stm32_adc_cfg *)dev_get_driver_data(dev);
  181. /* VDD supplied by common vref pin */
  182. uc_pdata->vdd_supply = common->vref;
  183. uc_pdata->vdd_microvolts = common->vref_uv;
  184. uc_pdata->vss_microvolts = 0;
  185. return stm32_adc_chan_of_init(dev);
  186. }
  187. static const struct adc_ops stm32_adc_ops = {
  188. .start_channel = stm32_adc_start_channel,
  189. .channel_data = stm32_adc_channel_data,
  190. .stop = stm32_adc_stop,
  191. };
  192. static const struct stm32_adc_cfg stm32h7_adc_cfg = {
  193. .num_bits = 16,
  194. .max_channels = STM32_ADC_CH_MAX,
  195. };
  196. static const struct stm32_adc_cfg stm32mp1_adc_cfg = {
  197. .num_bits = 16,
  198. .max_channels = STM32_ADC_CH_MAX,
  199. .has_vregready = true,
  200. };
  201. static const struct udevice_id stm32_adc_ids[] = {
  202. { .compatible = "st,stm32h7-adc",
  203. .data = (ulong)&stm32h7_adc_cfg },
  204. { .compatible = "st,stm32mp1-adc",
  205. .data = (ulong)&stm32mp1_adc_cfg },
  206. {}
  207. };
  208. U_BOOT_DRIVER(stm32_adc) = {
  209. .name = "stm32-adc",
  210. .id = UCLASS_ADC,
  211. .of_match = stm32_adc_ids,
  212. .probe = stm32_adc_probe,
  213. .ops = &stm32_adc_ops,
  214. .priv_auto_alloc_size = sizeof(struct stm32_adc),
  215. };