stm32-adc-core.c 5.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. * Author: Fabrice Gasnier <fabrice.gasnier@st.com>
  5. *
  6. * Originally based on the Linux kernel v4.18 drivers/iio/adc/stm32-adc-core.c.
  7. */
  8. #include <common.h>
  9. #include <asm/io.h>
  10. #include <dm/device_compat.h>
  11. #include <power/regulator.h>
  12. #include "stm32-adc-core.h"
  13. /* STM32H7 - common registers for all ADC instances */
  14. #define STM32H7_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x08)
  15. /* STM32H7_ADC_CCR - bit fields */
  16. #define STM32H7_PRESC_SHIFT 18
  17. #define STM32H7_PRESC_MASK GENMASK(21, 18)
  18. #define STM32H7_CKMODE_SHIFT 16
  19. #define STM32H7_CKMODE_MASK GENMASK(17, 16)
  20. /* STM32 H7 maximum analog clock rate (from datasheet) */
  21. #define STM32H7_ADC_MAX_CLK_RATE 36000000
  22. /**
  23. * struct stm32h7_adc_ck_spec - specification for stm32h7 adc clock
  24. * @ckmode: ADC clock mode, Async or sync with prescaler.
  25. * @presc: prescaler bitfield for async clock mode
  26. * @div: prescaler division ratio
  27. */
  28. struct stm32h7_adc_ck_spec {
  29. u32 ckmode;
  30. u32 presc;
  31. int div;
  32. };
  33. static const struct stm32h7_adc_ck_spec stm32h7_adc_ckmodes_spec[] = {
  34. /* 00: CK_ADC[1..3]: Asynchronous clock modes */
  35. { 0, 0, 1 },
  36. { 0, 1, 2 },
  37. { 0, 2, 4 },
  38. { 0, 3, 6 },
  39. { 0, 4, 8 },
  40. { 0, 5, 10 },
  41. { 0, 6, 12 },
  42. { 0, 7, 16 },
  43. { 0, 8, 32 },
  44. { 0, 9, 64 },
  45. { 0, 10, 128 },
  46. { 0, 11, 256 },
  47. /* HCLK used: Synchronous clock modes (1, 2 or 4 prescaler) */
  48. { 1, 0, 1 },
  49. { 2, 0, 2 },
  50. { 3, 0, 4 },
  51. };
  52. static int stm32h7_adc_clk_sel(struct udevice *dev,
  53. struct stm32_adc_common *common)
  54. {
  55. u32 ckmode, presc;
  56. unsigned long rate;
  57. unsigned int i;
  58. int div;
  59. /* stm32h7 bus clock is common for all ADC instances (mandatory) */
  60. if (!clk_valid(&common->bclk)) {
  61. dev_err(dev, "No bclk clock found\n");
  62. return -ENOENT;
  63. }
  64. /*
  65. * stm32h7 can use either 'bus' or 'adc' clock for analog circuitry.
  66. * So, choice is to have bus clock mandatory and adc clock optional.
  67. * If optional 'adc' clock has been found, then try to use it first.
  68. */
  69. if (clk_valid(&common->aclk)) {
  70. /*
  71. * Asynchronous clock modes (e.g. ckmode == 0)
  72. * From spec: PLL output musn't exceed max rate
  73. */
  74. rate = clk_get_rate(&common->aclk);
  75. if (!rate) {
  76. dev_err(dev, "Invalid aclk rate: 0\n");
  77. return -EINVAL;
  78. }
  79. for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
  80. ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
  81. presc = stm32h7_adc_ckmodes_spec[i].presc;
  82. div = stm32h7_adc_ckmodes_spec[i].div;
  83. if (ckmode)
  84. continue;
  85. if ((rate / div) <= STM32H7_ADC_MAX_CLK_RATE)
  86. goto out;
  87. }
  88. }
  89. /* Synchronous clock modes (e.g. ckmode is 1, 2 or 3) */
  90. rate = clk_get_rate(&common->bclk);
  91. if (!rate) {
  92. dev_err(dev, "Invalid bus clock rate: 0\n");
  93. return -EINVAL;
  94. }
  95. for (i = 0; i < ARRAY_SIZE(stm32h7_adc_ckmodes_spec); i++) {
  96. ckmode = stm32h7_adc_ckmodes_spec[i].ckmode;
  97. presc = stm32h7_adc_ckmodes_spec[i].presc;
  98. div = stm32h7_adc_ckmodes_spec[i].div;
  99. if (!ckmode)
  100. continue;
  101. if ((rate / div) <= STM32H7_ADC_MAX_CLK_RATE)
  102. goto out;
  103. }
  104. dev_err(dev, "clk selection failed\n");
  105. return -EINVAL;
  106. out:
  107. /* rate used later by each ADC instance to control BOOST mode */
  108. common->rate = rate / div;
  109. /* Set common clock mode and prescaler */
  110. clrsetbits_le32(common->base + STM32H7_ADC_CCR,
  111. STM32H7_CKMODE_MASK | STM32H7_PRESC_MASK,
  112. ckmode << STM32H7_CKMODE_SHIFT |
  113. presc << STM32H7_PRESC_SHIFT);
  114. dev_dbg(dev, "Using %s clock/%d source at %ld kHz\n",
  115. ckmode ? "bus" : "adc", div, common->rate / 1000);
  116. return 0;
  117. }
  118. static int stm32_adc_core_probe(struct udevice *dev)
  119. {
  120. struct stm32_adc_common *common = dev_get_priv(dev);
  121. int ret;
  122. common->base = dev_read_addr_ptr(dev);
  123. if (!common->base) {
  124. dev_err(dev, "can't get address\n");
  125. return -ENOENT;
  126. }
  127. ret = device_get_supply_regulator(dev, "vref-supply", &common->vref);
  128. if (ret) {
  129. dev_err(dev, "can't get vref-supply: %d\n", ret);
  130. return ret;
  131. }
  132. ret = regulator_get_value(common->vref);
  133. if (ret < 0) {
  134. dev_err(dev, "can't get vref-supply value: %d\n", ret);
  135. return ret;
  136. }
  137. common->vref_uv = ret;
  138. ret = clk_get_by_name(dev, "adc", &common->aclk);
  139. if (!ret) {
  140. ret = clk_enable(&common->aclk);
  141. if (ret) {
  142. dev_err(dev, "Can't enable aclk: %d\n", ret);
  143. return ret;
  144. }
  145. }
  146. ret = clk_get_by_name(dev, "bus", &common->bclk);
  147. if (!ret) {
  148. ret = clk_enable(&common->bclk);
  149. if (ret) {
  150. dev_err(dev, "Can't enable bclk: %d\n", ret);
  151. goto err_aclk_disable;
  152. }
  153. }
  154. ret = stm32h7_adc_clk_sel(dev, common);
  155. if (ret)
  156. goto err_bclk_disable;
  157. return ret;
  158. err_bclk_disable:
  159. if (clk_valid(&common->bclk))
  160. clk_disable(&common->bclk);
  161. err_aclk_disable:
  162. if (clk_valid(&common->aclk))
  163. clk_disable(&common->aclk);
  164. return ret;
  165. }
  166. static const struct udevice_id stm32_adc_core_ids[] = {
  167. { .compatible = "st,stm32h7-adc-core" },
  168. { .compatible = "st,stm32mp1-adc-core" },
  169. {}
  170. };
  171. U_BOOT_DRIVER(stm32_adc_core) = {
  172. .name = "stm32-adc-core",
  173. .id = UCLASS_SIMPLE_BUS,
  174. .of_match = stm32_adc_core_ids,
  175. .probe = stm32_adc_core_probe,
  176. .priv_auto_alloc_size = sizeof(struct stm32_adc_common),
  177. };