board.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * board.c
  4. *
  5. * Board functions for TI AM335X based boards
  6. *
  7. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <env.h>
  12. #include <errno.h>
  13. #include <init.h>
  14. #include <malloc.h>
  15. #include <spl.h>
  16. #include <serial.h>
  17. #include <asm/arch/cpu.h>
  18. #include <asm/arch/hardware.h>
  19. #include <asm/arch/omap.h>
  20. #include <asm/arch/ddr_defs.h>
  21. #include <asm/arch/clock.h>
  22. #include <asm/arch/clk_synthesizer.h>
  23. #include <asm/arch/gpio.h>
  24. #include <asm/arch/mmc_host_def.h>
  25. #include <asm/arch/sys_proto.h>
  26. #include <asm/arch/mem.h>
  27. #include <asm/io.h>
  28. #include <asm/emif.h>
  29. #include <asm/gpio.h>
  30. #include <asm/omap_common.h>
  31. #include <asm/omap_sec_common.h>
  32. #include <asm/omap_mmc.h>
  33. #include <i2c.h>
  34. #include <miiphy.h>
  35. #include <cpsw.h>
  36. #include <power/tps65217.h>
  37. #include <power/tps65910.h>
  38. #include <env_internal.h>
  39. #include <watchdog.h>
  40. #include "../common/board_detect.h"
  41. #include "board.h"
  42. DECLARE_GLOBAL_DATA_PTR;
  43. /* GPIO that controls power to DDR on EVM-SK */
  44. #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
  45. #define GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 7)
  46. #define ICE_GPIO_DDR_VTT_EN GPIO_TO_PIN(0, 18)
  47. #define GPIO_PR1_MII_CTRL GPIO_TO_PIN(3, 4)
  48. #define GPIO_MUX_MII_CTRL GPIO_TO_PIN(3, 10)
  49. #define GPIO_FET_SWITCH_CTRL GPIO_TO_PIN(0, 7)
  50. #define GPIO_PHY_RESET GPIO_TO_PIN(2, 5)
  51. #define GPIO_ETH0_MODE GPIO_TO_PIN(0, 11)
  52. #define GPIO_ETH1_MODE GPIO_TO_PIN(1, 26)
  53. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  54. #define GPIO0_RISINGDETECT (AM33XX_GPIO0_BASE + OMAP_GPIO_RISINGDETECT)
  55. #define GPIO1_RISINGDETECT (AM33XX_GPIO1_BASE + OMAP_GPIO_RISINGDETECT)
  56. #define GPIO0_IRQSTATUS1 (AM33XX_GPIO0_BASE + OMAP_GPIO_IRQSTATUS1)
  57. #define GPIO1_IRQSTATUS1 (AM33XX_GPIO1_BASE + OMAP_GPIO_IRQSTATUS1)
  58. #define GPIO0_IRQSTATUSRAW (AM33XX_GPIO0_BASE + 0x024)
  59. #define GPIO1_IRQSTATUSRAW (AM33XX_GPIO1_BASE + 0x024)
  60. /*
  61. * Read header information from EEPROM into global structure.
  62. */
  63. #ifdef CONFIG_TI_I2C_BOARD_DETECT
  64. void do_board_detect(void)
  65. {
  66. enable_i2c0_pin_mux();
  67. #ifndef CONFIG_DM_I2C
  68. i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
  69. #endif
  70. if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
  71. CONFIG_EEPROM_CHIP_ADDRESS))
  72. printf("ti_i2c_eeprom_init failed\n");
  73. }
  74. #endif
  75. #ifndef CONFIG_DM_SERIAL
  76. struct serial_device *default_serial_console(void)
  77. {
  78. if (board_is_icev2())
  79. return &eserial4_device;
  80. else
  81. return &eserial1_device;
  82. }
  83. #endif
  84. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  85. static const struct ddr_data ddr2_data = {
  86. .datardsratio0 = MT47H128M16RT25E_RD_DQS,
  87. .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
  88. .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
  89. };
  90. static const struct cmd_control ddr2_cmd_ctrl_data = {
  91. .cmd0csratio = MT47H128M16RT25E_RATIO,
  92. .cmd1csratio = MT47H128M16RT25E_RATIO,
  93. .cmd2csratio = MT47H128M16RT25E_RATIO,
  94. };
  95. static const struct emif_regs ddr2_emif_reg_data = {
  96. .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
  97. .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
  98. .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
  99. .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
  100. .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
  101. .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
  102. };
  103. static const struct emif_regs ddr2_evm_emif_reg_data = {
  104. .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
  105. .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
  106. .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
  107. .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
  108. .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
  109. .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
  110. .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
  111. };
  112. static const struct ddr_data ddr3_data = {
  113. .datardsratio0 = MT41J128MJT125_RD_DQS,
  114. .datawdsratio0 = MT41J128MJT125_WR_DQS,
  115. .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
  116. .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
  117. };
  118. static const struct ddr_data ddr3_beagleblack_data = {
  119. .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  120. .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  121. .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  122. .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  123. };
  124. static const struct ddr_data ddr3_evm_data = {
  125. .datardsratio0 = MT41J512M8RH125_RD_DQS,
  126. .datawdsratio0 = MT41J512M8RH125_WR_DQS,
  127. .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
  128. .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
  129. };
  130. static const struct ddr_data ddr3_icev2_data = {
  131. .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz,
  132. .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz,
  133. .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz,
  134. .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz,
  135. };
  136. static const struct cmd_control ddr3_cmd_ctrl_data = {
  137. .cmd0csratio = MT41J128MJT125_RATIO,
  138. .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
  139. .cmd1csratio = MT41J128MJT125_RATIO,
  140. .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
  141. .cmd2csratio = MT41J128MJT125_RATIO,
  142. .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
  143. };
  144. static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
  145. .cmd0csratio = MT41K256M16HA125E_RATIO,
  146. .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  147. .cmd1csratio = MT41K256M16HA125E_RATIO,
  148. .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  149. .cmd2csratio = MT41K256M16HA125E_RATIO,
  150. .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  151. };
  152. static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
  153. .cmd0csratio = MT41J512M8RH125_RATIO,
  154. .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
  155. .cmd1csratio = MT41J512M8RH125_RATIO,
  156. .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
  157. .cmd2csratio = MT41J512M8RH125_RATIO,
  158. .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
  159. };
  160. static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
  161. .cmd0csratio = MT41J128MJT125_RATIO_400MHz,
  162. .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
  163. .cmd1csratio = MT41J128MJT125_RATIO_400MHz,
  164. .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
  165. .cmd2csratio = MT41J128MJT125_RATIO_400MHz,
  166. .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
  167. };
  168. static struct emif_regs ddr3_emif_reg_data = {
  169. .sdram_config = MT41J128MJT125_EMIF_SDCFG,
  170. .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
  171. .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
  172. .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
  173. .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
  174. .zq_config = MT41J128MJT125_ZQ_CFG,
  175. .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
  176. PHY_EN_DYN_PWRDN,
  177. };
  178. static struct emif_regs ddr3_beagleblack_emif_reg_data = {
  179. .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  180. .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  181. .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  182. .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  183. .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  184. .ocp_config = EMIF_OCP_CONFIG_BEAGLEBONE_BLACK,
  185. .zq_config = MT41K256M16HA125E_ZQ_CFG,
  186. .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  187. };
  188. static struct emif_regs ddr3_evm_emif_reg_data = {
  189. .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
  190. .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
  191. .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
  192. .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
  193. .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
  194. .ocp_config = EMIF_OCP_CONFIG_AM335X_EVM,
  195. .zq_config = MT41J512M8RH125_ZQ_CFG,
  196. .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
  197. PHY_EN_DYN_PWRDN,
  198. };
  199. static struct emif_regs ddr3_icev2_emif_reg_data = {
  200. .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz,
  201. .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz,
  202. .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz,
  203. .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz,
  204. .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz,
  205. .zq_config = MT41J128MJT125_ZQ_CFG_400MHz,
  206. .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz |
  207. PHY_EN_DYN_PWRDN,
  208. };
  209. #ifdef CONFIG_SPL_OS_BOOT
  210. int spl_start_uboot(void)
  211. {
  212. #ifdef CONFIG_SPL_SERIAL_SUPPORT
  213. /* break into full u-boot on 'c' */
  214. if (serial_tstc() && serial_getc() == 'c')
  215. return 1;
  216. #endif
  217. #ifdef CONFIG_SPL_ENV_SUPPORT
  218. env_init();
  219. env_load();
  220. if (env_get_yesno("boot_os") != 1)
  221. return 1;
  222. #endif
  223. return 0;
  224. }
  225. #endif
  226. const struct dpll_params *get_dpll_ddr_params(void)
  227. {
  228. int ind = get_sys_clk_index();
  229. if (board_is_evm_sk())
  230. return &dpll_ddr3_303MHz[ind];
  231. else if (board_is_pb() || board_is_bone_lt() || board_is_icev2())
  232. return &dpll_ddr3_400MHz[ind];
  233. else if (board_is_evm_15_or_later())
  234. return &dpll_ddr3_303MHz[ind];
  235. else
  236. return &dpll_ddr2_266MHz[ind];
  237. }
  238. static u8 bone_not_connected_to_ac_power(void)
  239. {
  240. if (board_is_bone()) {
  241. uchar pmic_status_reg;
  242. if (tps65217_reg_read(TPS65217_STATUS,
  243. &pmic_status_reg))
  244. return 1;
  245. if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
  246. puts("No AC power, switching to default OPP\n");
  247. return 1;
  248. }
  249. }
  250. return 0;
  251. }
  252. const struct dpll_params *get_dpll_mpu_params(void)
  253. {
  254. int ind = get_sys_clk_index();
  255. int freq = am335x_get_efuse_mpu_max_freq(cdev);
  256. if (bone_not_connected_to_ac_power())
  257. freq = MPUPLL_M_600;
  258. if (board_is_pb() || board_is_bone_lt())
  259. freq = MPUPLL_M_1000;
  260. switch (freq) {
  261. case MPUPLL_M_1000:
  262. return &dpll_mpu_opp[ind][5];
  263. case MPUPLL_M_800:
  264. return &dpll_mpu_opp[ind][4];
  265. case MPUPLL_M_720:
  266. return &dpll_mpu_opp[ind][3];
  267. case MPUPLL_M_600:
  268. return &dpll_mpu_opp[ind][2];
  269. case MPUPLL_M_500:
  270. return &dpll_mpu_opp100;
  271. case MPUPLL_M_300:
  272. return &dpll_mpu_opp[ind][0];
  273. }
  274. return &dpll_mpu_opp[ind][0];
  275. }
  276. static void scale_vcores_bone(int freq)
  277. {
  278. int usb_cur_lim, mpu_vdd;
  279. /*
  280. * Only perform PMIC configurations if board rev > A1
  281. * on Beaglebone White
  282. */
  283. if (board_is_bone() && !strncmp(board_ti_get_rev(), "00A1", 4))
  284. return;
  285. #ifndef CONFIG_DM_I2C
  286. if (i2c_probe(TPS65217_CHIP_PM))
  287. return;
  288. #else
  289. if (power_tps65217_init(0))
  290. return;
  291. #endif
  292. /*
  293. * On Beaglebone White we need to ensure we have AC power
  294. * before increasing the frequency.
  295. */
  296. if (bone_not_connected_to_ac_power())
  297. freq = MPUPLL_M_600;
  298. /*
  299. * Override what we have detected since we know if we have
  300. * a Beaglebone Black it supports 1GHz.
  301. */
  302. if (board_is_pb() || board_is_bone_lt())
  303. freq = MPUPLL_M_1000;
  304. switch (freq) {
  305. case MPUPLL_M_1000:
  306. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
  307. usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
  308. break;
  309. case MPUPLL_M_800:
  310. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
  311. usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
  312. break;
  313. case MPUPLL_M_720:
  314. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
  315. usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
  316. break;
  317. case MPUPLL_M_600:
  318. case MPUPLL_M_500:
  319. case MPUPLL_M_300:
  320. default:
  321. mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
  322. usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
  323. break;
  324. }
  325. if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
  326. TPS65217_POWER_PATH,
  327. usb_cur_lim,
  328. TPS65217_USB_INPUT_CUR_LIMIT_MASK))
  329. puts("tps65217_reg_write failure\n");
  330. /* Set DCDC3 (CORE) voltage to 1.10V */
  331. if (tps65217_voltage_update(TPS65217_DEFDCDC3,
  332. TPS65217_DCDC_VOLT_SEL_1100MV)) {
  333. puts("tps65217_voltage_update failure\n");
  334. return;
  335. }
  336. /* Set DCDC2 (MPU) voltage */
  337. if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
  338. puts("tps65217_voltage_update failure\n");
  339. return;
  340. }
  341. /*
  342. * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
  343. * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
  344. */
  345. if (board_is_bone()) {
  346. if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
  347. TPS65217_DEFLS1,
  348. TPS65217_LDO_VOLTAGE_OUT_3_3,
  349. TPS65217_LDO_MASK))
  350. puts("tps65217_reg_write failure\n");
  351. } else {
  352. if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
  353. TPS65217_DEFLS1,
  354. TPS65217_LDO_VOLTAGE_OUT_1_8,
  355. TPS65217_LDO_MASK))
  356. puts("tps65217_reg_write failure\n");
  357. }
  358. if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
  359. TPS65217_DEFLS2,
  360. TPS65217_LDO_VOLTAGE_OUT_3_3,
  361. TPS65217_LDO_MASK))
  362. puts("tps65217_reg_write failure\n");
  363. }
  364. void scale_vcores_generic(int freq)
  365. {
  366. int sil_rev, mpu_vdd;
  367. /*
  368. * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
  369. * MPU frequencies we support we use a CORE voltage of
  370. * 1.10V. For MPU voltage we need to switch based on
  371. * the frequency we are running at.
  372. */
  373. #ifndef CONFIG_DM_I2C
  374. if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
  375. return;
  376. #else
  377. if (power_tps65910_init(0))
  378. return;
  379. #endif
  380. /*
  381. * Depending on MPU clock and PG we will need a different
  382. * VDD to drive at that speed.
  383. */
  384. sil_rev = readl(&cdev->deviceid) >> 28;
  385. mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
  386. /* Tell the TPS65910 to use i2c */
  387. tps65910_set_i2c_control();
  388. /* First update MPU voltage. */
  389. if (tps65910_voltage_update(MPU, mpu_vdd))
  390. return;
  391. /* Second, update the CORE voltage. */
  392. if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
  393. return;
  394. }
  395. void gpi2c_init(void)
  396. {
  397. /* When needed to be invoked prior to BSS initialization */
  398. static bool first_time = true;
  399. if (first_time) {
  400. enable_i2c0_pin_mux();
  401. #ifndef CONFIG_DM_I2C
  402. i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED,
  403. CONFIG_SYS_OMAP24_I2C_SLAVE);
  404. #endif
  405. first_time = false;
  406. }
  407. }
  408. void scale_vcores(void)
  409. {
  410. int freq;
  411. gpi2c_init();
  412. freq = am335x_get_efuse_mpu_max_freq(cdev);
  413. if (board_is_beaglebonex())
  414. scale_vcores_bone(freq);
  415. else
  416. scale_vcores_generic(freq);
  417. }
  418. void set_uart_mux_conf(void)
  419. {
  420. #if CONFIG_CONS_INDEX == 1
  421. enable_uart0_pin_mux();
  422. #elif CONFIG_CONS_INDEX == 2
  423. enable_uart1_pin_mux();
  424. #elif CONFIG_CONS_INDEX == 3
  425. enable_uart2_pin_mux();
  426. #elif CONFIG_CONS_INDEX == 4
  427. enable_uart3_pin_mux();
  428. #elif CONFIG_CONS_INDEX == 5
  429. enable_uart4_pin_mux();
  430. #elif CONFIG_CONS_INDEX == 6
  431. enable_uart5_pin_mux();
  432. #endif
  433. }
  434. void set_mux_conf_regs(void)
  435. {
  436. enable_board_pin_mux();
  437. }
  438. const struct ctrl_ioregs ioregs_evmsk = {
  439. .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
  440. .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
  441. .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
  442. .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
  443. .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
  444. };
  445. const struct ctrl_ioregs ioregs_bonelt = {
  446. .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  447. .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  448. .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  449. .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  450. .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  451. };
  452. const struct ctrl_ioregs ioregs_evm15 = {
  453. .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
  454. .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
  455. .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE,
  456. .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
  457. .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
  458. };
  459. const struct ctrl_ioregs ioregs = {
  460. .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  461. .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  462. .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  463. .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  464. .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  465. };
  466. void sdram_init(void)
  467. {
  468. if (board_is_evm_sk()) {
  469. /*
  470. * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
  471. * This is safe enough to do on older revs.
  472. */
  473. gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
  474. gpio_direction_output(GPIO_DDR_VTT_EN, 1);
  475. }
  476. if (board_is_icev2()) {
  477. gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en");
  478. gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1);
  479. }
  480. if (board_is_evm_sk())
  481. config_ddr(303, &ioregs_evmsk, &ddr3_data,
  482. &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
  483. else if (board_is_pb() || board_is_bone_lt())
  484. config_ddr(400, &ioregs_bonelt,
  485. &ddr3_beagleblack_data,
  486. &ddr3_beagleblack_cmd_ctrl_data,
  487. &ddr3_beagleblack_emif_reg_data, 0);
  488. else if (board_is_evm_15_or_later())
  489. config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
  490. &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
  491. else if (board_is_icev2())
  492. config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
  493. &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
  494. 0);
  495. else if (board_is_gp_evm())
  496. config_ddr(266, &ioregs, &ddr2_data,
  497. &ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0);
  498. else
  499. config_ddr(266, &ioregs, &ddr2_data,
  500. &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
  501. }
  502. #endif
  503. #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
  504. (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
  505. static void request_and_set_gpio(int gpio, char *name, int val)
  506. {
  507. int ret;
  508. ret = gpio_request(gpio, name);
  509. if (ret < 0) {
  510. printf("%s: Unable to request %s\n", __func__, name);
  511. return;
  512. }
  513. ret = gpio_direction_output(gpio, 0);
  514. if (ret < 0) {
  515. printf("%s: Unable to set %s as output\n", __func__, name);
  516. goto err_free_gpio;
  517. }
  518. gpio_set_value(gpio, val);
  519. return;
  520. err_free_gpio:
  521. gpio_free(gpio);
  522. }
  523. #define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1);
  524. #define REQUEST_AND_CLR_GPIO(N) request_and_set_gpio(N, #N, 0);
  525. /**
  526. * RMII mode on ICEv2 board needs 50MHz clock. Given the clock
  527. * synthesizer With a capacitor of 18pF, and 25MHz input clock cycle
  528. * PLL1 gives an output of 100MHz. So, configuring the div2/3 as 2 to
  529. * give 50MHz output for Eth0 and 1.
  530. */
  531. static struct clk_synth cdce913_data = {
  532. .id = 0x81,
  533. .capacitor = 0x90,
  534. .mux = 0x6d,
  535. .pdiv2 = 0x2,
  536. .pdiv3 = 0x2,
  537. };
  538. #endif
  539. #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_CONTROL) && \
  540. defined(CONFIG_DM_ETH) && defined(CONFIG_DRIVER_TI_CPSW)
  541. #define MAX_CPSW_SLAVES 2
  542. /* At the moment, we do not want to stop booting for any failures here */
  543. int ft_board_setup(void *fdt, bd_t *bd)
  544. {
  545. const char *slave_path, *enet_name;
  546. int enetnode, slavenode, phynode;
  547. struct udevice *ethdev;
  548. char alias[16];
  549. u32 phy_id[2];
  550. int phy_addr;
  551. int i, ret;
  552. /* phy address fixup needed only on beagle bone family */
  553. if (!board_is_beaglebonex())
  554. goto done;
  555. for (i = 0; i < MAX_CPSW_SLAVES; i++) {
  556. sprintf(alias, "ethernet%d", i);
  557. slave_path = fdt_get_alias(fdt, alias);
  558. if (!slave_path)
  559. continue;
  560. slavenode = fdt_path_offset(fdt, slave_path);
  561. if (slavenode < 0)
  562. continue;
  563. enetnode = fdt_parent_offset(fdt, slavenode);
  564. enet_name = fdt_get_name(fdt, enetnode, NULL);
  565. ethdev = eth_get_dev_by_name(enet_name);
  566. if (!ethdev)
  567. continue;
  568. phy_addr = cpsw_get_slave_phy_addr(ethdev, i);
  569. /* check for phy_id as well as phy-handle properties */
  570. ret = fdtdec_get_int_array_count(fdt, slavenode, "phy_id",
  571. phy_id, 2);
  572. if (ret == 2) {
  573. if (phy_id[1] != phy_addr) {
  574. printf("fixing up phy_id for %s, old: %d, new: %d\n",
  575. alias, phy_id[1], phy_addr);
  576. phy_id[0] = cpu_to_fdt32(phy_id[0]);
  577. phy_id[1] = cpu_to_fdt32(phy_addr);
  578. do_fixup_by_path(fdt, slave_path, "phy_id",
  579. phy_id, sizeof(phy_id), 0);
  580. }
  581. } else {
  582. phynode = fdtdec_lookup_phandle(fdt, slavenode,
  583. "phy-handle");
  584. if (phynode < 0)
  585. continue;
  586. ret = fdtdec_get_int(fdt, phynode, "reg", -ENOENT);
  587. if (ret < 0)
  588. continue;
  589. if (ret != phy_addr) {
  590. printf("fixing up phy-handle for %s, old: %d, new: %d\n",
  591. alias, ret, phy_addr);
  592. fdt_setprop_u32(fdt, phynode, "reg",
  593. cpu_to_fdt32(phy_addr));
  594. }
  595. }
  596. }
  597. done:
  598. return 0;
  599. }
  600. #endif
  601. /*
  602. * Basic board specific setup. Pinmux has been handled already.
  603. */
  604. int board_init(void)
  605. {
  606. #if defined(CONFIG_HW_WATCHDOG)
  607. hw_watchdog_init();
  608. #endif
  609. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  610. #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
  611. gpmc_init();
  612. #endif
  613. #if defined(CONFIG_CLOCK_SYNTHESIZER) && (!defined(CONFIG_SPL_BUILD) || \
  614. (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)))
  615. if (board_is_icev2()) {
  616. int rv;
  617. u32 reg;
  618. REQUEST_AND_SET_GPIO(GPIO_PR1_MII_CTRL);
  619. /* Make J19 status available on GPIO1_26 */
  620. REQUEST_AND_CLR_GPIO(GPIO_MUX_MII_CTRL);
  621. REQUEST_AND_SET_GPIO(GPIO_FET_SWITCH_CTRL);
  622. /*
  623. * Both ports can be set as RMII-CPSW or MII-PRU-ETH using
  624. * jumpers near the port. Read the jumper value and set
  625. * the pinmux, external mux and PHY clock accordingly.
  626. * As jumper line is overridden by PHY RX_DV pin immediately
  627. * after bootstrap (power-up/reset), we need to sample
  628. * it during PHY reset using GPIO rising edge detection.
  629. */
  630. REQUEST_AND_SET_GPIO(GPIO_PHY_RESET);
  631. /* Enable rising edge IRQ on GPIO0_11 and GPIO 1_26 */
  632. reg = readl(GPIO0_RISINGDETECT) | BIT(11);
  633. writel(reg, GPIO0_RISINGDETECT);
  634. reg = readl(GPIO1_RISINGDETECT) | BIT(26);
  635. writel(reg, GPIO1_RISINGDETECT);
  636. /* Reset PHYs to capture the Jumper setting */
  637. gpio_set_value(GPIO_PHY_RESET, 0);
  638. udelay(2); /* PHY datasheet states 1uS min. */
  639. gpio_set_value(GPIO_PHY_RESET, 1);
  640. reg = readl(GPIO0_IRQSTATUSRAW) & BIT(11);
  641. if (reg) {
  642. writel(reg, GPIO0_IRQSTATUS1); /* clear irq */
  643. /* RMII mode */
  644. printf("ETH0, CPSW\n");
  645. } else {
  646. /* MII mode */
  647. printf("ETH0, PRU\n");
  648. cdce913_data.pdiv3 = 4; /* 25MHz PHY clk */
  649. }
  650. reg = readl(GPIO1_IRQSTATUSRAW) & BIT(26);
  651. if (reg) {
  652. writel(reg, GPIO1_IRQSTATUS1); /* clear irq */
  653. /* RMII mode */
  654. printf("ETH1, CPSW\n");
  655. gpio_set_value(GPIO_MUX_MII_CTRL, 1);
  656. } else {
  657. /* MII mode */
  658. printf("ETH1, PRU\n");
  659. cdce913_data.pdiv2 = 4; /* 25MHz PHY clk */
  660. }
  661. /* disable rising edge IRQs */
  662. reg = readl(GPIO0_RISINGDETECT) & ~BIT(11);
  663. writel(reg, GPIO0_RISINGDETECT);
  664. reg = readl(GPIO1_RISINGDETECT) & ~BIT(26);
  665. writel(reg, GPIO1_RISINGDETECT);
  666. rv = setup_clock_synthesizer(&cdce913_data);
  667. if (rv) {
  668. printf("Clock synthesizer setup failed %d\n", rv);
  669. return rv;
  670. }
  671. /* reset PHYs */
  672. gpio_set_value(GPIO_PHY_RESET, 0);
  673. udelay(2); /* PHY datasheet states 1uS min. */
  674. gpio_set_value(GPIO_PHY_RESET, 1);
  675. }
  676. #endif
  677. return 0;
  678. }
  679. #ifdef CONFIG_BOARD_LATE_INIT
  680. int board_late_init(void)
  681. {
  682. struct udevice *dev;
  683. #if !defined(CONFIG_SPL_BUILD)
  684. uint8_t mac_addr[6];
  685. uint32_t mac_hi, mac_lo;
  686. #endif
  687. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  688. char *name = NULL;
  689. if (board_is_bone_lt()) {
  690. /* BeagleBoard.org BeagleBone Black Wireless: */
  691. if (!strncmp(board_ti_get_rev(), "BWA", 3)) {
  692. name = "BBBW";
  693. }
  694. /* SeeedStudio BeagleBone Green Wireless */
  695. if (!strncmp(board_ti_get_rev(), "GW1", 3)) {
  696. name = "BBGW";
  697. }
  698. /* BeagleBoard.org BeagleBone Blue */
  699. if (!strncmp(board_ti_get_rev(), "BLA", 3)) {
  700. name = "BBBL";
  701. }
  702. }
  703. if (board_is_bbg1())
  704. name = "BBG1";
  705. if (board_is_bben())
  706. name = "BBEN";
  707. set_board_info_env(name);
  708. /*
  709. * Default FIT boot on HS devices. Non FIT images are not allowed
  710. * on HS devices.
  711. */
  712. if (get_device_type() == HS_DEVICE)
  713. env_set("boot_fit", "1");
  714. #endif
  715. #if !defined(CONFIG_SPL_BUILD)
  716. /* try reading mac address from efuse */
  717. mac_lo = readl(&cdev->macid0l);
  718. mac_hi = readl(&cdev->macid0h);
  719. mac_addr[0] = mac_hi & 0xFF;
  720. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  721. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  722. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  723. mac_addr[4] = mac_lo & 0xFF;
  724. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  725. if (!env_get("ethaddr")) {
  726. printf("<ethaddr> not set. Validating first E-fuse MAC\n");
  727. if (is_valid_ethaddr(mac_addr))
  728. eth_env_set_enetaddr("ethaddr", mac_addr);
  729. }
  730. mac_lo = readl(&cdev->macid1l);
  731. mac_hi = readl(&cdev->macid1h);
  732. mac_addr[0] = mac_hi & 0xFF;
  733. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  734. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  735. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  736. mac_addr[4] = mac_lo & 0xFF;
  737. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  738. if (!env_get("eth1addr")) {
  739. if (is_valid_ethaddr(mac_addr))
  740. eth_env_set_enetaddr("eth1addr", mac_addr);
  741. }
  742. #endif
  743. if (!env_get("serial#")) {
  744. char *board_serial = env_get("board_serial");
  745. char *ethaddr = env_get("ethaddr");
  746. if (!board_serial || !strncmp(board_serial, "unknown", 7))
  747. env_set("serial#", ethaddr);
  748. else
  749. env_set("serial#", board_serial);
  750. }
  751. /* Just probe the potentially supported cdce913 device */
  752. uclass_get_device(UCLASS_CLK, 0, &dev);
  753. return 0;
  754. }
  755. #endif
  756. /* CPSW platdata */
  757. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  758. struct cpsw_slave_data slave_data[] = {
  759. {
  760. .slave_reg_ofs = CPSW_SLAVE0_OFFSET,
  761. .sliver_reg_ofs = CPSW_SLIVER0_OFFSET,
  762. .phy_addr = 0,
  763. },
  764. {
  765. .slave_reg_ofs = CPSW_SLAVE1_OFFSET,
  766. .sliver_reg_ofs = CPSW_SLIVER1_OFFSET,
  767. .phy_addr = 1,
  768. },
  769. };
  770. struct cpsw_platform_data am335_eth_data = {
  771. .cpsw_base = CPSW_BASE,
  772. .version = CPSW_CTRL_VERSION_2,
  773. .bd_ram_ofs = CPSW_BD_OFFSET,
  774. .ale_reg_ofs = CPSW_ALE_OFFSET,
  775. .cpdma_reg_ofs = CPSW_CPDMA_OFFSET,
  776. .mdio_div = CPSW_MDIO_DIV,
  777. .host_port_reg_ofs = CPSW_HOST_PORT_OFFSET,
  778. .channels = 8,
  779. .slaves = 2,
  780. .slave_data = slave_data,
  781. .ale_entries = 1024,
  782. .bd_ram_ofs = 0x2000,
  783. .mac_control = 0x20,
  784. .active_slave = 0,
  785. .mdio_base = 0x4a101000,
  786. .gmii_sel = 0x44e10650,
  787. .phy_sel_compat = "ti,am3352-cpsw-phy-sel",
  788. .syscon_addr = 0x44e10630,
  789. .macid_sel_compat = "cpsw,am33xx",
  790. };
  791. struct eth_pdata cpsw_pdata = {
  792. .iobase = 0x4a100000,
  793. .phy_interface = 0,
  794. .priv_pdata = &am335_eth_data,
  795. };
  796. U_BOOT_DEVICE(am335x_eth) = {
  797. .name = "eth_cpsw",
  798. .platdata = &cpsw_pdata,
  799. };
  800. #endif
  801. #ifdef CONFIG_SPL_LOAD_FIT
  802. int board_fit_config_name_match(const char *name)
  803. {
  804. if (board_is_gp_evm() && !strcmp(name, "am335x-evm"))
  805. return 0;
  806. else if (board_is_bone() && !strcmp(name, "am335x-bone"))
  807. return 0;
  808. else if (board_is_bone_lt() && !strcmp(name, "am335x-boneblack"))
  809. return 0;
  810. else if (board_is_pb() && !strcmp(name, "am335x-pocketbeagle"))
  811. return 0;
  812. else if (board_is_evm_sk() && !strcmp(name, "am335x-evmsk"))
  813. return 0;
  814. else if (board_is_bbg1() && !strcmp(name, "am335x-bonegreen"))
  815. return 0;
  816. else if (board_is_icev2() && !strcmp(name, "am335x-icev2"))
  817. return 0;
  818. else
  819. return -1;
  820. }
  821. #endif
  822. #ifdef CONFIG_TI_SECURE_DEVICE
  823. void board_fit_image_post_process(void **p_image, size_t *p_size)
  824. {
  825. secure_boot_verify_image(p_image, p_size);
  826. }
  827. #endif
  828. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  829. static const struct omap_hsmmc_plat am335x_mmc0_platdata = {
  830. .base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
  831. .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
  832. .cfg.f_min = 400000,
  833. .cfg.f_max = 52000000,
  834. .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
  835. .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
  836. };
  837. U_BOOT_DEVICE(am335x_mmc0) = {
  838. .name = "omap_hsmmc",
  839. .platdata = &am335x_mmc0_platdata,
  840. };
  841. static const struct omap_hsmmc_plat am335x_mmc1_platdata = {
  842. .base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE,
  843. .cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT,
  844. .cfg.f_min = 400000,
  845. .cfg.f_max = 52000000,
  846. .cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195,
  847. .cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
  848. };
  849. U_BOOT_DEVICE(am335x_mmc1) = {
  850. .name = "omap_hsmmc",
  851. .platdata = &am335x_mmc1_platdata,
  852. };
  853. #endif