board.c 10 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Board functions for TI AM335X based rut board
  4. * (C) Copyright 2013 Siemens Schweiz AG
  5. * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
  6. *
  7. * Based on:
  8. * u-boot:/board/ti/am335x/board.c
  9. *
  10. * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  11. */
  12. #include <common.h>
  13. #include <env.h>
  14. #include <errno.h>
  15. #include <init.h>
  16. #include <malloc.h>
  17. #include <spi.h>
  18. #include <spl.h>
  19. #include <asm/arch/cpu.h>
  20. #include <asm/arch/hardware.h>
  21. #include <asm/arch/omap.h>
  22. #include <asm/arch/ddr_defs.h>
  23. #include <asm/arch/clock.h>
  24. #include <asm/arch/gpio.h>
  25. #include <asm/arch/mmc_host_def.h>
  26. #include <asm/arch/sys_proto.h>
  27. #include <asm/io.h>
  28. #include <asm/emif.h>
  29. #include <asm/gpio.h>
  30. #include <i2c.h>
  31. #include <miiphy.h>
  32. #include <cpsw.h>
  33. #include <video.h>
  34. #include <watchdog.h>
  35. #include "board.h"
  36. #include "../common/factoryset.h"
  37. #include "../../../drivers/video/da8xx-fb.h"
  38. /*
  39. * Read header information from EEPROM into global structure.
  40. */
  41. static int read_eeprom(void)
  42. {
  43. return 0;
  44. }
  45. #ifdef CONFIG_SPL_BUILD
  46. static void board_init_ddr(void)
  47. {
  48. struct emif_regs rut_ddr3_emif_reg_data = {
  49. .sdram_config = 0x61C04AB2,
  50. .sdram_tim1 = 0x0888A39B,
  51. .sdram_tim2 = 0x26337FDA,
  52. .sdram_tim3 = 0x501F830F,
  53. .emif_ddr_phy_ctlr_1 = 0x6,
  54. .zq_config = 0x50074BE4,
  55. .ref_ctrl = 0x93B,
  56. };
  57. struct ddr_data rut_ddr3_data = {
  58. .datardsratio0 = 0x3b,
  59. .datawdsratio0 = 0x85,
  60. .datafwsratio0 = 0x100,
  61. .datawrsratio0 = 0xc1,
  62. };
  63. struct cmd_control rut_ddr3_cmd_ctrl_data = {
  64. .cmd0csratio = 0x40,
  65. .cmd0iclkout = 1,
  66. .cmd1csratio = 0x40,
  67. .cmd1iclkout = 1,
  68. .cmd2csratio = 0x40,
  69. .cmd2iclkout = 1,
  70. };
  71. const struct ctrl_ioregs ioregs = {
  72. .cm0ioctl = RUT_IOCTRL_VAL,
  73. .cm1ioctl = RUT_IOCTRL_VAL,
  74. .cm2ioctl = RUT_IOCTRL_VAL,
  75. .dt0ioctl = RUT_IOCTRL_VAL,
  76. .dt1ioctl = RUT_IOCTRL_VAL,
  77. };
  78. config_ddr(DDR_PLL_FREQ, &ioregs, &rut_ddr3_data,
  79. &rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0);
  80. }
  81. static int request_and_pulse_reset(int gpio, const char *name)
  82. {
  83. int ret;
  84. const int delay_us = 2000; /* 2ms */
  85. ret = gpio_request(gpio, name);
  86. if (ret < 0) {
  87. printf("%s: Unable to request %s\n", __func__, name);
  88. goto err;
  89. }
  90. ret = gpio_direction_output(gpio, 0);
  91. if (ret < 0) {
  92. printf("%s: Unable to set %s as output\n", __func__, name);
  93. goto err_free_gpio;
  94. }
  95. udelay(delay_us);
  96. gpio_set_value(gpio, 1);
  97. return 0;
  98. err_free_gpio:
  99. gpio_free(gpio);
  100. err:
  101. return ret;
  102. }
  103. #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
  104. #define ETH_PHY_RESET_GPIO GPIO_TO_PIN(2, 18)
  105. #define MAXTOUCH_RESET_GPIO GPIO_TO_PIN(3, 18)
  106. #define DISPLAY_RESET_GPIO GPIO_TO_PIN(3, 19)
  107. #define REQUEST_AND_PULSE_RESET(N) \
  108. request_and_pulse_reset(N, #N);
  109. static void spl_siemens_board_init(void)
  110. {
  111. REQUEST_AND_PULSE_RESET(ETH_PHY_RESET_GPIO);
  112. REQUEST_AND_PULSE_RESET(MAXTOUCH_RESET_GPIO);
  113. REQUEST_AND_PULSE_RESET(DISPLAY_RESET_GPIO);
  114. }
  115. #endif /* if def CONFIG_SPL_BUILD */
  116. #if defined(CONFIG_DRIVER_TI_CPSW)
  117. static void cpsw_control(int enabled)
  118. {
  119. /* VTP can be added here */
  120. return;
  121. }
  122. static struct cpsw_slave_data cpsw_slaves[] = {
  123. {
  124. .slave_reg_ofs = 0x208,
  125. .sliver_reg_ofs = 0xd80,
  126. .phy_addr = 1,
  127. .phy_if = PHY_INTERFACE_MODE_RMII,
  128. },
  129. {
  130. .slave_reg_ofs = 0x308,
  131. .sliver_reg_ofs = 0xdc0,
  132. .phy_addr = 0,
  133. .phy_if = PHY_INTERFACE_MODE_RMII,
  134. },
  135. };
  136. static struct cpsw_platform_data cpsw_data = {
  137. .mdio_base = CPSW_MDIO_BASE,
  138. .cpsw_base = CPSW_BASE,
  139. .mdio_div = 0xff,
  140. .channels = 8,
  141. .cpdma_reg_ofs = 0x800,
  142. .slaves = 1,
  143. .slave_data = cpsw_slaves,
  144. .ale_reg_ofs = 0xd00,
  145. .ale_entries = 1024,
  146. .host_port_reg_ofs = 0x108,
  147. .hw_stats_reg_ofs = 0x900,
  148. .bd_ram_ofs = 0x2000,
  149. .mac_control = (1 << 5),
  150. .control = cpsw_control,
  151. .host_port_num = 0,
  152. .version = CPSW_CTRL_VERSION_2,
  153. };
  154. #if defined(CONFIG_DRIVER_TI_CPSW) || \
  155. (defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET))
  156. int board_eth_init(bd_t *bis)
  157. {
  158. struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  159. int n = 0;
  160. int rv;
  161. #ifndef CONFIG_SPL_BUILD
  162. factoryset_env_set();
  163. #endif
  164. /* Set rgmii mode and enable rmii clock to be sourced from chip */
  165. writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
  166. rv = cpsw_register(&cpsw_data);
  167. if (rv < 0)
  168. printf("Error %d registering CPSW switch\n", rv);
  169. else
  170. n += rv;
  171. return n;
  172. }
  173. #endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
  174. #endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
  175. #if defined(CONFIG_HW_WATCHDOG)
  176. static bool hw_watchdog_init_done;
  177. static int hw_watchdog_trigger_level;
  178. void hw_watchdog_reset(void)
  179. {
  180. if (!hw_watchdog_init_done)
  181. return;
  182. hw_watchdog_trigger_level = hw_watchdog_trigger_level ? 0 : 1;
  183. gpio_set_value(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
  184. }
  185. void hw_watchdog_init(void)
  186. {
  187. gpio_request(WATCHDOG_TRIGGER_GPIO, "watchdog_trigger");
  188. gpio_direction_output(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level);
  189. hw_watchdog_reset();
  190. hw_watchdog_init_done = 1;
  191. }
  192. #endif /* defined(CONFIG_HW_WATCHDOG) */
  193. #if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
  194. static struct da8xx_panel lcd_panels[] = {
  195. /* FORMIKE, 4.3", 480x800, KWH043MC17-F01 */
  196. [0] = {
  197. .name = "KWH043MC17-F01",
  198. .width = 480,
  199. .height = 800,
  200. .hfp = 50, /* no spec, "don't care" values */
  201. .hbp = 50,
  202. .hsw = 50,
  203. .vfp = 50,
  204. .vbp = 50,
  205. .vsw = 50,
  206. .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
  207. .invert_pxl_clk = 1,
  208. },
  209. /* FORMIKE, 4.3", 480x800, KWH043ST20-F01 */
  210. [1] = {
  211. .name = "KWH043ST20-F01",
  212. .width = 480,
  213. .height = 800,
  214. .hfp = 50, /* no spec, "don't care" values */
  215. .hbp = 50,
  216. .hsw = 50,
  217. .vfp = 50,
  218. .vbp = 50,
  219. .vsw = 50,
  220. .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
  221. .invert_pxl_clk = 1,
  222. },
  223. /* Multi-Inno, 4.3", 480x800, MI0430VT-1 */
  224. [2] = {
  225. .name = "MI0430VT-1",
  226. .width = 480,
  227. .height = 800,
  228. .hfp = 50, /* no spec, "don't care" values */
  229. .hbp = 50,
  230. .hsw = 50,
  231. .vfp = 50,
  232. .vbp = 50,
  233. .vsw = 50,
  234. .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
  235. .invert_pxl_clk = 1,
  236. },
  237. };
  238. static const struct display_panel disp_panels[] = {
  239. [0] = {
  240. WVGA,
  241. 16, /* RGB 888 */
  242. 16,
  243. COLOR_ACTIVE,
  244. },
  245. [1] = {
  246. WVGA,
  247. 16, /* RGB 888 */
  248. 16,
  249. COLOR_ACTIVE,
  250. },
  251. [2] = {
  252. WVGA,
  253. 24, /* RGB 888 */
  254. 16,
  255. COLOR_ACTIVE,
  256. },
  257. };
  258. static const struct lcd_ctrl_config lcd_cfgs[] = {
  259. [0] = {
  260. &disp_panels[0],
  261. .ac_bias = 255,
  262. .ac_bias_intrpt = 0,
  263. .dma_burst_sz = 16,
  264. .bpp = 16,
  265. .fdd = 0x80,
  266. .tft_alt_mode = 0,
  267. .stn_565_mode = 0,
  268. .mono_8bit_mode = 0,
  269. .invert_line_clock = 1,
  270. .invert_frm_clock = 1,
  271. .sync_edge = 0,
  272. .sync_ctrl = 1,
  273. .raster_order = 0,
  274. },
  275. [1] = {
  276. &disp_panels[1],
  277. .ac_bias = 255,
  278. .ac_bias_intrpt = 0,
  279. .dma_burst_sz = 16,
  280. .bpp = 16,
  281. .fdd = 0x80,
  282. .tft_alt_mode = 0,
  283. .stn_565_mode = 0,
  284. .mono_8bit_mode = 0,
  285. .invert_line_clock = 1,
  286. .invert_frm_clock = 1,
  287. .sync_edge = 0,
  288. .sync_ctrl = 1,
  289. .raster_order = 0,
  290. },
  291. [2] = {
  292. &disp_panels[2],
  293. .ac_bias = 255,
  294. .ac_bias_intrpt = 0,
  295. .dma_burst_sz = 16,
  296. .bpp = 24,
  297. .fdd = 0x80,
  298. .tft_alt_mode = 0,
  299. .stn_565_mode = 0,
  300. .mono_8bit_mode = 0,
  301. .invert_line_clock = 1,
  302. .invert_frm_clock = 1,
  303. .sync_edge = 0,
  304. .sync_ctrl = 1,
  305. .raster_order = 0,
  306. },
  307. };
  308. /* no console on this board */
  309. int board_cfb_skip(void)
  310. {
  311. return 1;
  312. }
  313. #define PLL_GET_M(v) ((v >> 8) & 0x7ff)
  314. #define PLL_GET_N(v) (v & 0x7f)
  315. static struct dpll_regs dpll_lcd_regs = {
  316. .cm_clkmode_dpll = CM_WKUP + 0x98,
  317. .cm_idlest_dpll = CM_WKUP + 0x48,
  318. .cm_clksel_dpll = CM_WKUP + 0x54,
  319. };
  320. static int get_clk(struct dpll_regs *dpll_regs)
  321. {
  322. unsigned int val;
  323. unsigned int m, n;
  324. int f = 0;
  325. val = readl(dpll_regs->cm_clksel_dpll);
  326. m = PLL_GET_M(val);
  327. n = PLL_GET_N(val);
  328. f = (m * V_OSCK) / n;
  329. return f;
  330. };
  331. int clk_get(int clk)
  332. {
  333. return get_clk(&dpll_lcd_regs);
  334. };
  335. static int conf_disp_pll(int m, int n)
  336. {
  337. struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
  338. struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
  339. #if defined(DISPL_PLL_SPREAD_SPECTRUM)
  340. struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
  341. #endif
  342. u32 *const clk_domains[] = {
  343. &cmper->lcdclkctrl,
  344. 0
  345. };
  346. u32 *const clk_modules_explicit_en[] = {
  347. &cmper->lcdclkctrl,
  348. &cmper->lcdcclkstctrl,
  349. &cmper->spi1clkctrl,
  350. 0
  351. };
  352. do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
  353. do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
  354. #if defined(DISPL_PLL_SPREAD_SPECTRUM)
  355. writel(0x64, &cmwkup->resv6[3]); /* 0x50 */
  356. writel(0x800, &cmwkup->resv6[2]); /* 0x4c */
  357. writel(readl(&cmwkup->clkmoddplldisp) | CM_CLKMODE_DPLL_SSC_EN_MASK,
  358. &cmwkup->clkmoddplldisp); /* 0x98 */
  359. #endif
  360. return 0;
  361. }
  362. static int set_gpio(int gpio, int state)
  363. {
  364. gpio_request(gpio, "temp");
  365. gpio_direction_output(gpio, state);
  366. gpio_set_value(gpio, state);
  367. gpio_free(gpio);
  368. return 0;
  369. }
  370. static int enable_lcd(void)
  371. {
  372. unsigned char buf[1];
  373. set_gpio(BOARD_LCD_RESET, 0);
  374. mdelay(1);
  375. set_gpio(BOARD_LCD_RESET, 1);
  376. mdelay(1);
  377. /* spi lcd init */
  378. kwh043st20_f01_spi_startup(1, 0, 5000000, SPI_MODE_0);
  379. /* backlight on */
  380. buf[0] = 0xf;
  381. i2c_write(0x24, 0x7, 1, buf, 1);
  382. buf[0] = 0x3f;
  383. i2c_write(0x24, 0x8, 1, buf, 1);
  384. return 0;
  385. }
  386. int arch_early_init_r(void)
  387. {
  388. enable_lcd();
  389. return 0;
  390. }
  391. static int board_video_init(void)
  392. {
  393. int i;
  394. int anzdisp = ARRAY_SIZE(lcd_panels);
  395. int display = 1;
  396. for (i = 0; i < anzdisp; i++) {
  397. if (strncmp((const char *)factory_dat.disp_name,
  398. lcd_panels[i].name,
  399. strlen((const char *)factory_dat.disp_name)) == 0) {
  400. printf("DISPLAY: %s\n", factory_dat.disp_name);
  401. break;
  402. }
  403. }
  404. if (i == anzdisp) {
  405. i = 1;
  406. printf("%s: %s not found, using default %s\n", __func__,
  407. factory_dat.disp_name, lcd_panels[i].name);
  408. }
  409. conf_disp_pll(24, 1);
  410. da8xx_video_init(&lcd_panels[display], &lcd_cfgs[display],
  411. lcd_cfgs[display].bpp);
  412. return 0;
  413. }
  414. #endif /* ifdef CONFIG_VIDEO */
  415. #ifdef CONFIG_BOARD_LATE_INIT
  416. int board_late_init(void)
  417. {
  418. int ret;
  419. char tmp[2 * MAX_STRING_LENGTH + 2];
  420. omap_nand_switch_ecc(1, 8);
  421. if (factory_dat.asn[0] != 0)
  422. sprintf(tmp, "%s_%s", factory_dat.asn,
  423. factory_dat.comp_version);
  424. else
  425. strcpy(tmp, "QMX7.E38_4.0");
  426. ret = env_set("boardid", tmp);
  427. if (ret)
  428. printf("error setting board id\n");
  429. return 0;
  430. }
  431. #endif
  432. #include "../common/board.c"