itss.c 5.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Interrupt Timer Subsystem
  4. *
  5. * Copyright (C) 2017 Intel Corporation.
  6. * Copyright (C) 2017 Siemens AG
  7. * Copyright 2019 Google LLC
  8. *
  9. * Taken from coreboot itss.c
  10. */
  11. #include <common.h>
  12. #include <dm.h>
  13. #include <dt-structs.h>
  14. #include <irq.h>
  15. #include <malloc.h>
  16. #include <p2sb.h>
  17. #include <spl.h>
  18. #include <asm/itss.h>
  19. struct itss_platdata {
  20. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  21. /* Put this first since driver model will copy the data here */
  22. struct dtd_intel_itss dtplat;
  23. #endif
  24. };
  25. /* struct pmc_route - Routing for PMC to GPIO */
  26. struct pmc_route {
  27. u32 pmc;
  28. u32 gpio;
  29. };
  30. struct itss_priv {
  31. struct pmc_route *route;
  32. uint route_count;
  33. u32 irq_snapshot[NUM_IPC_REGS];
  34. };
  35. static int set_polarity(struct udevice *dev, uint irq, bool active_low)
  36. {
  37. u32 mask;
  38. uint reg;
  39. if (irq > ITSS_MAX_IRQ)
  40. return -EINVAL;
  41. reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * (irq / IRQS_PER_IPC);
  42. mask = 1 << (irq % IRQS_PER_IPC);
  43. pcr_clrsetbits32(dev, reg, mask, active_low ? mask : 0);
  44. return 0;
  45. }
  46. #ifndef CONFIG_TPL_BUILD
  47. static int snapshot_polarities(struct udevice *dev)
  48. {
  49. struct itss_priv *priv = dev_get_priv(dev);
  50. const int start = GPIO_IRQ_START;
  51. const int end = GPIO_IRQ_END;
  52. int reg_start;
  53. int reg_end;
  54. int i;
  55. reg_start = start / IRQS_PER_IPC;
  56. reg_end = (end + IRQS_PER_IPC - 1) / IRQS_PER_IPC;
  57. for (i = reg_start; i < reg_end; i++) {
  58. uint reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i;
  59. priv->irq_snapshot[i] = pcr_read32(dev, reg);
  60. }
  61. return 0;
  62. }
  63. static void show_polarities(struct udevice *dev, const char *msg)
  64. {
  65. int i;
  66. log_info("ITSS IRQ Polarities %s:\n", msg);
  67. for (i = 0; i < NUM_IPC_REGS; i++) {
  68. uint reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i;
  69. log_info("IPC%d: 0x%08x\n", i, pcr_read32(dev, reg));
  70. }
  71. }
  72. static int restore_polarities(struct udevice *dev)
  73. {
  74. struct itss_priv *priv = dev_get_priv(dev);
  75. const int start = GPIO_IRQ_START;
  76. const int end = GPIO_IRQ_END;
  77. int reg_start;
  78. int reg_end;
  79. int i;
  80. show_polarities(dev, "Before");
  81. reg_start = start / IRQS_PER_IPC;
  82. reg_end = (end + IRQS_PER_IPC - 1) / IRQS_PER_IPC;
  83. for (i = reg_start; i < reg_end; i++) {
  84. u32 mask;
  85. u16 reg;
  86. int irq_start;
  87. int irq_end;
  88. irq_start = i * IRQS_PER_IPC;
  89. irq_end = min(irq_start + IRQS_PER_IPC - 1, ITSS_MAX_IRQ);
  90. if (start > irq_end)
  91. continue;
  92. if (end < irq_start)
  93. break;
  94. /* Track bits within the bounds of of the register */
  95. irq_start = max(start, irq_start) % IRQS_PER_IPC;
  96. irq_end = min(end, irq_end) % IRQS_PER_IPC;
  97. /* Create bitmask of the inclusive range of start and end */
  98. mask = (((1U << irq_end) - 1) | (1U << irq_end));
  99. mask &= ~((1U << irq_start) - 1);
  100. reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i;
  101. pcr_clrsetbits32(dev, reg, mask, mask & priv->irq_snapshot[i]);
  102. }
  103. show_polarities(dev, "After");
  104. return 0;
  105. }
  106. #endif
  107. static int route_pmc_gpio_gpe(struct udevice *dev, uint pmc_gpe_num)
  108. {
  109. struct itss_priv *priv = dev_get_priv(dev);
  110. struct pmc_route *route;
  111. int i;
  112. for (i = 0, route = priv->route; i < priv->route_count; i++, route++) {
  113. if (pmc_gpe_num == route->pmc)
  114. return route->gpio;
  115. }
  116. return -ENOENT;
  117. }
  118. static int itss_ofdata_to_platdata(struct udevice *dev)
  119. {
  120. struct itss_priv *priv = dev_get_priv(dev);
  121. int ret;
  122. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  123. struct itss_platdata *plat = dev_get_platdata(dev);
  124. struct dtd_intel_itss *dtplat = &plat->dtplat;
  125. /*
  126. * It would be nice to do this in the bind() method, but with
  127. * of-platdata binding happens in the order that DM finds things in the
  128. * linker list (i.e. alphabetical order by driver name). So the GPIO
  129. * device may well be bound before its parent (p2sb), and this call
  130. * will fail if p2sb is not bound yet.
  131. *
  132. * TODO(sjg@chromium.org): Add a parent pointer to child devices in dtoc
  133. */
  134. ret = p2sb_set_port_id(dev, dtplat->intel_p2sb_port_id);
  135. if (ret)
  136. return log_msg_ret("Could not set port id", ret);
  137. priv->route = (struct pmc_route *)dtplat->intel_pmc_routes;
  138. priv->route_count = ARRAY_SIZE(dtplat->intel_pmc_routes) /
  139. sizeof(struct pmc_route);
  140. #else
  141. int size;
  142. size = dev_read_size(dev, "intel,pmc-routes");
  143. if (size < 0)
  144. return size;
  145. priv->route = malloc(size);
  146. if (!priv->route)
  147. return -ENOMEM;
  148. ret = dev_read_u32_array(dev, "intel,pmc-routes", (u32 *)priv->route,
  149. size / sizeof(fdt32_t));
  150. if (ret)
  151. return log_msg_ret("Cannot read pmc-routes", ret);
  152. priv->route_count = size / sizeof(struct pmc_route);
  153. #endif
  154. return 0;
  155. }
  156. static const struct irq_ops itss_ops = {
  157. .route_pmc_gpio_gpe = route_pmc_gpio_gpe,
  158. .set_polarity = set_polarity,
  159. #ifndef CONFIG_TPL_BUILD
  160. .snapshot_polarities = snapshot_polarities,
  161. .restore_polarities = restore_polarities,
  162. #endif
  163. };
  164. static const struct udevice_id itss_ids[] = {
  165. { .compatible = "intel,itss"},
  166. { }
  167. };
  168. U_BOOT_DRIVER(itss_drv) = {
  169. .name = "intel_itss",
  170. .id = UCLASS_IRQ,
  171. .of_match = itss_ids,
  172. .ops = &itss_ops,
  173. .ofdata_to_platdata = itss_ofdata_to_platdata,
  174. .platdata_auto_alloc_size = sizeof(struct itss_platdata),
  175. .priv_auto_alloc_size = sizeof(struct itss_priv),
  176. };