fsp_s.c 17 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2019 Google LLC
  4. * Written by Simon Glass <sjg@chromium.org>
  5. */
  6. #include <common.h>
  7. #include <acpi_s3.h>
  8. #include <binman.h>
  9. #include <dm.h>
  10. #include <irq.h>
  11. #include <malloc.h>
  12. #include <asm/intel_pinctrl.h>
  13. #include <asm/io.h>
  14. #include <asm/intel_regs.h>
  15. #include <asm/msr.h>
  16. #include <asm/msr-index.h>
  17. #include <asm/pci.h>
  18. #include <asm/arch/cpu.h>
  19. #include <asm/arch/systemagent.h>
  20. #include <asm/arch/fsp/fsp_configs.h>
  21. #include <asm/arch/fsp/fsp_s_upd.h>
  22. #define PCH_P2SB_E0 0xe0
  23. #define HIDE_BIT BIT(0)
  24. #define INTEL_GSPI_MAX 3
  25. #define INTEL_I2C_DEV_MAX 8
  26. #define MAX_USB2_PORTS 8
  27. enum {
  28. CHIPSET_LOCKDOWN_FSP = 0, /* FSP handles locking per UPDs */
  29. CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */
  30. };
  31. enum i2c_speed {
  32. I2C_SPEED_STANDARD = 100000,
  33. I2C_SPEED_FAST = 400000,
  34. I2C_SPEED_FAST_PLUS = 1000000,
  35. I2C_SPEED_HIGH = 3400000,
  36. I2C_SPEED_FAST_ULTRA = 5000000,
  37. };
  38. /*
  39. * Timing values are in units of clock period, with the clock speed
  40. * provided by the SOC
  41. *
  42. * TODO(sjg@chromium.org): Connect this up to the I2C driver
  43. */
  44. struct dw_i2c_speed_config {
  45. enum i2c_speed speed;
  46. /* SCL high and low period count */
  47. u16 scl_lcnt;
  48. u16 scl_hcnt;
  49. /*
  50. * SDA hold time should be 300ns in standard and fast modes
  51. * and long enough for deterministic logic level change in
  52. * fast-plus and high speed modes.
  53. *
  54. * [15:0] SDA TX Hold Time
  55. * [23:16] SDA RX Hold Time
  56. */
  57. u32 sda_hold;
  58. };
  59. /* Serial IRQ control. SERIRQ_QUIET is the default (0) */
  60. enum serirq_mode {
  61. SERIRQ_QUIET,
  62. SERIRQ_CONTINUOUS,
  63. SERIRQ_OFF,
  64. };
  65. /*
  66. * This I2C controller has support for 3 independent speed configs but can
  67. * support both FAST_PLUS and HIGH speeds through the same set of speed
  68. * config registers. These are treated separately so the speed config values
  69. * can be provided via ACPI to the OS.
  70. */
  71. #define DW_I2C_SPEED_CONFIG_COUNT 4
  72. struct dw_i2c_bus_config {
  73. /* Bus should be enabled in TPL with temporary base */
  74. int early_init;
  75. /* Bus speed in Hz, default is I2C_SPEED_FAST (400 KHz) */
  76. enum i2c_speed speed;
  77. /*
  78. * If rise_time_ns is non-zero the calculations for lcnt and hcnt
  79. * registers take into account the times of the bus. However, if
  80. * there is a match in speed_config those register values take
  81. * precedence
  82. */
  83. int rise_time_ns;
  84. int fall_time_ns;
  85. int data_hold_time_ns;
  86. /* Specific bus speed configuration */
  87. struct dw_i2c_speed_config speed_config[DW_I2C_SPEED_CONFIG_COUNT];
  88. };
  89. struct gspi_cfg {
  90. /* Bus speed in MHz */
  91. u32 speed_mhz;
  92. /* Bus should be enabled prior to ramstage with temporary base */
  93. u8 early_init;
  94. };
  95. /*
  96. * This structure will hold data required by common blocks.
  97. * These are soc specific configurations which will be filled by soc.
  98. * We'll fill this structure once during init and use the data in common block.
  99. */
  100. struct soc_intel_common_config {
  101. int chipset_lockdown;
  102. struct gspi_cfg gspi[INTEL_GSPI_MAX];
  103. struct dw_i2c_bus_config i2c[INTEL_I2C_DEV_MAX];
  104. };
  105. enum pnp_settings {
  106. PNP_PERF,
  107. PNP_POWER,
  108. PNP_PERF_POWER,
  109. };
  110. struct usb2_eye_per_port {
  111. u8 per_port_tx_pe_half;
  112. u8 per_port_pe_txi_set;
  113. u8 per_port_txi_set;
  114. u8 hs_skew_sel;
  115. u8 usb_tx_emphasis_en;
  116. u8 per_port_rxi_set;
  117. u8 hs_npre_drv_sel;
  118. u8 override_en;
  119. };
  120. struct apl_config {
  121. /* Common structure containing soc config data required by common code*/
  122. struct soc_intel_common_config common_soc_config;
  123. /*
  124. * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has
  125. * four CLKREQ inputs, but six root ports. Root ports without an
  126. * associated CLKREQ signal must be marked with "CLKREQ_DISABLED"
  127. */
  128. u8 pcie_rp_clkreq_pin[MAX_PCIE_PORTS];
  129. /* Enable/disable hot-plug for root ports (0 = disable, 1 = enable) */
  130. u8 pcie_rp_hotplug_enable[MAX_PCIE_PORTS];
  131. /* De-emphasis enable configuration for each PCIe root port */
  132. u8 pcie_rp_deemphasis_enable[MAX_PCIE_PORTS];
  133. /*
  134. * [14:8] DDR mode Number of dealy elements.Each = 125pSec.
  135. * [6:0] SDR mode Number of dealy elements.Each = 125pSec.
  136. */
  137. u32 emmc_tx_cmd_cntl;
  138. /*
  139. * [14:8] HS400 mode Number of dealy elements.Each = 125pSec.
  140. * [6:0] SDR104/HS200 mode Number of dealy elements.Each = 125pSec.
  141. */
  142. u32 emmc_tx_data_cntl1;
  143. /*
  144. * [30:24] SDR50 mode Number of dealy elements.Each = 125pSec.
  145. * [22:16] DDR50 mode Number of dealy elements.Each = 125pSec.
  146. * [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec.
  147. * [6:0] SDR12/Compatibility mode Number of dealy elements.
  148. * Each = 125pSec.
  149. */
  150. u32 emmc_tx_data_cntl2;
  151. /*
  152. * [30:24] SDR50 mode Number of dealy elements.Each = 125pSec.
  153. * [22:16] DDR50 mode Number of dealy elements.Each = 125pSec.
  154. * [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec.
  155. * [6:0] SDR12/Compatibility mode Number of dealy elements.
  156. * Each = 125pSec.
  157. */
  158. u32 emmc_rx_cmd_data_cntl1;
  159. /*
  160. * [14:8] HS400 mode 1 Number of dealy elements.Each = 125pSec.
  161. * [6:0] HS400 mode 2 Number of dealy elements.Each = 125pSec.
  162. */
  163. u32 emmc_rx_strobe_cntl;
  164. /*
  165. * [13:8] Auto Tuning mode Number of dealy elements.Each = 125pSec.
  166. * [6:0] SDR104/HS200 Number of dealy elements.Each = 125pSec.
  167. */
  168. u32 emmc_rx_cmd_data_cntl2;
  169. /* Select the eMMC max speed allowed */
  170. u32 emmc_host_max_speed;
  171. /* Specifies on which IRQ the SCI will internally appear */
  172. u32 sci_irq;
  173. /* Configure serial IRQ (SERIRQ) line */
  174. enum serirq_mode serirq_mode;
  175. /* Configure LPSS S0ix Enable */
  176. bool lpss_s0ix_enable;
  177. /* Enable DPTF support */
  178. bool dptf_enable;
  179. /* TCC activation offset value in degrees Celsius */
  180. int tcc_offset;
  181. /*
  182. * Configure Audio clk gate and power gate
  183. * IOSF-SB port ID 92 offset 0x530 [5] and [3]
  184. */
  185. bool hdaudio_clk_gate_enable;
  186. bool hdaudio_pwr_gate_enable;
  187. bool hdaudio_bios_config_lockdown;
  188. /* SLP S3 minimum assertion width */
  189. int slp_s3_assertion_width_usecs;
  190. /* GPIO pin for PERST_0 */
  191. u32 prt0_gpio;
  192. /* USB2 eye diagram settings per port */
  193. struct usb2_eye_per_port usb2eye[MAX_USB2_PORTS];
  194. /* GPIO SD card detect pin */
  195. unsigned int sdcard_cd_gpio;
  196. /*
  197. * PRMRR size setting with three options
  198. * 0x02000000 - 32MiB
  199. * 0x04000000 - 64MiB
  200. * 0x08000000 - 128MiB
  201. */
  202. u32 PrmrrSize;
  203. /*
  204. * Enable SGX feature.
  205. * Enabling SGX feature is 2 step process,
  206. * (1) set sgx_enable = 1
  207. * (2) set PrmrrSize to supported size
  208. */
  209. bool sgx_enable;
  210. /*
  211. * Select PNP Settings.
  212. * (0) Performance,
  213. * (1) Power
  214. * (2) Power & Performance
  215. */
  216. enum pnp_settings pnp_settings;
  217. /*
  218. * PMIC PCH_PWROK delay configuration - IPC Configuration
  219. * Upd for changing PCH_PWROK delay configuration : I2C_Slave_Address
  220. * (31:24) + Register_Offset (23:16) + OR Value (15:8) + AND Value (7:0)
  221. */
  222. u32 pmic_pmc_ipc_ctrl;
  223. /*
  224. * Options to disable XHCI Link Compliance Mode. Default is FALSE to not
  225. * disable Compliance Mode. Set TRUE to disable Compliance Mode.
  226. * 0:FALSE(Default), 1:True.
  227. */
  228. bool disable_compliance_mode;
  229. /*
  230. * Options to change USB3 ModPhy setting for the Integrated Filter (IF)
  231. * value. Default is 0 to not changing default IF value (0x12). Set
  232. * value with the range from 0x01 to 0xff to change IF value.
  233. */
  234. u32 mod_phy_if_value;
  235. /*
  236. * Options to bump USB3 LDO voltage. Default is FALSE to not increasing
  237. * LDO voltage. Set TRUE to increase LDO voltage with 40mV.
  238. * 0:FALSE (default), 1:True.
  239. */
  240. bool mod_phy_voltage_bump;
  241. /*
  242. * Options to adjust PMIC Vdd2 voltage. Default is 0 to not adjusting
  243. * the PMIC Vdd2 default voltage 1.20v. Upd for changing Vdd2 Voltage
  244. * configuration: I2C_Slave_Address (31:23) + Register_Offset (23:16)
  245. * + OR Value (15:8) + AND Value (7:0) through BUCK5_VID[3:2]:
  246. * 00=1.10v, 01=1.15v, 10=1.24v, 11=1.20v (default).
  247. */
  248. u32 pmic_vdd2_voltage;
  249. /* Option to enable VTD feature */
  250. bool enable_vtd;
  251. };
  252. static int get_config(struct udevice *dev, struct apl_config *apl)
  253. {
  254. const u8 *ptr;
  255. ofnode node;
  256. u32 emmc[4];
  257. int ret;
  258. memset(apl, '\0', sizeof(*apl));
  259. node = dev_read_subnode(dev, "fsp-s");
  260. if (!ofnode_valid(node))
  261. return log_msg_ret("fsp-s settings", -ENOENT);
  262. ptr = ofnode_read_u8_array_ptr(node, "pcie-rp-clkreq-pin",
  263. MAX_PCIE_PORTS);
  264. if (!ptr)
  265. return log_msg_ret("pcie-rp-clkreq-pin", -EINVAL);
  266. memcpy(apl->pcie_rp_clkreq_pin, ptr, MAX_PCIE_PORTS);
  267. ret = ofnode_read_u32(node, "prt0-gpio", &apl->prt0_gpio);
  268. if (ret)
  269. return log_msg_ret("prt0-gpio", ret);
  270. ret = ofnode_read_u32(node, "sdcard-cd-gpio", &apl->sdcard_cd_gpio);
  271. if (ret)
  272. return log_msg_ret("sdcard-cd-gpio", ret);
  273. ret = ofnode_read_u32_array(node, "emmc", emmc, ARRAY_SIZE(emmc));
  274. if (ret)
  275. return log_msg_ret("emmc", ret);
  276. apl->emmc_tx_data_cntl1 = emmc[0];
  277. apl->emmc_tx_data_cntl2 = emmc[1];
  278. apl->emmc_rx_cmd_data_cntl1 = emmc[2];
  279. apl->emmc_rx_cmd_data_cntl2 = emmc[3];
  280. apl->dptf_enable = ofnode_read_bool(node, "dptf-enable");
  281. apl->hdaudio_clk_gate_enable = ofnode_read_bool(node,
  282. "hdaudio-clk-gate-enable");
  283. apl->hdaudio_pwr_gate_enable = ofnode_read_bool(node,
  284. "hdaudio-pwr-gate-enable");
  285. apl->hdaudio_bios_config_lockdown = ofnode_read_bool(node,
  286. "hdaudio-bios-config-lockdown");
  287. apl->lpss_s0ix_enable = ofnode_read_bool(node, "lpss-s0ix-enable");
  288. /* Santa */
  289. apl->usb2eye[1].per_port_pe_txi_set = 7;
  290. apl->usb2eye[1].per_port_txi_set = 2;
  291. return 0;
  292. }
  293. static void apl_fsp_silicon_init_params_cb(struct apl_config *apl,
  294. struct fsp_s_config *cfg)
  295. {
  296. u8 port;
  297. for (port = 0; port < MAX_USB2_PORTS; port++) {
  298. if (apl->usb2eye[port].per_port_tx_pe_half)
  299. cfg->port_usb20_per_port_tx_pe_half[port] =
  300. apl->usb2eye[port].per_port_tx_pe_half;
  301. if (apl->usb2eye[port].per_port_pe_txi_set)
  302. cfg->port_usb20_per_port_pe_txi_set[port] =
  303. apl->usb2eye[port].per_port_pe_txi_set;
  304. if (apl->usb2eye[port].per_port_txi_set)
  305. cfg->port_usb20_per_port_txi_set[port] =
  306. apl->usb2eye[port].per_port_txi_set;
  307. if (apl->usb2eye[port].hs_skew_sel)
  308. cfg->port_usb20_hs_skew_sel[port] =
  309. apl->usb2eye[port].hs_skew_sel;
  310. if (apl->usb2eye[port].usb_tx_emphasis_en)
  311. cfg->port_usb20_i_usb_tx_emphasis_en[port] =
  312. apl->usb2eye[port].usb_tx_emphasis_en;
  313. if (apl->usb2eye[port].per_port_rxi_set)
  314. cfg->port_usb20_per_port_rxi_set[port] =
  315. apl->usb2eye[port].per_port_rxi_set;
  316. if (apl->usb2eye[port].hs_npre_drv_sel)
  317. cfg->port_usb20_hs_npre_drv_sel[port] =
  318. apl->usb2eye[port].hs_npre_drv_sel;
  319. }
  320. }
  321. int fsps_update_config(struct udevice *dev, ulong rom_offset,
  322. struct fsps_upd *upd)
  323. {
  324. struct fsp_s_config *cfg = &upd->config;
  325. struct apl_config *apl;
  326. struct binman_entry vbt;
  327. void *buf;
  328. int ret;
  329. ret = binman_entry_find("intel-vbt", &vbt);
  330. if (ret)
  331. return log_msg_ret("Cannot find VBT", ret);
  332. vbt.image_pos += rom_offset;
  333. buf = malloc(vbt.size);
  334. if (!buf)
  335. return log_msg_ret("Alloc VBT", -ENOMEM);
  336. /*
  337. * Load VBT before devicetree-specific config. This only supports
  338. * memory-mapped SPI at present.
  339. */
  340. bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
  341. memcpy(buf, (void *)vbt.image_pos, vbt.size);
  342. bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
  343. if (*(u32 *)buf != VBT_SIGNATURE)
  344. return log_msg_ret("VBT signature", -EINVAL);
  345. cfg->graphics_config_ptr = (ulong)buf;
  346. apl = malloc(sizeof(*apl));
  347. if (!apl)
  348. return log_msg_ret("config", -ENOMEM);
  349. get_config(dev, apl);
  350. cfg->ish_enable = 0;
  351. cfg->enable_sata = 0;
  352. cfg->pcie_root_port_en[2] = 0;
  353. cfg->pcie_rp_hot_plug[2] = 0;
  354. cfg->pcie_root_port_en[3] = 0;
  355. cfg->pcie_rp_hot_plug[3] = 0;
  356. cfg->pcie_root_port_en[4] = 0;
  357. cfg->pcie_rp_hot_plug[4] = 0;
  358. cfg->pcie_root_port_en[5] = 0;
  359. cfg->pcie_rp_hot_plug[5] = 0;
  360. cfg->pcie_root_port_en[1] = 0;
  361. cfg->pcie_rp_hot_plug[1] = 0;
  362. cfg->usb_otg = 0;
  363. cfg->i2c6_enable = 0;
  364. cfg->i2c7_enable = 0;
  365. cfg->hsuart3_enable = 0;
  366. cfg->spi1_enable = 0;
  367. cfg->spi2_enable = 0;
  368. cfg->sdio_enabled = 0;
  369. memcpy(cfg->pcie_rp_clk_req_number, apl->pcie_rp_clkreq_pin,
  370. sizeof(cfg->pcie_rp_clk_req_number));
  371. memcpy(cfg->pcie_rp_hot_plug, apl->pcie_rp_hotplug_enable,
  372. sizeof(cfg->pcie_rp_hot_plug));
  373. switch (apl->serirq_mode) {
  374. case SERIRQ_QUIET:
  375. cfg->sirq_enable = 1;
  376. cfg->sirq_mode = 0;
  377. break;
  378. case SERIRQ_CONTINUOUS:
  379. cfg->sirq_enable = 1;
  380. cfg->sirq_mode = 1;
  381. break;
  382. case SERIRQ_OFF:
  383. default:
  384. cfg->sirq_enable = 0;
  385. break;
  386. }
  387. if (apl->emmc_tx_cmd_cntl)
  388. cfg->emmc_tx_cmd_cntl = apl->emmc_tx_cmd_cntl;
  389. if (apl->emmc_tx_data_cntl1)
  390. cfg->emmc_tx_data_cntl1 = apl->emmc_tx_data_cntl1;
  391. if (apl->emmc_tx_data_cntl2)
  392. cfg->emmc_tx_data_cntl2 = apl->emmc_tx_data_cntl2;
  393. if (apl->emmc_rx_cmd_data_cntl1)
  394. cfg->emmc_rx_cmd_data_cntl1 = apl->emmc_rx_cmd_data_cntl1;
  395. if (apl->emmc_rx_strobe_cntl)
  396. cfg->emmc_rx_strobe_cntl = apl->emmc_rx_strobe_cntl;
  397. if (apl->emmc_rx_cmd_data_cntl2)
  398. cfg->emmc_rx_cmd_data_cntl2 = apl->emmc_rx_cmd_data_cntl2;
  399. if (apl->emmc_host_max_speed)
  400. cfg->e_mmc_host_max_speed = apl->emmc_host_max_speed;
  401. cfg->lpss_s0ix_enable = apl->lpss_s0ix_enable;
  402. cfg->skip_mp_init = true;
  403. /* Disable setting of EISS bit in FSP */
  404. cfg->spi_eiss = 0;
  405. /* Disable FSP from locking access to the RTC NVRAM */
  406. cfg->rtc_lock = 0;
  407. /* Enable Audio clk gate and power gate */
  408. cfg->hd_audio_clk_gate = apl->hdaudio_clk_gate_enable;
  409. cfg->hd_audio_pwr_gate = apl->hdaudio_pwr_gate_enable;
  410. /* Bios config lockdown Audio clk and power gate */
  411. cfg->bios_cfg_lock_down = apl->hdaudio_bios_config_lockdown;
  412. apl_fsp_silicon_init_params_cb(apl, cfg);
  413. cfg->usb_otg = true;
  414. cfg->vtd_enable = apl->enable_vtd;
  415. return 0;
  416. }
  417. static void p2sb_set_hide_bit(pci_dev_t dev, int hide)
  418. {
  419. pci_x86_clrset_config(dev, PCH_P2SB_E0 + 1, HIDE_BIT,
  420. hide ? HIDE_BIT : 0, PCI_SIZE_8);
  421. }
  422. /* Configure package power limits */
  423. static int set_power_limits(struct udevice *dev)
  424. {
  425. msr_t rapl_msr_reg, limit;
  426. u32 power_unit;
  427. u32 tdp, min_power, max_power;
  428. u32 pl2_val;
  429. u32 override_tdp[2];
  430. int ret;
  431. /* Get units */
  432. rapl_msr_reg = msr_read(MSR_PKG_POWER_SKU_UNIT);
  433. power_unit = 1 << (rapl_msr_reg.lo & 0xf);
  434. /* Get power defaults for this SKU */
  435. rapl_msr_reg = msr_read(MSR_PKG_POWER_SKU);
  436. tdp = rapl_msr_reg.lo & PKG_POWER_LIMIT_MASK;
  437. pl2_val = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK;
  438. min_power = (rapl_msr_reg.lo >> 16) & PKG_POWER_LIMIT_MASK;
  439. max_power = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK;
  440. if (min_power > 0 && tdp < min_power)
  441. tdp = min_power;
  442. if (max_power > 0 && tdp > max_power)
  443. tdp = max_power;
  444. ret = dev_read_u32_array(dev, "tdp-pl-override-mw", override_tdp,
  445. ARRAY_SIZE(override_tdp));
  446. if (ret)
  447. return log_msg_ret("tdp-pl-override-mw", ret);
  448. /* Set PL1 override value */
  449. if (override_tdp[0])
  450. tdp = override_tdp[0] * power_unit / 1000;
  451. /* Set PL2 override value */
  452. if (override_tdp[1])
  453. pl2_val = override_tdp[1] * power_unit / 1000;
  454. /* Set long term power limit to TDP */
  455. limit.lo = tdp & PKG_POWER_LIMIT_MASK;
  456. /* Set PL1 Pkg Power clamp bit */
  457. limit.lo |= PKG_POWER_LIMIT_CLAMP;
  458. limit.lo |= PKG_POWER_LIMIT_EN;
  459. limit.lo |= (MB_POWER_LIMIT1_TIME_DEFAULT &
  460. PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT;
  461. /* Set short term power limit PL2 */
  462. limit.hi = pl2_val & PKG_POWER_LIMIT_MASK;
  463. limit.hi |= PKG_POWER_LIMIT_EN;
  464. /* Program package power limits in RAPL MSR */
  465. msr_write(MSR_PKG_POWER_LIMIT, limit);
  466. log_info("RAPL PL1 %d.%dW\n", tdp / power_unit,
  467. 100 * (tdp % power_unit) / power_unit);
  468. log_info("RAPL PL2 %d.%dW\n", pl2_val / power_unit,
  469. 100 * (pl2_val % power_unit) / power_unit);
  470. /*
  471. * Sett RAPL MMIO register for Power limits. RAPL driver is using MSR
  472. * instead of MMIO, so disable LIMIT_EN bit for MMIO
  473. */
  474. writel(limit.lo & ~PKG_POWER_LIMIT_EN, MCHBAR_REG(MCHBAR_RAPL_PPL));
  475. writel(limit.hi & ~PKG_POWER_LIMIT_EN, MCHBAR_REG(MCHBAR_RAPL_PPL + 4));
  476. return 0;
  477. }
  478. int p2sb_unhide(void)
  479. {
  480. pci_dev_t dev = PCI_BDF(0, 0xd, 0);
  481. ulong val;
  482. p2sb_set_hide_bit(dev, 0);
  483. pci_x86_read_config(dev, PCI_VENDOR_ID, &val, PCI_SIZE_16);
  484. if (val != PCI_VENDOR_ID_INTEL)
  485. return log_msg_ret("p2sb unhide", -EIO);
  486. return 0;
  487. }
  488. /* Overwrites the SCI IRQ if another IRQ number is given by device tree */
  489. static void set_sci_irq(void)
  490. {
  491. /* Skip this for now */
  492. }
  493. int arch_fsps_preinit(void)
  494. {
  495. struct udevice *itss;
  496. int ret;
  497. ret = uclass_first_device_err(UCLASS_IRQ, &itss);
  498. if (ret)
  499. return log_msg_ret("no itss", ret);
  500. /*
  501. * Snapshot the current GPIO IRQ polarities. FSP is setting a default
  502. * policy that doesn't honour boards' requirements
  503. */
  504. irq_snapshot_polarities(itss);
  505. /*
  506. * Clear the GPI interrupt status and enable registers. These
  507. * registers do not get reset to default state when booting from S5.
  508. */
  509. ret = pinctrl_gpi_clear_int_cfg();
  510. if (ret)
  511. return log_msg_ret("gpi_clear", ret);
  512. return 0;
  513. }
  514. int arch_fsp_init_r(void)
  515. {
  516. #ifdef CONFIG_HAVE_ACPI_RESUME
  517. bool s3wake = gd->arch.prev_sleep_state == ACPI_S3;
  518. #else
  519. bool s3wake = false;
  520. #endif
  521. struct udevice *dev, *itss;
  522. int ret;
  523. /*
  524. * This must be called before any devices are probed. Put any probing
  525. * into arch_fsps_preinit() above.
  526. *
  527. * We don't use CONFIG_APL_BOOT_FROM_FAST_SPI_FLASH here since it will
  528. * force PCI to be probed.
  529. */
  530. ret = fsp_silicon_init(s3wake, false);
  531. if (ret)
  532. return ret;
  533. ret = uclass_first_device_err(UCLASS_IRQ, &itss);
  534. if (ret)
  535. return log_msg_ret("no itss", ret);
  536. /* Restore GPIO IRQ polarities back to previous settings */
  537. irq_restore_polarities(itss);
  538. /* soc_init() */
  539. ret = p2sb_unhide();
  540. if (ret)
  541. return log_msg_ret("unhide p2sb", ret);
  542. /* Set RAPL MSR for Package power limits*/
  543. ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev);
  544. if (ret)
  545. return log_msg_ret("Cannot get northbridge", ret);
  546. set_power_limits(dev);
  547. /*
  548. * FSP-S routes SCI to IRQ 9. With the help of this function you can
  549. * select another IRQ for SCI.
  550. */
  551. set_sci_irq();
  552. return 0;
  553. }