spl.c 2.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /* Copyright 2013 Freescale Semiconductor, Inc.
  3. */
  4. #include <common.h>
  5. #include <clock_legacy.h>
  6. #include <console.h>
  7. #include <env.h>
  8. #include <env_internal.h>
  9. #include <init.h>
  10. #include <ns16550.h>
  11. #include <malloc.h>
  12. #include <mmc.h>
  13. #include <nand.h>
  14. #include <i2c.h>
  15. #include <fsl_esdhc.h>
  16. #include <spi_flash.h>
  17. #include "../common/spl.h"
  18. DECLARE_GLOBAL_DATA_PTR;
  19. phys_size_t get_effective_memsize(void)
  20. {
  21. return CONFIG_SYS_L2_SIZE;
  22. }
  23. void board_init_f(ulong bootflag)
  24. {
  25. u32 plat_ratio;
  26. ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  27. struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
  28. console_init_f();
  29. /* Clock configuration to access CPLD using IFC(GPCM) */
  30. setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
  31. #ifdef CONFIG_TARGET_P1010RDB_PB
  32. setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS);
  33. #endif
  34. /* initialize selected port with appropriate baud rate */
  35. plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
  36. plat_ratio >>= 1;
  37. gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
  38. NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
  39. gd->bus_clk / 16 / CONFIG_BAUDRATE);
  40. #ifdef CONFIG_SPL_MMC_BOOT
  41. puts("\nSD boot...\n");
  42. #elif defined(CONFIG_SPL_SPI_BOOT)
  43. puts("\nSPI Flash boot...\n");
  44. #endif
  45. /* copy code to RAM and jump to it - this should not return */
  46. /* NOTE - code has to be copied out of NAND buffer before
  47. * other blocks can be read.
  48. */
  49. relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
  50. }
  51. void board_init_r(gd_t *gd, ulong dest_addr)
  52. {
  53. /* Pointer is writable since we allocated a register for it */
  54. gd = (gd_t *)CONFIG_SPL_GD_ADDR;
  55. struct bd_info *bd;
  56. memset(gd, 0, sizeof(gd_t));
  57. bd = (struct bd_info *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
  58. memset(bd, 0, sizeof(struct bd_info));
  59. gd->bd = bd;
  60. arch_cpu_init();
  61. get_clocks();
  62. mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
  63. CONFIG_SPL_RELOC_MALLOC_SIZE);
  64. gd->flags |= GD_FLG_FULL_MALLOC_INIT;
  65. #ifndef CONFIG_SPL_NAND_BOOT
  66. env_init();
  67. #endif
  68. #ifdef CONFIG_SPL_MMC_BOOT
  69. mmc_initialize(bd);
  70. #endif
  71. /* relocate environment function pointers etc. */
  72. #ifdef CONFIG_SPL_NAND_BOOT
  73. nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
  74. (uchar *)SPL_ENV_ADDR);
  75. gd->env_addr = (ulong)(SPL_ENV_ADDR);
  76. gd->env_valid = ENV_VALID;
  77. #else
  78. env_relocate();
  79. #endif
  80. i2c_init_all();
  81. dram_init();
  82. #ifdef CONFIG_SPL_NAND_BOOT
  83. puts("\nTertiary program loader running in sram...");
  84. #else
  85. puts("\nSecond program loader running in sram...");
  86. #endif
  87. #ifdef CONFIG_SPL_MMC_BOOT
  88. mmc_boot();
  89. #elif defined(CONFIG_SPL_SPI_BOOT)
  90. fsl_spi_boot();
  91. #elif defined(CONFIG_SPL_NAND_BOOT)
  92. nand_boot();
  93. #endif
  94. }