b4860qds.c 31 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2011-2012 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <command.h>
  7. #include <env.h>
  8. #include <fdt_support.h>
  9. #include <i2c.h>
  10. #include <image.h>
  11. #include <init.h>
  12. #include <irq_func.h>
  13. #include <log.h>
  14. #include <netdev.h>
  15. #include <linux/compiler.h>
  16. #include <asm/mmu.h>
  17. #include <asm/processor.h>
  18. #include <linux/delay.h>
  19. #include <linux/errno.h>
  20. #include <asm/cache.h>
  21. #include <asm/immap_85xx.h>
  22. #include <asm/fsl_law.h>
  23. #include <asm/fsl_serdes.h>
  24. #include <asm/fsl_liodn.h>
  25. #include <fm_eth.h>
  26. #include <hwconfig.h>
  27. #include "../common/qixis.h"
  28. #include "../common/vsc3316_3308.h"
  29. #include "../common/idt8t49n222a_serdes_clk.h"
  30. #include "../common/zm7300.h"
  31. #include "b4860qds.h"
  32. #include "b4860qds_qixis.h"
  33. #include "b4860qds_crossbar_con.h"
  34. #define CLK_MUX_SEL_MASK 0x4
  35. #define ETH_PHY_CLK_OUT 0x4
  36. DECLARE_GLOBAL_DATA_PTR;
  37. int checkboard(void)
  38. {
  39. char buf[64];
  40. u8 sw;
  41. struct cpu_type *cpu = gd->arch.cpu;
  42. static const char *const freq[] = {"100", "125", "156.25", "161.13",
  43. "122.88", "122.88", "122.88"};
  44. int clock;
  45. printf("Board: %sQDS, ", cpu->name);
  46. printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
  47. QIXIS_READ(id), QIXIS_READ(arch));
  48. sw = QIXIS_READ(brdcfg[0]);
  49. sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  50. if (sw < 0x8)
  51. printf("vBank: %d\n", sw);
  52. else if (sw >= 0x8 && sw <= 0xE)
  53. puts("NAND\n");
  54. else
  55. printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  56. printf("FPGA: v%d (%s), build %d",
  57. (int)QIXIS_READ(scver), qixis_read_tag(buf),
  58. (int)qixis_read_minor());
  59. /* the timestamp string contains "\n" at the end */
  60. printf(" on %s", qixis_read_time(buf));
  61. /*
  62. * Display the actual SERDES reference clocks as configured by the
  63. * dip switches on the board. Note that the SWx registers could
  64. * technically be set to force the reference clocks to match the
  65. * values that the SERDES expects (or vice versa). For now, however,
  66. * we just display both values and hope the user notices when they
  67. * don't match.
  68. */
  69. puts("SERDES Reference Clocks: ");
  70. sw = QIXIS_READ(brdcfg[2]);
  71. clock = (sw >> 5) & 7;
  72. printf("Bank1=%sMHz ", freq[clock]);
  73. sw = QIXIS_READ(brdcfg[4]);
  74. clock = (sw >> 6) & 3;
  75. printf("Bank2=%sMHz\n", freq[clock]);
  76. return 0;
  77. }
  78. int select_i2c_ch_pca(u8 ch)
  79. {
  80. int ret;
  81. /* Selecting proper channel via PCA*/
  82. ret = i2c_write(I2C_MUX_PCA_ADDR, 0x0, 1, &ch, 1);
  83. if (ret) {
  84. printf("PCA: failed to select proper channel.\n");
  85. return ret;
  86. }
  87. return 0;
  88. }
  89. /*
  90. * read_voltage from sensor on I2C bus
  91. * We use average of 4 readings, waiting for 532us befor another reading
  92. */
  93. #define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */
  94. #define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */
  95. static inline int read_voltage(void)
  96. {
  97. int i, ret, voltage_read = 0;
  98. u16 vol_mon;
  99. for (i = 0; i < NUM_READINGS; i++) {
  100. ret = i2c_read(I2C_VOL_MONITOR_ADDR,
  101. I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
  102. if (ret) {
  103. printf("VID: failed to read core voltage\n");
  104. return ret;
  105. }
  106. if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
  107. printf("VID: Core voltage sensor error\n");
  108. return -1;
  109. }
  110. debug("VID: bus voltage reads 0x%04x\n", vol_mon);
  111. /* LSB = 4mv */
  112. voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
  113. udelay(WAIT_FOR_ADC);
  114. }
  115. /* calculate the average */
  116. voltage_read /= NUM_READINGS;
  117. return voltage_read;
  118. }
  119. static int adjust_vdd(ulong vdd_override)
  120. {
  121. int re_enable = disable_interrupts();
  122. ccsr_gur_t __iomem *gur =
  123. (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  124. u32 fusesr;
  125. u8 vid;
  126. int vdd_target, vdd_last;
  127. int existing_voltage, temp_voltage, voltage; /* all in 1/10 mV */
  128. int ret;
  129. unsigned int orig_i2c_speed;
  130. unsigned long vdd_string_override;
  131. char *vdd_string;
  132. static const uint16_t vdd[32] = {
  133. 0, /* unused */
  134. 9875, /* 0.9875V */
  135. 9750,
  136. 9625,
  137. 9500,
  138. 9375,
  139. 9250,
  140. 9125,
  141. 9000,
  142. 8875,
  143. 8750,
  144. 8625,
  145. 8500,
  146. 8375,
  147. 8250,
  148. 8125,
  149. 10000, /* 1.0000V */
  150. 10125,
  151. 10250,
  152. 10375,
  153. 10500,
  154. 10625,
  155. 10750,
  156. 10875,
  157. 11000,
  158. 0, /* reserved */
  159. };
  160. struct vdd_drive {
  161. u8 vid;
  162. unsigned voltage;
  163. };
  164. ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR);
  165. if (ret) {
  166. printf("VID: I2c failed to switch channel\n");
  167. ret = -1;
  168. goto exit;
  169. }
  170. /* get the voltage ID from fuse status register */
  171. fusesr = in_be32(&gur->dcfg_fusesr);
  172. vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
  173. FSL_CORENET_DCFG_FUSESR_VID_MASK;
  174. if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
  175. vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
  176. FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
  177. }
  178. vdd_target = vdd[vid];
  179. debug("VID:Reading from from fuse,vid=%x vdd is %dmV\n",
  180. vid, vdd_target/10);
  181. /* check override variable for overriding VDD */
  182. vdd_string = env_get("b4qds_vdd_mv");
  183. if (vdd_override == 0 && vdd_string &&
  184. !strict_strtoul(vdd_string, 10, &vdd_string_override))
  185. vdd_override = vdd_string_override;
  186. if (vdd_override >= 819 && vdd_override <= 1212) {
  187. vdd_target = vdd_override * 10; /* convert to 1/10 mV */
  188. debug("VDD override is %lu\n", vdd_override);
  189. } else if (vdd_override != 0) {
  190. printf("Invalid value.\n");
  191. }
  192. if (vdd_target == 0) {
  193. printf("VID: VID not used\n");
  194. ret = 0;
  195. goto exit;
  196. }
  197. /*
  198. * Read voltage monitor to check real voltage.
  199. * Voltage monitor LSB is 4mv.
  200. */
  201. vdd_last = read_voltage();
  202. if (vdd_last < 0) {
  203. printf("VID: abort VID adjustment\n");
  204. ret = -1;
  205. goto exit;
  206. }
  207. debug("VID: Core voltage is at %d mV\n", vdd_last);
  208. ret = select_i2c_ch_pca(I2C_MUX_CH_DPM);
  209. if (ret) {
  210. printf("VID: I2c failed to switch channel to DPM\n");
  211. ret = -1;
  212. goto exit;
  213. }
  214. /* Round up to the value of step of Voltage regulator */
  215. voltage = roundup(vdd_target, ZM_STEP);
  216. debug("VID: rounded up voltage = %d\n", voltage);
  217. /* lower the speed to 100kHz to access ZM7300 device */
  218. debug("VID: Setting bus speed to 100KHz if not already set\n");
  219. orig_i2c_speed = i2c_get_bus_speed();
  220. if (orig_i2c_speed != 100000)
  221. i2c_set_bus_speed(100000);
  222. /* Read the existing level on board, if equal to requsted one,
  223. no need to re-set */
  224. existing_voltage = zm_read_voltage();
  225. /* allowing the voltage difference of one step 0.0125V acceptable */
  226. if ((existing_voltage >= voltage) &&
  227. (existing_voltage < (voltage + ZM_STEP))) {
  228. debug("VID: voltage already set as requested,returning\n");
  229. ret = existing_voltage;
  230. goto out;
  231. }
  232. debug("VID: Changing voltage for board from %dmV to %dmV\n",
  233. existing_voltage/10, voltage/10);
  234. if (zm_disable_wp() < 0) {
  235. ret = -1;
  236. goto out;
  237. }
  238. /* Change Voltage: the change is done through all the steps in the
  239. way, to avoid reset to the board due to power good signal fail
  240. in big voltage change gap jump.
  241. */
  242. if (existing_voltage > voltage) {
  243. temp_voltage = existing_voltage - ZM_STEP;
  244. while (temp_voltage >= voltage) {
  245. ret = zm_write_voltage(temp_voltage);
  246. if (ret == temp_voltage) {
  247. temp_voltage -= ZM_STEP;
  248. } else {
  249. /* ZM7300 device failed to set
  250. * the voltage */
  251. printf
  252. ("VID:Stepping down vol failed:%dmV\n",
  253. temp_voltage/10);
  254. ret = -1;
  255. goto out;
  256. }
  257. }
  258. } else {
  259. temp_voltage = existing_voltage + ZM_STEP;
  260. while (temp_voltage < (voltage + ZM_STEP)) {
  261. ret = zm_write_voltage(temp_voltage);
  262. if (ret == temp_voltage) {
  263. temp_voltage += ZM_STEP;
  264. } else {
  265. /* ZM7300 device failed to set
  266. * the voltage */
  267. printf
  268. ("VID:Stepping up vol failed:%dmV\n",
  269. temp_voltage/10);
  270. ret = -1;
  271. goto out;
  272. }
  273. }
  274. }
  275. if (zm_enable_wp() < 0)
  276. ret = -1;
  277. /* restore the speed to 400kHz */
  278. out: debug("VID: Restore the I2C bus speed to %dKHz\n",
  279. orig_i2c_speed/1000);
  280. i2c_set_bus_speed(orig_i2c_speed);
  281. if (ret < 0)
  282. goto exit;
  283. ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR);
  284. if (ret) {
  285. printf("VID: I2c failed to switch channel\n");
  286. ret = -1;
  287. goto exit;
  288. }
  289. vdd_last = read_voltage();
  290. select_i2c_ch_pca(I2C_CH_DEFAULT);
  291. if (vdd_last > 0)
  292. printf("VID: Core voltage %d mV\n", vdd_last);
  293. else
  294. ret = -1;
  295. exit:
  296. if (re_enable)
  297. enable_interrupts();
  298. return ret;
  299. }
  300. int configure_vsc3316_3308(void)
  301. {
  302. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  303. unsigned int num_vsc16_con, num_vsc08_con;
  304. u32 serdes1_prtcl, serdes2_prtcl;
  305. int ret;
  306. char buffer[HWCONFIG_BUFFER_SIZE];
  307. char *buf = NULL;
  308. serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
  309. FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  310. if (!serdes1_prtcl) {
  311. printf("SERDES1 is not enabled\n");
  312. return 0;
  313. }
  314. serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  315. debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
  316. serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
  317. FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
  318. if (!serdes2_prtcl) {
  319. printf("SERDES2 is not enabled\n");
  320. return 0;
  321. }
  322. serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
  323. debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
  324. switch (serdes1_prtcl) {
  325. case 0x29:
  326. case 0x2a:
  327. case 0x2C:
  328. case 0x2D:
  329. case 0x2E:
  330. /*
  331. * Configuration:
  332. * SERDES: 1
  333. * Lanes: A,B: SGMII
  334. * Lanes: C,D,E,F,G,H: CPRI
  335. */
  336. debug("Configuring crossbar to use onboard SGMII PHYs:"
  337. "srds_prctl:%x\n", serdes1_prtcl);
  338. num_vsc16_con = NUM_CON_VSC3316;
  339. /* Configure VSC3316 crossbar switch */
  340. ret = select_i2c_ch_pca(I2C_CH_VSC3316);
  341. if (!ret) {
  342. ret = vsc3316_config(VSC3316_TX_ADDRESS,
  343. vsc16_tx_4sfp_sgmii_12_56,
  344. num_vsc16_con);
  345. if (ret)
  346. return ret;
  347. ret = vsc3316_config(VSC3316_RX_ADDRESS,
  348. vsc16_rx_4sfp_sgmii_12_56,
  349. num_vsc16_con);
  350. if (ret)
  351. return ret;
  352. } else {
  353. return ret;
  354. }
  355. break;
  356. case 0x01:
  357. case 0x02:
  358. case 0x04:
  359. case 0x05:
  360. case 0x06:
  361. case 0x07:
  362. case 0x08:
  363. case 0x09:
  364. case 0x0A:
  365. case 0x0B:
  366. case 0x0C:
  367. case 0x2F:
  368. case 0x30:
  369. case 0x32:
  370. case 0x33:
  371. case 0x34:
  372. case 0x39:
  373. case 0x3A:
  374. case 0x3C:
  375. case 0x3D:
  376. case 0x5C:
  377. case 0x5D:
  378. /*
  379. * Configuration:
  380. * SERDES: 1
  381. * Lanes: A,B: AURORA
  382. * Lanes: C,d: SGMII
  383. * Lanes: E,F,G,H: CPRI
  384. */
  385. debug("Configuring crossbar for Aurora, SGMII 3 and 4,"
  386. " and CPRI. srds_prctl:%x\n", serdes1_prtcl);
  387. num_vsc16_con = NUM_CON_VSC3316;
  388. /* Configure VSC3316 crossbar switch */
  389. ret = select_i2c_ch_pca(I2C_CH_VSC3316);
  390. if (!ret) {
  391. ret = vsc3316_config(VSC3316_TX_ADDRESS,
  392. vsc16_tx_sfp_sgmii_aurora,
  393. num_vsc16_con);
  394. if (ret)
  395. return ret;
  396. ret = vsc3316_config(VSC3316_RX_ADDRESS,
  397. vsc16_rx_sfp_sgmii_aurora,
  398. num_vsc16_con);
  399. if (ret)
  400. return ret;
  401. } else {
  402. return ret;
  403. }
  404. break;
  405. #ifdef CONFIG_ARCH_B4420
  406. case 0x17:
  407. case 0x18:
  408. /*
  409. * Configuration:
  410. * SERDES: 1
  411. * Lanes: A,B,C,D: SGMII
  412. * Lanes: E,F,G,H: CPRI
  413. */
  414. debug("Configuring crossbar to use onboard SGMII PHYs:"
  415. "srds_prctl:%x\n", serdes1_prtcl);
  416. num_vsc16_con = NUM_CON_VSC3316;
  417. /* Configure VSC3316 crossbar switch */
  418. ret = select_i2c_ch_pca(I2C_CH_VSC3316);
  419. if (!ret) {
  420. ret = vsc3316_config(VSC3316_TX_ADDRESS,
  421. vsc16_tx_sgmii_lane_cd, num_vsc16_con);
  422. if (ret)
  423. return ret;
  424. ret = vsc3316_config(VSC3316_RX_ADDRESS,
  425. vsc16_rx_sgmii_lane_cd, num_vsc16_con);
  426. if (ret)
  427. return ret;
  428. } else {
  429. return ret;
  430. }
  431. break;
  432. #endif
  433. case 0x3E:
  434. case 0x0D:
  435. case 0x0E:
  436. case 0x12:
  437. num_vsc16_con = NUM_CON_VSC3316;
  438. /* Configure VSC3316 crossbar switch */
  439. ret = select_i2c_ch_pca(I2C_CH_VSC3316);
  440. if (!ret) {
  441. ret = vsc3316_config(VSC3316_TX_ADDRESS,
  442. vsc16_tx_sfp, num_vsc16_con);
  443. if (ret)
  444. return ret;
  445. ret = vsc3316_config(VSC3316_RX_ADDRESS,
  446. vsc16_rx_sfp, num_vsc16_con);
  447. if (ret)
  448. return ret;
  449. } else {
  450. return ret;
  451. }
  452. break;
  453. default:
  454. printf("WARNING:VSC crossbars programming not supported for:%x"
  455. " SerDes1 Protocol.\n", serdes1_prtcl);
  456. return -1;
  457. }
  458. num_vsc08_con = NUM_CON_VSC3308;
  459. /* Configure VSC3308 crossbar switch */
  460. ret = select_i2c_ch_pca(I2C_CH_VSC3308);
  461. switch (serdes2_prtcl) {
  462. #ifdef CONFIG_ARCH_B4420
  463. case 0x9d:
  464. #endif
  465. case 0x9E:
  466. case 0x9A:
  467. case 0x98:
  468. case 0x48:
  469. case 0x49:
  470. case 0x4E:
  471. case 0x79:
  472. case 0x7A:
  473. if (!ret) {
  474. ret = vsc3308_config(VSC3308_TX_ADDRESS,
  475. vsc08_tx_amc, num_vsc08_con);
  476. if (ret)
  477. return ret;
  478. ret = vsc3308_config(VSC3308_RX_ADDRESS,
  479. vsc08_rx_amc, num_vsc08_con);
  480. if (ret)
  481. return ret;
  482. } else {
  483. return ret;
  484. }
  485. break;
  486. case 0x80:
  487. case 0x81:
  488. case 0x82:
  489. case 0x83:
  490. case 0x84:
  491. case 0x85:
  492. case 0x86:
  493. case 0x87:
  494. case 0x88:
  495. case 0x89:
  496. case 0x8a:
  497. case 0x8b:
  498. case 0x8c:
  499. case 0x8d:
  500. case 0x8e:
  501. case 0xb1:
  502. case 0xb2:
  503. if (!ret) {
  504. /*
  505. * Extract hwconfig from environment since environment
  506. * is not setup properly yet
  507. */
  508. env_get_f("hwconfig", buffer, sizeof(buffer));
  509. buf = buffer;
  510. if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2",
  511. "sfp_amc", "sfp", buf)) {
  512. #ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR
  513. /* change default VSC3308 for XFI erratum */
  514. ret = vsc3308_config_adjust(VSC3308_TX_ADDRESS,
  515. vsc08_tx_sfp, num_vsc08_con);
  516. if (ret)
  517. return ret;
  518. ret = vsc3308_config_adjust(VSC3308_RX_ADDRESS,
  519. vsc08_rx_sfp, num_vsc08_con);
  520. if (ret)
  521. return ret;
  522. #else
  523. ret = vsc3308_config(VSC3308_TX_ADDRESS,
  524. vsc08_tx_sfp, num_vsc08_con);
  525. if (ret)
  526. return ret;
  527. ret = vsc3308_config(VSC3308_RX_ADDRESS,
  528. vsc08_rx_sfp, num_vsc08_con);
  529. if (ret)
  530. return ret;
  531. #endif
  532. } else {
  533. ret = vsc3308_config(VSC3308_TX_ADDRESS,
  534. vsc08_tx_amc, num_vsc08_con);
  535. if (ret)
  536. return ret;
  537. ret = vsc3308_config(VSC3308_RX_ADDRESS,
  538. vsc08_rx_amc, num_vsc08_con);
  539. if (ret)
  540. return ret;
  541. }
  542. } else {
  543. return ret;
  544. }
  545. break;
  546. default:
  547. printf("WARNING:VSC crossbars programming not supported for: %x"
  548. " SerDes2 Protocol.\n", serdes2_prtcl);
  549. return -1;
  550. }
  551. return 0;
  552. }
  553. static int calibrate_pll(serdes_corenet_t *srds_regs, int pll_num)
  554. {
  555. u32 rst_err;
  556. /* Steps For SerDes PLLs reset and reconfiguration
  557. * or PLL power-up procedure
  558. */
  559. debug("CALIBRATE PLL:%d\n", pll_num);
  560. clrbits_be32(&srds_regs->bank[pll_num].rstctl,
  561. SRDS_RSTCTL_SDRST_B);
  562. udelay(10);
  563. clrbits_be32(&srds_regs->bank[pll_num].rstctl,
  564. (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
  565. udelay(10);
  566. setbits_be32(&srds_regs->bank[pll_num].rstctl,
  567. SRDS_RSTCTL_RST);
  568. setbits_be32(&srds_regs->bank[pll_num].rstctl,
  569. (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
  570. | SRDS_RSTCTL_SDRST_B));
  571. udelay(20);
  572. /* Check whether PLL has been locked or not */
  573. rst_err = in_be32(&srds_regs->bank[pll_num].rstctl) &
  574. SRDS_RSTCTL_RSTERR;
  575. rst_err >>= SRDS_RSTCTL_RSTERR_SHIFT;
  576. debug("RST_ERR value for PLL %d is: 0x%x:\n", pll_num, rst_err);
  577. if (rst_err)
  578. return rst_err;
  579. return rst_err;
  580. }
  581. static int check_pll_locks(serdes_corenet_t *srds_regs, int pll_num)
  582. {
  583. int ret = 0;
  584. u32 fcap, dcbias, bcap, pllcr1, pllcr0;
  585. if (calibrate_pll(srds_regs, pll_num)) {
  586. /* STEP 1 */
  587. /* Read fcap, dcbias and bcap value */
  588. clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
  589. SRDS_PLLCR0_DCBIAS_OUT_EN);
  590. fcap = in_be32(&srds_regs->bank[pll_num].pllsr2) &
  591. SRDS_PLLSR2_FCAP;
  592. fcap >>= SRDS_PLLSR2_FCAP_SHIFT;
  593. bcap = in_be32(&srds_regs->bank[pll_num].pllsr2) &
  594. SRDS_PLLSR2_BCAP_EN;
  595. bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT;
  596. setbits_be32(&srds_regs->bank[pll_num].pllcr0,
  597. SRDS_PLLCR0_DCBIAS_OUT_EN);
  598. dcbias = in_be32(&srds_regs->bank[pll_num].pllsr2) &
  599. SRDS_PLLSR2_DCBIAS;
  600. dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT;
  601. debug("values of bcap:%x, fcap:%x and dcbias:%x\n",
  602. bcap, fcap, dcbias);
  603. if (fcap == 0 && bcap == 1) {
  604. /* Step 3 */
  605. clrbits_be32(&srds_regs->bank[pll_num].rstctl,
  606. (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
  607. | SRDS_RSTCTL_SDRST_B));
  608. clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
  609. SRDS_PLLCR1_BCAP_EN);
  610. setbits_be32(&srds_regs->bank[pll_num].pllcr1,
  611. SRDS_PLLCR1_BCAP_OVD);
  612. if (calibrate_pll(srds_regs, pll_num)) {
  613. /*save the fcap, dcbias and bcap values*/
  614. clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
  615. SRDS_PLLCR0_DCBIAS_OUT_EN);
  616. fcap = in_be32(&srds_regs->bank[pll_num].pllsr2)
  617. & SRDS_PLLSR2_FCAP;
  618. fcap >>= SRDS_PLLSR2_FCAP_SHIFT;
  619. bcap = in_be32(&srds_regs->bank[pll_num].pllsr2)
  620. & SRDS_PLLSR2_BCAP_EN;
  621. bcap >>= SRDS_PLLSR2_BCAP_EN_SHIFT;
  622. setbits_be32(&srds_regs->bank[pll_num].pllcr0,
  623. SRDS_PLLCR0_DCBIAS_OUT_EN);
  624. dcbias = in_be32
  625. (&srds_regs->bank[pll_num].pllsr2) &
  626. SRDS_PLLSR2_DCBIAS;
  627. dcbias >>= SRDS_PLLSR2_DCBIAS_SHIFT;
  628. /* Step 4*/
  629. clrbits_be32(&srds_regs->bank[pll_num].rstctl,
  630. (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
  631. | SRDS_RSTCTL_SDRST_B));
  632. setbits_be32(&srds_regs->bank[pll_num].pllcr1,
  633. SRDS_PLLCR1_BYP_CAL);
  634. clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
  635. SRDS_PLLCR1_BCAP_EN);
  636. setbits_be32(&srds_regs->bank[pll_num].pllcr1,
  637. SRDS_PLLCR1_BCAP_OVD);
  638. /* change the fcap and dcbias to the saved
  639. * values from Step 3 */
  640. clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
  641. SRDS_PLLCR1_PLL_FCAP);
  642. pllcr1 = (in_be32
  643. (&srds_regs->bank[pll_num].pllcr1)|
  644. (fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT));
  645. out_be32(&srds_regs->bank[pll_num].pllcr1,
  646. pllcr1);
  647. clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
  648. SRDS_PLLCR0_DCBIAS_OVRD);
  649. pllcr0 = (in_be32
  650. (&srds_regs->bank[pll_num].pllcr0)|
  651. (dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT));
  652. out_be32(&srds_regs->bank[pll_num].pllcr0,
  653. pllcr0);
  654. ret = calibrate_pll(srds_regs, pll_num);
  655. if (ret)
  656. return ret;
  657. } else {
  658. goto out;
  659. }
  660. } else { /* Step 5 */
  661. clrbits_be32(&srds_regs->bank[pll_num].rstctl,
  662. (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
  663. | SRDS_RSTCTL_SDRST_B));
  664. udelay(10);
  665. /* Change the fcap, dcbias, and bcap to the
  666. * values from Step 1 */
  667. setbits_be32(&srds_regs->bank[pll_num].pllcr1,
  668. SRDS_PLLCR1_BYP_CAL);
  669. clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
  670. SRDS_PLLCR1_PLL_FCAP);
  671. pllcr1 = (in_be32(&srds_regs->bank[pll_num].pllcr1)|
  672. (fcap << SRDS_PLLCR1_PLL_FCAP_SHIFT));
  673. out_be32(&srds_regs->bank[pll_num].pllcr1,
  674. pllcr1);
  675. clrbits_be32(&srds_regs->bank[pll_num].pllcr0,
  676. SRDS_PLLCR0_DCBIAS_OVRD);
  677. pllcr0 = (in_be32(&srds_regs->bank[pll_num].pllcr0)|
  678. (dcbias << SRDS_PLLCR0_DCBIAS_OVRD_SHIFT));
  679. out_be32(&srds_regs->bank[pll_num].pllcr0,
  680. pllcr0);
  681. clrbits_be32(&srds_regs->bank[pll_num].pllcr1,
  682. SRDS_PLLCR1_BCAP_EN);
  683. setbits_be32(&srds_regs->bank[pll_num].pllcr1,
  684. SRDS_PLLCR1_BCAP_OVD);
  685. ret = calibrate_pll(srds_regs, pll_num);
  686. if (ret)
  687. return ret;
  688. }
  689. }
  690. out:
  691. return 0;
  692. }
  693. static int check_serdes_pll_locks(void)
  694. {
  695. serdes_corenet_t *srds1_regs =
  696. (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  697. serdes_corenet_t *srds2_regs =
  698. (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
  699. int i, ret1, ret2;
  700. debug("\nSerDes1 Lock check\n");
  701. for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
  702. ret1 = check_pll_locks(srds1_regs, i);
  703. if (ret1) {
  704. printf("SerDes1, PLL:%d didnt lock\n", i);
  705. return ret1;
  706. }
  707. }
  708. debug("\nSerDes2 Lock check\n");
  709. for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
  710. ret2 = check_pll_locks(srds2_regs, i);
  711. if (ret2) {
  712. printf("SerDes2, PLL:%d didnt lock\n", i);
  713. return ret2;
  714. }
  715. }
  716. return 0;
  717. }
  718. int config_serdes1_refclks(void)
  719. {
  720. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  721. serdes_corenet_t *srds_regs =
  722. (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  723. u32 serdes1_prtcl, lane;
  724. unsigned int flag_sgmii_aurora_prtcl = 0;
  725. int i;
  726. int ret = 0;
  727. serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
  728. FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  729. if (!serdes1_prtcl) {
  730. printf("SERDES1 is not enabled\n");
  731. return -1;
  732. }
  733. serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  734. debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
  735. /* To prevent generation of reset request from SerDes
  736. * while changing the refclks, By setting SRDS_RST_MSK bit,
  737. * SerDes reset event cannot cause a reset request
  738. */
  739. setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
  740. /* Reconfigure IDT idt8t49n222a device for CPRI to work
  741. * For this SerDes1's Refclk1 and refclk2 need to be set
  742. * to 122.88MHz
  743. */
  744. switch (serdes1_prtcl) {
  745. case 0x29:
  746. case 0x2A:
  747. case 0x2C:
  748. case 0x2D:
  749. case 0x2E:
  750. case 0x01:
  751. case 0x02:
  752. case 0x04:
  753. case 0x05:
  754. case 0x06:
  755. case 0x07:
  756. case 0x08:
  757. case 0x09:
  758. case 0x0A:
  759. case 0x0B:
  760. case 0x0C:
  761. case 0x2F:
  762. case 0x30:
  763. case 0x32:
  764. case 0x33:
  765. case 0x34:
  766. case 0x39:
  767. case 0x3A:
  768. case 0x3C:
  769. case 0x3D:
  770. case 0x5C:
  771. case 0x5D:
  772. debug("Configuring idt8t49n222a for CPRI SerDes clks:"
  773. " for srds_prctl:%x\n", serdes1_prtcl);
  774. ret = select_i2c_ch_pca(I2C_CH_IDT);
  775. if (!ret) {
  776. ret = set_serdes_refclk(IDT_SERDES1_ADDRESS, 1,
  777. SERDES_REFCLK_122_88,
  778. SERDES_REFCLK_122_88, 0);
  779. if (ret) {
  780. printf("IDT8T49N222A configuration failed.\n");
  781. goto out;
  782. } else
  783. debug("IDT8T49N222A configured.\n");
  784. } else {
  785. goto out;
  786. }
  787. select_i2c_ch_pca(I2C_CH_DEFAULT);
  788. /* Change SerDes1's Refclk1 to 125MHz for on board
  789. * SGMIIs or Aurora to work
  790. */
  791. for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
  792. enum srds_prtcl lane_prtcl = serdes_get_prtcl
  793. (0, serdes1_prtcl, lane);
  794. switch (lane_prtcl) {
  795. case SGMII_FM1_DTSEC1:
  796. case SGMII_FM1_DTSEC2:
  797. case SGMII_FM1_DTSEC3:
  798. case SGMII_FM1_DTSEC4:
  799. case SGMII_FM1_DTSEC5:
  800. case SGMII_FM1_DTSEC6:
  801. case AURORA:
  802. flag_sgmii_aurora_prtcl++;
  803. break;
  804. default:
  805. break;
  806. }
  807. }
  808. if (flag_sgmii_aurora_prtcl)
  809. QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
  810. /* Steps For SerDes PLLs reset and reconfiguration after
  811. * changing SerDes's refclks
  812. */
  813. for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
  814. debug("For PLL%d reset and reconfiguration after"
  815. " changing refclks\n", i+1);
  816. clrbits_be32(&srds_regs->bank[i].rstctl,
  817. SRDS_RSTCTL_SDRST_B);
  818. udelay(10);
  819. clrbits_be32(&srds_regs->bank[i].rstctl,
  820. (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
  821. udelay(10);
  822. setbits_be32(&srds_regs->bank[i].rstctl,
  823. SRDS_RSTCTL_RST);
  824. setbits_be32(&srds_regs->bank[i].rstctl,
  825. (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
  826. | SRDS_RSTCTL_SDRST_B));
  827. }
  828. break;
  829. default:
  830. printf("WARNING:IDT8T49N222A configuration not"
  831. " supported for:%x SerDes1 Protocol.\n",
  832. serdes1_prtcl);
  833. }
  834. out:
  835. /* Clearing SRDS_RST_MSK bit as now
  836. * SerDes reset event can cause a reset request
  837. */
  838. clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
  839. return ret;
  840. }
  841. int config_serdes2_refclks(void)
  842. {
  843. ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  844. serdes_corenet_t *srds2_regs =
  845. (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
  846. u32 serdes2_prtcl;
  847. int ret = 0;
  848. int i;
  849. serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
  850. FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
  851. if (!serdes2_prtcl) {
  852. debug("SERDES2 is not enabled\n");
  853. return -ENODEV;
  854. }
  855. serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
  856. debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
  857. /* To prevent generation of reset request from SerDes
  858. * while changing the refclks, By setting SRDS_RST_MSK bit,
  859. * SerDes reset event cannot cause a reset request
  860. */
  861. setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
  862. /* Reconfigure IDT idt8t49n222a device for PCIe SATA to work
  863. * For this SerDes2's Refclk1 need to be set to 100MHz
  864. */
  865. switch (serdes2_prtcl) {
  866. #ifdef CONFIG_ARCH_B4420
  867. case 0x9d:
  868. #endif
  869. case 0x9E:
  870. case 0x9A:
  871. /* fallthrough */
  872. case 0xb1:
  873. case 0xb2:
  874. debug("Configuring IDT for PCIe SATA for srds_prctl:%x\n",
  875. serdes2_prtcl);
  876. ret = select_i2c_ch_pca(I2C_CH_IDT);
  877. if (!ret) {
  878. ret = set_serdes_refclk(IDT_SERDES2_ADDRESS, 2,
  879. SERDES_REFCLK_100,
  880. SERDES_REFCLK_156_25, 0);
  881. if (ret) {
  882. printf("IDT8T49N222A configuration failed.\n");
  883. goto out;
  884. } else
  885. debug("IDT8T49N222A configured.\n");
  886. } else {
  887. goto out;
  888. }
  889. select_i2c_ch_pca(I2C_CH_DEFAULT);
  890. /* Steps For SerDes PLLs reset and reconfiguration after
  891. * changing SerDes's refclks
  892. */
  893. for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
  894. clrbits_be32(&srds2_regs->bank[i].rstctl,
  895. SRDS_RSTCTL_SDRST_B);
  896. udelay(10);
  897. clrbits_be32(&srds2_regs->bank[i].rstctl,
  898. (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B));
  899. udelay(10);
  900. setbits_be32(&srds2_regs->bank[i].rstctl,
  901. SRDS_RSTCTL_RST);
  902. setbits_be32(&srds2_regs->bank[i].rstctl,
  903. (SRDS_RSTCTL_SDEN | SRDS_RSTCTL_PLLRST_B
  904. | SRDS_RSTCTL_SDRST_B));
  905. udelay(10);
  906. }
  907. break;
  908. default:
  909. printf("IDT configuration not supported for:%x S2 Protocol.\n",
  910. serdes2_prtcl);
  911. }
  912. out:
  913. /* Clearing SRDS_RST_MSK bit as now
  914. * SerDes reset event can cause a reset request
  915. */
  916. clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
  917. return ret;
  918. }
  919. int board_early_init_r(void)
  920. {
  921. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  922. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  923. int ret;
  924. u32 svr = SVR_SOC_VER(get_svr());
  925. /* Create law for MAPLE only for personalities having MAPLE */
  926. if ((svr == SVR_B4860) || (svr == SVR_B4440) ||
  927. (svr == SVR_B4420) || (svr == SVR_B4220)) {
  928. set_next_law(CONFIG_SYS_MAPLE_MEM_PHYS, LAW_SIZE_16M,
  929. LAW_TRGT_IF_MAPLE);
  930. }
  931. /*
  932. * Remap Boot flash + PROMJET region to caching-inhibited
  933. * so that flash can be erased properly.
  934. */
  935. /* Flush d-cache and invalidate i-cache of any FLASH data */
  936. flush_dcache();
  937. invalidate_icache();
  938. if (flash_esel == -1) {
  939. /* very unlikely unless something is messed up */
  940. puts("Error: Could not find TLB for FLASH BASE\n");
  941. flash_esel = 2; /* give our best effort to continue */
  942. } else {
  943. /* invalidate existing TLB entry for flash + promjet */
  944. disable_tlb(flash_esel);
  945. }
  946. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  947. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  948. 0, flash_esel, BOOKE_PAGESZ_256M, 1);
  949. /*
  950. * Adjust core voltage according to voltage ID
  951. * This function changes I2C mux to channel 2.
  952. */
  953. if (adjust_vdd(0) < 0)
  954. printf("Warning: Adjusting core voltage failed\n");
  955. /* SerDes1 refclks need to be set again, as default clks
  956. * are not suitable for CPRI and onboard SGMIIs to work
  957. * simultaneously.
  958. * This function will set SerDes1's Refclk1 and refclk2
  959. * as per SerDes1 protocols
  960. */
  961. if (config_serdes1_refclks())
  962. printf("SerDes1 Refclks couldn't set properly.\n");
  963. else
  964. printf("SerDes1 Refclks have been set.\n");
  965. /* SerDes2 refclks need to be set again, as default clks
  966. * are not suitable for PCIe SATA to work
  967. * This function will set SerDes2's Refclk1 and refclk2
  968. * for SerDes2 protocols having PCIe in them
  969. * for PCIe SATA to work
  970. */
  971. ret = config_serdes2_refclks();
  972. if (!ret)
  973. printf("SerDes2 Refclks have been set.\n");
  974. else if (ret == -ENODEV)
  975. printf("SerDes disable, Refclks couldn't change.\n");
  976. else
  977. printf("SerDes2 Refclk reconfiguring failed.\n");
  978. #if defined(CONFIG_SYS_FSL_ERRATUM_A006384) || \
  979. defined(CONFIG_SYS_FSL_ERRATUM_A006475)
  980. /* Rechecking the SerDes locks after all SerDes configurations
  981. * are done, As SerDes PLLs may not lock reliably at 5 G VCO
  982. * and at cold temperatures.
  983. * Following sequence ensure the proper locking of SerDes PLLs.
  984. */
  985. if (SVR_MAJ(get_svr()) == 1) {
  986. if (check_serdes_pll_locks())
  987. printf("SerDes plls still not locked properly.\n");
  988. else
  989. printf("SerDes plls have been locked well.\n");
  990. }
  991. #endif
  992. /* Configure VSC3316 and VSC3308 crossbar switches */
  993. if (configure_vsc3316_3308())
  994. printf("VSC:failed to configure VSC3316/3308.\n");
  995. else
  996. printf("VSC:VSC3316/3308 successfully configured.\n");
  997. select_i2c_ch_pca(I2C_CH_DEFAULT);
  998. return 0;
  999. }
  1000. unsigned long get_board_sys_clk(void)
  1001. {
  1002. u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
  1003. switch ((sysclk_conf & 0x0C) >> 2) {
  1004. case QIXIS_CLK_100:
  1005. return 100000000;
  1006. case QIXIS_CLK_125:
  1007. return 125000000;
  1008. case QIXIS_CLK_133:
  1009. return 133333333;
  1010. }
  1011. return 66666666;
  1012. }
  1013. unsigned long get_board_ddr_clk(void)
  1014. {
  1015. u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
  1016. switch (ddrclk_conf & 0x03) {
  1017. case QIXIS_CLK_100:
  1018. return 100000000;
  1019. case QIXIS_CLK_125:
  1020. return 125000000;
  1021. case QIXIS_CLK_133:
  1022. return 133333333;
  1023. }
  1024. return 66666666;
  1025. }
  1026. static int serdes_refclock(u8 sw, u8 sdclk)
  1027. {
  1028. unsigned int clock;
  1029. int ret = -1;
  1030. u8 brdcfg4;
  1031. if (sdclk == 1) {
  1032. brdcfg4 = QIXIS_READ(brdcfg[4]);
  1033. if ((brdcfg4 & CLK_MUX_SEL_MASK) == ETH_PHY_CLK_OUT)
  1034. return SRDS_PLLCR0_RFCK_SEL_125;
  1035. else
  1036. clock = (sw >> 5) & 7;
  1037. } else
  1038. clock = (sw >> 6) & 3;
  1039. switch (clock) {
  1040. case 0:
  1041. ret = SRDS_PLLCR0_RFCK_SEL_100;
  1042. break;
  1043. case 1:
  1044. ret = SRDS_PLLCR0_RFCK_SEL_125;
  1045. break;
  1046. case 2:
  1047. ret = SRDS_PLLCR0_RFCK_SEL_156_25;
  1048. break;
  1049. case 3:
  1050. ret = SRDS_PLLCR0_RFCK_SEL_161_13;
  1051. break;
  1052. case 4:
  1053. case 5:
  1054. case 6:
  1055. ret = SRDS_PLLCR0_RFCK_SEL_122_88;
  1056. break;
  1057. default:
  1058. ret = -1;
  1059. break;
  1060. }
  1061. return ret;
  1062. }
  1063. #define NUM_SRDS_BANKS 2
  1064. int misc_init_r(void)
  1065. {
  1066. u8 sw;
  1067. serdes_corenet_t *srds_regs =
  1068. (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  1069. u32 actual[NUM_SRDS_BANKS];
  1070. unsigned int i;
  1071. int clock;
  1072. sw = QIXIS_READ(brdcfg[2]);
  1073. clock = serdes_refclock(sw, 1);
  1074. if (clock >= 0)
  1075. actual[0] = clock;
  1076. else
  1077. printf("Warning: SDREFCLK1 switch setting is unsupported\n");
  1078. sw = QIXIS_READ(brdcfg[4]);
  1079. clock = serdes_refclock(sw, 2);
  1080. if (clock >= 0)
  1081. actual[1] = clock;
  1082. else
  1083. printf("Warning: SDREFCLK2 switch setting unsupported\n");
  1084. for (i = 0; i < NUM_SRDS_BANKS; i++) {
  1085. u32 pllcr0 = srds_regs->bank[i].pllcr0;
  1086. u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
  1087. if (expected != actual[i]) {
  1088. printf("Warning: SERDES bank %u expects reference clock"
  1089. " %sMHz, but actual is %sMHz\n", i + 1,
  1090. serdes_clock_to_string(expected),
  1091. serdes_clock_to_string(actual[i]));
  1092. }
  1093. }
  1094. return 0;
  1095. }
  1096. int ft_board_setup(void *blob, bd_t *bd)
  1097. {
  1098. phys_addr_t base;
  1099. phys_size_t size;
  1100. ft_cpu_setup(blob, bd);
  1101. base = env_get_bootm_low();
  1102. size = env_get_bootm_size();
  1103. fdt_fixup_memory(blob, (u64)base, (u64)size);
  1104. #ifdef CONFIG_PCI
  1105. pci_of_setup(blob, bd);
  1106. #endif
  1107. fdt_fixup_liodn(blob);
  1108. #ifdef CONFIG_HAS_FSL_DR_USB
  1109. fsl_fdt_fixup_dr_usb(blob, bd);
  1110. #endif
  1111. #ifdef CONFIG_SYS_DPAA_FMAN
  1112. #ifndef CONFIG_DM_ETH
  1113. fdt_fixup_fman_ethernet(blob);
  1114. #endif
  1115. fdt_fixup_board_enet(blob);
  1116. #endif
  1117. return 0;
  1118. }
  1119. /*
  1120. * Dump board switch settings.
  1121. * The bits that cannot be read/sampled via some FPGA or some
  1122. * registers, they will be displayed as
  1123. * underscore in binary format. mask[] has those bits.
  1124. * Some bits are calculated differently than the actual switches
  1125. * if booting with overriding by FPGA.
  1126. */
  1127. void qixis_dump_switch(void)
  1128. {
  1129. int i;
  1130. u8 sw[5];
  1131. /*
  1132. * Any bit with 1 means that bit cannot be reverse engineered.
  1133. * It will be displayed as _ in binary format.
  1134. */
  1135. static const u8 mask[] = {0x07, 0, 0, 0xff, 0};
  1136. char buf[10];
  1137. u8 brdcfg[16], dutcfg[16];
  1138. for (i = 0; i < 16; i++) {
  1139. brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
  1140. dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
  1141. }
  1142. sw[0] = ((brdcfg[0] & 0x0f) << 4) | \
  1143. (brdcfg[9] & 0x08);
  1144. sw[1] = ((dutcfg[1] & 0x01) << 7) | \
  1145. ((dutcfg[2] & 0x07) << 4) | \
  1146. ((dutcfg[6] & 0x10) >> 1) | \
  1147. ((dutcfg[6] & 0x80) >> 5) | \
  1148. ((dutcfg[1] & 0x40) >> 5) | \
  1149. (dutcfg[6] & 0x01);
  1150. sw[2] = dutcfg[0];
  1151. sw[3] = 0;
  1152. sw[4] = ((brdcfg[1] & 0x30) << 2) | \
  1153. ((brdcfg[1] & 0xc0) >> 2) | \
  1154. (brdcfg[1] & 0x0f);
  1155. puts("DIP switch settings:\n");
  1156. for (i = 0; i < 5; i++) {
  1157. printf("SW%d = 0b%s (0x%02x)\n",
  1158. i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
  1159. }
  1160. }