mtk_wdt.c 3.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Watchdog driver for MediaTek SoCs
  4. *
  5. * Copyright (C) 2018 MediaTek Inc.
  6. * Author: Ryder Lee <ryder.lee@mediatek.com>
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <hang.h>
  11. #include <wdt.h>
  12. #include <asm/io.h>
  13. #define MTK_WDT_MODE 0x00
  14. #define MTK_WDT_LENGTH 0x04
  15. #define MTK_WDT_RESTART 0x08
  16. #define MTK_WDT_STATUS 0x0c
  17. #define MTK_WDT_INTERVAL 0x10
  18. #define MTK_WDT_SWRST 0x14
  19. #define MTK_WDT_REQ_MODE 0x30
  20. #define MTK_WDT_DEBUG_CTL 0x40
  21. #define WDT_MODE_KEY (0x22 << 24)
  22. #define WDT_MODE_EN BIT(0)
  23. #define WDT_MODE_EXTPOL BIT(1)
  24. #define WDT_MODE_EXTEN BIT(2)
  25. #define WDT_MODE_IRQ_EN BIT(3)
  26. #define WDT_MODE_DUAL_EN BIT(6)
  27. #define WDT_LENGTH_KEY 0x8
  28. #define WDT_LENGTH_TIMEOUT(n) ((n) << 5)
  29. #define WDT_RESTART_KEY 0x1971
  30. #define WDT_SWRST_KEY 0x1209
  31. struct mtk_wdt_priv {
  32. void __iomem *base;
  33. };
  34. static int mtk_wdt_reset(struct udevice *dev)
  35. {
  36. struct mtk_wdt_priv *priv = dev_get_priv(dev);
  37. /* Reload watchdog duration */
  38. writel(WDT_RESTART_KEY, priv->base + MTK_WDT_RESTART);
  39. return 0;
  40. }
  41. static int mtk_wdt_stop(struct udevice *dev)
  42. {
  43. struct mtk_wdt_priv *priv = dev_get_priv(dev);
  44. clrsetbits_le32(priv->base + MTK_WDT_MODE, WDT_MODE_EN, WDT_MODE_KEY);
  45. return 0;
  46. }
  47. static int mtk_wdt_expire_now(struct udevice *dev, ulong flags)
  48. {
  49. struct mtk_wdt_priv *priv = dev_get_priv(dev);
  50. /* Kick watchdog to prevent counter == 0 */
  51. writel(WDT_RESTART_KEY, priv->base + MTK_WDT_RESTART);
  52. /* Reset */
  53. writel(WDT_SWRST_KEY, priv->base + MTK_WDT_SWRST);
  54. hang();
  55. return 0;
  56. }
  57. static void mtk_wdt_set_timeout(struct udevice *dev, u64 timeout_ms)
  58. {
  59. struct mtk_wdt_priv *priv = dev_get_priv(dev);
  60. u64 timeout_us;
  61. u32 timeout_cc;
  62. u32 length;
  63. /*
  64. * One WDT_LENGTH count is 512 ticks of the wdt clock
  65. * Clock runs at 32768 Hz
  66. * e.g. 15.625 ms per count (nominal)
  67. * We want the ceiling after dividing timeout_ms by 15.625 ms
  68. * We add 15624 prior to the divide to implement the ceiling
  69. * We prevent over-flow by clamping the timeout_ms value here
  70. * as the maximum WDT_LENGTH counts is 1023 -> 15.984375 sec
  71. * We also enforce a minimum of 1 count
  72. * Many watchdog peripherals have a self-imposed count of 1
  73. * that is added to the register counts.
  74. * The MediaTek docs lack details to know if this is the case here.
  75. * So we enforce a minimum of 1 to guarantee operation.
  76. */
  77. if (timeout_ms > 15984)
  78. timeout_ms = 15984;
  79. timeout_us = timeout_ms * 1000;
  80. timeout_cc = (15624 + timeout_us) / 15625;
  81. if (timeout_cc == 0)
  82. timeout_cc = 1;
  83. length = WDT_LENGTH_TIMEOUT(timeout_cc) | WDT_LENGTH_KEY;
  84. writel(length, priv->base + MTK_WDT_LENGTH);
  85. }
  86. static int mtk_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
  87. {
  88. struct mtk_wdt_priv *priv = dev_get_priv(dev);
  89. mtk_wdt_set_timeout(dev, timeout_ms);
  90. mtk_wdt_reset(dev);
  91. /* Enable watchdog reset signal */
  92. setbits_le32(priv->base + MTK_WDT_MODE,
  93. WDT_MODE_EN | WDT_MODE_KEY | WDT_MODE_EXTEN);
  94. return 0;
  95. }
  96. static int mtk_wdt_probe(struct udevice *dev)
  97. {
  98. struct mtk_wdt_priv *priv = dev_get_priv(dev);
  99. priv->base = dev_read_addr_ptr(dev);
  100. if (!priv->base)
  101. return -ENOENT;
  102. /* Clear status */
  103. clrsetbits_le32(priv->base + MTK_WDT_MODE,
  104. WDT_MODE_IRQ_EN | WDT_MODE_EXTPOL, WDT_MODE_KEY);
  105. return mtk_wdt_stop(dev);
  106. }
  107. static const struct wdt_ops mtk_wdt_ops = {
  108. .start = mtk_wdt_start,
  109. .reset = mtk_wdt_reset,
  110. .stop = mtk_wdt_stop,
  111. .expire_now = mtk_wdt_expire_now,
  112. };
  113. static const struct udevice_id mtk_wdt_ids[] = {
  114. { .compatible = "mediatek,wdt"},
  115. { .compatible = "mediatek,mt6589-wdt"},
  116. {}
  117. };
  118. U_BOOT_DRIVER(mtk_wdt) = {
  119. .name = "mtk_wdt",
  120. .id = UCLASS_WDT,
  121. .of_match = mtk_wdt_ids,
  122. .priv_auto_alloc_size = sizeof(struct mtk_wdt_priv),
  123. .probe = mtk_wdt_probe,
  124. .ops = &mtk_wdt_ops,
  125. .flags = DM_FLAG_PRE_RELOC,
  126. };