pci.c 2.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013 Keymile AG
  4. * Valentin Longchamp <valentin.longchamp@keymile.com>
  5. *
  6. * Copyright 2007-2011 Freescale Semiconductor, Inc.
  7. */
  8. #include <common.h>
  9. #include <command.h>
  10. #include <init.h>
  11. #include <pci.h>
  12. #include <asm/fsl_pci.h>
  13. #include <linux/libfdt.h>
  14. #include <fdt_support.h>
  15. #include <asm/fsl_serdes.h>
  16. #include <linux/errno.h>
  17. #include "kmp204x.h"
  18. #define PROM_SEL_L 11
  19. /* control the PROM_SEL_L signal*/
  20. static void toggle_fpga_eeprom_bus(bool cpu_own)
  21. {
  22. qrio_gpio_direction_output(GPIO_A, PROM_SEL_L, !cpu_own);
  23. }
  24. #define CONF_SEL_L 10
  25. #define FPGA_PROG_L 19
  26. #define FPGA_DONE 18
  27. #define FPGA_INIT_L 17
  28. int trigger_fpga_config(void)
  29. {
  30. int ret = 0, init_l;
  31. /* approx 10ms */
  32. u32 timeout = 10000;
  33. /* make sure the FPGA_can access the EEPROM */
  34. toggle_fpga_eeprom_bus(false);
  35. /* assert CONF_SEL_L to be able to drive FPGA_PROG_L */
  36. qrio_gpio_direction_output(GPIO_A, CONF_SEL_L, 0);
  37. /* trigger the config start */
  38. qrio_gpio_direction_output(GPIO_A, FPGA_PROG_L, 0);
  39. /* small delay for INIT_L line */
  40. udelay(10);
  41. /* wait for FPGA_INIT to be asserted */
  42. do {
  43. init_l = qrio_get_gpio(GPIO_A, FPGA_INIT_L);
  44. if (timeout-- == 0) {
  45. printf("FPGA_INIT timeout\n");
  46. ret = -EFAULT;
  47. break;
  48. }
  49. udelay(10);
  50. } while (init_l);
  51. /* deassert FPGA_PROG, config should start */
  52. qrio_set_gpio(GPIO_A, FPGA_PROG_L, 1);
  53. return ret;
  54. }
  55. /* poll the FPGA_DONE signal and give the EEPROM back to the QorIQ */
  56. static int wait_for_fpga_config(void)
  57. {
  58. int ret = 0, done;
  59. /* approx 5 s */
  60. u32 timeout = 500000;
  61. printf("PCIe FPGA config:");
  62. do {
  63. done = qrio_get_gpio(GPIO_A, FPGA_DONE);
  64. if (timeout-- == 0) {
  65. printf(" FPGA_DONE timeout\n");
  66. ret = -EFAULT;
  67. goto err_out;
  68. }
  69. udelay(10);
  70. } while (!done);
  71. printf(" done\n");
  72. err_out:
  73. /* deactive CONF_SEL and give the CPU conf EEPROM access */
  74. qrio_set_gpio(GPIO_A, CONF_SEL_L, 1);
  75. toggle_fpga_eeprom_bus(true);
  76. return ret;
  77. }
  78. #define PCIE_SW_RST 14
  79. #define PEXHC_RST 13
  80. #define HOOPER_RST 12
  81. void pci_init_board(void)
  82. {
  83. qrio_prstcfg(PCIE_SW_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
  84. qrio_prstcfg(PEXHC_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
  85. qrio_prstcfg(HOOPER_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
  86. /* wait for the PCIe FPGA to be configured
  87. * it has been triggered earlier in board_early_init_r */
  88. if (wait_for_fpga_config())
  89. printf("error finishing PCIe FPGA config\n");
  90. qrio_prst(PCIE_SW_RST, false, false);
  91. qrio_prst(PEXHC_RST, false, false);
  92. qrio_prst(HOOPER_RST, false, false);
  93. /* Hooper is not direcly PCIe capable */
  94. mdelay(50);
  95. fsl_pcie_init_board(0);
  96. }
  97. void pci_of_setup(void *blob, bd_t *bd)
  98. {
  99. FT_FSL_PCI_SETUP;
  100. }