hrcon.c 9.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2014
  4. * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
  5. */
  6. #include <common.h>
  7. #include <env.h>
  8. #include <hwconfig.h>
  9. #include <i2c.h>
  10. #include <init.h>
  11. #include <spi.h>
  12. #include <linux/libfdt.h>
  13. #include <fdt_support.h>
  14. #include <pci.h>
  15. #include <mpc83xx.h>
  16. #include <fsl_esdhc.h>
  17. #include <asm/io.h>
  18. #include <asm/fsl_serdes.h>
  19. #include <asm/fsl_mpc83xx_serdes.h>
  20. #include "mpc8308.h"
  21. #include <gdsys_fpga.h>
  22. #include "../common/ioep-fpga.h"
  23. #include "../common/osd.h"
  24. #include "../common/mclink.h"
  25. #include "../common/phy.h"
  26. #include "../common/fanctrl.h"
  27. #include <pca953x.h>
  28. #include <pca9698.h>
  29. #include <miiphy.h>
  30. #define MAX_MUX_CHANNELS 2
  31. enum {
  32. MCFPGA_DONE = BIT(0),
  33. MCFPGA_INIT_N = BIT(1),
  34. MCFPGA_PROGRAM_N = BIT(2),
  35. MCFPGA_UPDATE_ENABLE_N = BIT(3),
  36. MCFPGA_RESET_N = BIT(4),
  37. };
  38. enum {
  39. GPIO_MDC = 1 << 14,
  40. GPIO_MDIO = 1 << 15,
  41. };
  42. uint mclink_fpgacount;
  43. struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
  44. struct {
  45. u8 bus;
  46. u8 addr;
  47. } hrcon_fans[] = CONFIG_HRCON_FANS;
  48. int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
  49. {
  50. int res;
  51. switch (fpga) {
  52. case 0:
  53. out_le16(reg, data);
  54. break;
  55. default:
  56. res = mclink_send(fpga - 1, regoff, data);
  57. if (res < 0) {
  58. printf("mclink_send reg %02lx data %04x returned %d\n",
  59. regoff, data, res);
  60. return res;
  61. }
  62. break;
  63. }
  64. return 0;
  65. }
  66. int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
  67. {
  68. int res;
  69. switch (fpga) {
  70. case 0:
  71. *data = in_le16(reg);
  72. break;
  73. default:
  74. if (fpga > mclink_fpgacount)
  75. return -EINVAL;
  76. res = mclink_receive(fpga - 1, regoff, data);
  77. if (res < 0) {
  78. printf("mclink_receive reg %02lx returned %d\n",
  79. regoff, res);
  80. return res;
  81. }
  82. }
  83. return 0;
  84. }
  85. int checkboard(void)
  86. {
  87. char *s = env_get("serial#");
  88. bool hw_type_cat = pca9698_get_value(0x20, 20);
  89. puts("Board: ");
  90. printf("HRCon %s", hw_type_cat ? "CAT" : "Fiber");
  91. if (s) {
  92. puts(", serial# ");
  93. puts(s);
  94. }
  95. puts("\n");
  96. return 0;
  97. }
  98. int last_stage_init(void)
  99. {
  100. int slaves;
  101. uint k;
  102. uchar mclink_controllers[] = { 0x3c, 0x3d, 0x3e };
  103. u16 fpga_features;
  104. bool hw_type_cat = pca9698_get_value(0x20, 20);
  105. bool ch0_rgmii2_present;
  106. FPGA_GET_REG(0, fpga_features, &fpga_features);
  107. /* Turn on Parade DP501 */
  108. pca9698_direction_output(0x20, 10, 1);
  109. pca9698_direction_output(0x20, 11, 1);
  110. ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
  111. /* wait for FPGA done, then reset FPGA */
  112. for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {
  113. uint ctr = 0;
  114. if (i2c_probe(mclink_controllers[k]))
  115. continue;
  116. while (!(pca953x_get_val(mclink_controllers[k])
  117. & MCFPGA_DONE)) {
  118. mdelay(100);
  119. if (ctr++ > 5) {
  120. printf("no done for mclink_controller %u\n", k);
  121. break;
  122. }
  123. }
  124. pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
  125. pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
  126. udelay(10);
  127. pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
  128. MCFPGA_RESET_N);
  129. }
  130. if (hw_type_cat) {
  131. uint mux_ch;
  132. int retval;
  133. struct mii_dev *mdiodev = mdio_alloc();
  134. if (!mdiodev)
  135. return -ENOMEM;
  136. strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
  137. mdiodev->read = bb_miiphy_read;
  138. mdiodev->write = bb_miiphy_write;
  139. retval = mdio_register(mdiodev);
  140. if (retval < 0)
  141. return retval;
  142. for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
  143. if ((mux_ch == 1) && !ch0_rgmii2_present)
  144. continue;
  145. setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
  146. }
  147. }
  148. /* give slave-PLLs and Parade DP501 some time to be up and running */
  149. mdelay(500);
  150. mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
  151. slaves = mclink_probe();
  152. mclink_fpgacount = 0;
  153. ioep_fpga_print_info(0);
  154. osd_probe(0);
  155. #ifdef CONFIG_SYS_OSD_DH
  156. osd_probe(4);
  157. #endif
  158. if (slaves <= 0)
  159. return 0;
  160. mclink_fpgacount = slaves;
  161. for (k = 1; k <= slaves; ++k) {
  162. FPGA_GET_REG(k, fpga_features, &fpga_features);
  163. ioep_fpga_print_info(k);
  164. osd_probe(k);
  165. #ifdef CONFIG_SYS_OSD_DH
  166. osd_probe(k + 4);
  167. #endif
  168. if (hw_type_cat) {
  169. int retval;
  170. struct mii_dev *mdiodev = mdio_alloc();
  171. if (!mdiodev)
  172. return -ENOMEM;
  173. strncpy(mdiodev->name, bb_miiphy_buses[k].name,
  174. MDIO_NAME_LEN);
  175. mdiodev->read = bb_miiphy_read;
  176. mdiodev->write = bb_miiphy_write;
  177. retval = mdio_register(mdiodev);
  178. if (retval < 0)
  179. return retval;
  180. setup_88e1514(bb_miiphy_buses[k].name, 0);
  181. }
  182. }
  183. for (k = 0; k < ARRAY_SIZE(hrcon_fans); ++k) {
  184. i2c_set_bus_num(hrcon_fans[k].bus);
  185. init_fan_controller(hrcon_fans[k].addr);
  186. }
  187. return 0;
  188. }
  189. /*
  190. * provide access to fpga gpios and controls (for I2C bitbang)
  191. * (these may look all too simple but make iocon.h much more readable)
  192. */
  193. void fpga_gpio_set(uint bus, int pin)
  194. {
  195. FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.set, pin);
  196. }
  197. void fpga_gpio_clear(uint bus, int pin)
  198. {
  199. FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.clear, pin);
  200. }
  201. int fpga_gpio_get(uint bus, int pin)
  202. {
  203. u16 val;
  204. FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, gpio.read, &val);
  205. return val & pin;
  206. }
  207. void fpga_control_set(uint bus, int pin)
  208. {
  209. u16 val;
  210. FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, control, &val);
  211. FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val | pin);
  212. }
  213. void fpga_control_clear(uint bus, int pin)
  214. {
  215. u16 val;
  216. FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, control, &val);
  217. FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val & ~pin);
  218. }
  219. void mpc8308_init(void)
  220. {
  221. pca9698_direction_output(0x20, 4, 1);
  222. }
  223. void mpc8308_set_fpga_reset(uint state)
  224. {
  225. pca9698_set_value(0x20, 4, state ? 0 : 1);
  226. }
  227. void mpc8308_setup_hw(void)
  228. {
  229. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  230. /*
  231. * set "startup-finished"-gpios
  232. */
  233. setbits_be32(&immr->gpio[0].dir, BIT(31 - 11) | BIT(31 - 12));
  234. setbits_gpio0_out(BIT(31 - 12));
  235. }
  236. int mpc8308_get_fpga_done(uint fpga)
  237. {
  238. return pca9698_get_value(0x20, 19);
  239. }
  240. #ifdef CONFIG_FSL_ESDHC
  241. int board_mmc_init(bd_t *bd)
  242. {
  243. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  244. sysconf83xx_t *sysconf = &immr->sysconf;
  245. /* Enable cache snooping in eSDHC system configuration register */
  246. out_be32(&sysconf->sdhccr, 0x02000000);
  247. return fsl_esdhc_mmc_init(bd);
  248. }
  249. #endif
  250. static struct pci_region pcie_regions_0[] = {
  251. {
  252. .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
  253. .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
  254. .size = CONFIG_SYS_PCIE1_MEM_SIZE,
  255. .flags = PCI_REGION_MEM,
  256. },
  257. {
  258. .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
  259. .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
  260. .size = CONFIG_SYS_PCIE1_IO_SIZE,
  261. .flags = PCI_REGION_IO,
  262. },
  263. };
  264. void pci_init_board(void)
  265. {
  266. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  267. sysconf83xx_t *sysconf = &immr->sysconf;
  268. law83xx_t *pcie_law = sysconf->pcielaw;
  269. struct pci_region *pcie_reg[] = { pcie_regions_0 };
  270. fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
  271. FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
  272. /* Deassert the resets in the control register */
  273. out_be32(&sysconf->pecr1, 0xE0008000);
  274. udelay(2000);
  275. /* Configure PCI Express Local Access Windows */
  276. out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
  277. out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
  278. mpc83xx_pcie_init(1, pcie_reg);
  279. }
  280. ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
  281. {
  282. info->portwidth = FLASH_CFI_16BIT;
  283. info->chipwidth = FLASH_CFI_BY16;
  284. info->interface = FLASH_CFI_X16;
  285. return 1;
  286. }
  287. #if defined(CONFIG_OF_BOARD_SETUP)
  288. int ft_board_setup(void *blob, bd_t *bd)
  289. {
  290. ft_cpu_setup(blob, bd);
  291. fsl_fdt_fixup_dr_usb(blob, bd);
  292. fdt_fixup_esdhc(blob, bd);
  293. return 0;
  294. }
  295. #endif
  296. /*
  297. * FPGA MII bitbang implementation
  298. */
  299. struct fpga_mii {
  300. uint fpga;
  301. int mdio;
  302. } fpga_mii[] = {
  303. { 0, 1},
  304. { 1, 1},
  305. { 2, 1},
  306. { 3, 1},
  307. };
  308. static int mii_dummy_init(struct bb_miiphy_bus *bus)
  309. {
  310. return 0;
  311. }
  312. static int mii_mdio_active(struct bb_miiphy_bus *bus)
  313. {
  314. struct fpga_mii *fpga_mii = bus->priv;
  315. if (fpga_mii->mdio)
  316. FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
  317. else
  318. FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
  319. return 0;
  320. }
  321. static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
  322. {
  323. struct fpga_mii *fpga_mii = bus->priv;
  324. FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
  325. return 0;
  326. }
  327. static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
  328. {
  329. struct fpga_mii *fpga_mii = bus->priv;
  330. if (v)
  331. FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
  332. else
  333. FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
  334. fpga_mii->mdio = v;
  335. return 0;
  336. }
  337. static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
  338. {
  339. u16 gpio;
  340. struct fpga_mii *fpga_mii = bus->priv;
  341. FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
  342. *v = ((gpio & GPIO_MDIO) != 0);
  343. return 0;
  344. }
  345. static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
  346. {
  347. struct fpga_mii *fpga_mii = bus->priv;
  348. if (v)
  349. FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
  350. else
  351. FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
  352. return 0;
  353. }
  354. static int mii_delay(struct bb_miiphy_bus *bus)
  355. {
  356. udelay(1);
  357. return 0;
  358. }
  359. struct bb_miiphy_bus bb_miiphy_buses[] = {
  360. {
  361. .name = "board0",
  362. .init = mii_dummy_init,
  363. .mdio_active = mii_mdio_active,
  364. .mdio_tristate = mii_mdio_tristate,
  365. .set_mdio = mii_set_mdio,
  366. .get_mdio = mii_get_mdio,
  367. .set_mdc = mii_set_mdc,
  368. .delay = mii_delay,
  369. .priv = &fpga_mii[0],
  370. },
  371. {
  372. .name = "board1",
  373. .init = mii_dummy_init,
  374. .mdio_active = mii_mdio_active,
  375. .mdio_tristate = mii_mdio_tristate,
  376. .set_mdio = mii_set_mdio,
  377. .get_mdio = mii_get_mdio,
  378. .set_mdc = mii_set_mdc,
  379. .delay = mii_delay,
  380. .priv = &fpga_mii[1],
  381. },
  382. {
  383. .name = "board2",
  384. .init = mii_dummy_init,
  385. .mdio_active = mii_mdio_active,
  386. .mdio_tristate = mii_mdio_tristate,
  387. .set_mdio = mii_set_mdio,
  388. .get_mdio = mii_get_mdio,
  389. .set_mdc = mii_set_mdc,
  390. .delay = mii_delay,
  391. .priv = &fpga_mii[2],
  392. },
  393. {
  394. .name = "board3",
  395. .init = mii_dummy_init,
  396. .mdio_active = mii_mdio_active,
  397. .mdio_tristate = mii_mdio_tristate,
  398. .set_mdio = mii_set_mdio,
  399. .get_mdio = mii_get_mdio,
  400. .set_mdc = mii_set_mdc,
  401. .delay = mii_delay,
  402. .priv = &fpga_mii[3],
  403. },
  404. };
  405. int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);