mpc8568mds.c 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
  4. *
  5. * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  6. */
  7. #include <common.h>
  8. #include <init.h>
  9. #include <pci.h>
  10. #include <asm/processor.h>
  11. #include <asm/mmu.h>
  12. #include <asm/immap_85xx.h>
  13. #include <asm/fsl_pci.h>
  14. #include <fsl_ddr_sdram.h>
  15. #include <asm/fsl_serdes.h>
  16. #include <spd_sdram.h>
  17. #include <i2c.h>
  18. #include <ioports.h>
  19. #include <linux/libfdt.h>
  20. #include <fdt_support.h>
  21. #include "bcsr.h"
  22. const qe_iop_conf_t qe_iop_conf_tab[] = {
  23. /* GETH1 */
  24. {4, 10, 1, 0, 2}, /* TxD0 */
  25. {4, 9, 1, 0, 2}, /* TxD1 */
  26. {4, 8, 1, 0, 2}, /* TxD2 */
  27. {4, 7, 1, 0, 2}, /* TxD3 */
  28. {4, 23, 1, 0, 2}, /* TxD4 */
  29. {4, 22, 1, 0, 2}, /* TxD5 */
  30. {4, 21, 1, 0, 2}, /* TxD6 */
  31. {4, 20, 1, 0, 2}, /* TxD7 */
  32. {4, 15, 2, 0, 2}, /* RxD0 */
  33. {4, 14, 2, 0, 2}, /* RxD1 */
  34. {4, 13, 2, 0, 2}, /* RxD2 */
  35. {4, 12, 2, 0, 2}, /* RxD3 */
  36. {4, 29, 2, 0, 2}, /* RxD4 */
  37. {4, 28, 2, 0, 2}, /* RxD5 */
  38. {4, 27, 2, 0, 2}, /* RxD6 */
  39. {4, 26, 2, 0, 2}, /* RxD7 */
  40. {4, 11, 1, 0, 2}, /* TX_EN */
  41. {4, 24, 1, 0, 2}, /* TX_ER */
  42. {4, 16, 2, 0, 2}, /* RX_DV */
  43. {4, 30, 2, 0, 2}, /* RX_ER */
  44. {4, 17, 2, 0, 2}, /* RX_CLK */
  45. {4, 19, 1, 0, 2}, /* GTX_CLK */
  46. {1, 31, 2, 0, 3}, /* GTX125 */
  47. /* GETH2 */
  48. {5, 10, 1, 0, 2}, /* TxD0 */
  49. {5, 9, 1, 0, 2}, /* TxD1 */
  50. {5, 8, 1, 0, 2}, /* TxD2 */
  51. {5, 7, 1, 0, 2}, /* TxD3 */
  52. {5, 23, 1, 0, 2}, /* TxD4 */
  53. {5, 22, 1, 0, 2}, /* TxD5 */
  54. {5, 21, 1, 0, 2}, /* TxD6 */
  55. {5, 20, 1, 0, 2}, /* TxD7 */
  56. {5, 15, 2, 0, 2}, /* RxD0 */
  57. {5, 14, 2, 0, 2}, /* RxD1 */
  58. {5, 13, 2, 0, 2}, /* RxD2 */
  59. {5, 12, 2, 0, 2}, /* RxD3 */
  60. {5, 29, 2, 0, 2}, /* RxD4 */
  61. {5, 28, 2, 0, 2}, /* RxD5 */
  62. {5, 27, 2, 0, 3}, /* RxD6 */
  63. {5, 26, 2, 0, 2}, /* RxD7 */
  64. {5, 11, 1, 0, 2}, /* TX_EN */
  65. {5, 24, 1, 0, 2}, /* TX_ER */
  66. {5, 16, 2, 0, 2}, /* RX_DV */
  67. {5, 30, 2, 0, 2}, /* RX_ER */
  68. {5, 17, 2, 0, 2}, /* RX_CLK */
  69. {5, 19, 1, 0, 2}, /* GTX_CLK */
  70. {1, 31, 2, 0, 3}, /* GTX125 */
  71. {4, 6, 3, 0, 2}, /* MDIO */
  72. {4, 5, 1, 0, 2}, /* MDC */
  73. /* UART1 */
  74. {2, 0, 1, 0, 2}, /* UART_SOUT1 */
  75. {2, 1, 1, 0, 2}, /* UART_RTS1 */
  76. {2, 2, 2, 0, 2}, /* UART_CTS1 */
  77. {2, 3, 2, 0, 2}, /* UART_SIN1 */
  78. {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
  79. };
  80. void local_bus_init(void);
  81. int board_early_init_f (void)
  82. {
  83. /*
  84. * Initialize local bus.
  85. */
  86. local_bus_init ();
  87. enable_8568mds_duart();
  88. enable_8568mds_flash_write();
  89. #if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
  90. reset_8568mds_uccs();
  91. #endif
  92. #if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
  93. enable_8568mds_qe_mdio();
  94. #endif
  95. #ifdef CONFIG_SYS_I2C2_OFFSET
  96. /* Enable I2C2_SCL and I2C2_SDA */
  97. volatile struct par_io *port_c;
  98. port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140);
  99. port_c->cpdir2 |= 0x0f000000;
  100. port_c->cppar2 &= ~0x0f000000;
  101. port_c->cppar2 |= 0x0a000000;
  102. #endif
  103. return 0;
  104. }
  105. int checkboard (void)
  106. {
  107. printf ("Board: 8568 MDS\n");
  108. return 0;
  109. }
  110. /*
  111. * Initialize Local Bus
  112. */
  113. void
  114. local_bus_init(void)
  115. {
  116. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  117. volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  118. uint clkdiv;
  119. sys_info_t sysinfo;
  120. get_sys_info(&sysinfo);
  121. clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
  122. gur->lbiuiplldcr1 = 0x00078080;
  123. if (clkdiv == 16) {
  124. gur->lbiuiplldcr0 = 0x7c0f1bf0;
  125. } else if (clkdiv == 8) {
  126. gur->lbiuiplldcr0 = 0x6c0f1bf0;
  127. } else if (clkdiv == 4) {
  128. gur->lbiuiplldcr0 = 0x5c0f1bf0;
  129. }
  130. lbc->lcrr |= 0x00030000;
  131. asm("sync;isync;msync");
  132. }
  133. /*
  134. * Initialize SDRAM memory on the Local Bus.
  135. */
  136. void lbc_sdram_init(void)
  137. {
  138. #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
  139. uint idx;
  140. volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  141. uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
  142. uint lsdmr_common;
  143. puts("LBC SDRAM: ");
  144. print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
  145. "\n ");
  146. /*
  147. * Setup SDRAM Base and Option Registers
  148. */
  149. set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
  150. set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
  151. asm("msync");
  152. lbc->lbcr = CONFIG_SYS_LBC_LBCR;
  153. asm("msync");
  154. lbc->lsrt = CONFIG_SYS_LBC_LSRT;
  155. lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
  156. asm("msync");
  157. /*
  158. * MPC8568 uses "new" 15-16 style addressing.
  159. */
  160. lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
  161. lsdmr_common |= LSDMR_BSMA1516;
  162. /*
  163. * Issue PRECHARGE ALL command.
  164. */
  165. lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
  166. asm("sync;msync");
  167. *sdram_addr = 0xff;
  168. ppcDcbf((unsigned long) sdram_addr);
  169. udelay(100);
  170. /*
  171. * Issue 8 AUTO REFRESH commands.
  172. */
  173. for (idx = 0; idx < 8; idx++) {
  174. lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
  175. asm("sync;msync");
  176. *sdram_addr = 0xff;
  177. ppcDcbf((unsigned long) sdram_addr);
  178. udelay(100);
  179. }
  180. /*
  181. * Issue 8 MODE-set command.
  182. */
  183. lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
  184. asm("sync;msync");
  185. *sdram_addr = 0xff;
  186. ppcDcbf((unsigned long) sdram_addr);
  187. udelay(100);
  188. /*
  189. * Issue NORMAL OP command.
  190. */
  191. lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
  192. asm("sync;msync");
  193. *sdram_addr = 0xff;
  194. ppcDcbf((unsigned long) sdram_addr);
  195. udelay(200); /* Overkill. Must wait > 200 bus cycles */
  196. #endif /* enable SDRAM init */
  197. }
  198. #if defined(CONFIG_PCI)
  199. #ifndef CONFIG_PCI_PNP
  200. static struct pci_config_table pci_mpc8568mds_config_table[] = {
  201. {
  202. PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  203. pci_cfgfunc_config_device,
  204. {PCI_ENET0_IOADDR,
  205. PCI_ENET0_MEMADDR,
  206. PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
  207. },
  208. {}
  209. };
  210. #endif
  211. static struct pci_controller pci1_hose;
  212. #endif /* CONFIG_PCI */
  213. /*
  214. * pib_init() -- Initialize the PCA9555 IO expander on the PIB board
  215. */
  216. void
  217. pib_init(void)
  218. {
  219. u8 val8, orig_i2c_bus;
  220. /*
  221. * Assign PIB PMC2/3 to PCI bus
  222. */
  223. /*switch temporarily to I2C bus #2 */
  224. orig_i2c_bus = i2c_get_bus_num();
  225. i2c_set_bus_num(1);
  226. val8 = 0x00;
  227. i2c_write(0x23, 0x6, 1, &val8, 1);
  228. i2c_write(0x23, 0x7, 1, &val8, 1);
  229. val8 = 0xff;
  230. i2c_write(0x23, 0x2, 1, &val8, 1);
  231. i2c_write(0x23, 0x3, 1, &val8, 1);
  232. val8 = 0x00;
  233. i2c_write(0x26, 0x6, 1, &val8, 1);
  234. val8 = 0x34;
  235. i2c_write(0x26, 0x7, 1, &val8, 1);
  236. val8 = 0xf9;
  237. i2c_write(0x26, 0x2, 1, &val8, 1);
  238. val8 = 0xff;
  239. i2c_write(0x26, 0x3, 1, &val8, 1);
  240. val8 = 0x00;
  241. i2c_write(0x27, 0x6, 1, &val8, 1);
  242. i2c_write(0x27, 0x7, 1, &val8, 1);
  243. val8 = 0xff;
  244. i2c_write(0x27, 0x2, 1, &val8, 1);
  245. val8 = 0xef;
  246. i2c_write(0x27, 0x3, 1, &val8, 1);
  247. asm("eieio");
  248. i2c_set_bus_num(orig_i2c_bus);
  249. }
  250. #ifdef CONFIG_PCI
  251. void pci_init_board(void)
  252. {
  253. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  254. int first_free_busno = 0;
  255. #ifdef CONFIG_PCI1
  256. struct fsl_pci_info pci_info;
  257. u32 devdisr, pordevsr, io_sel;
  258. u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
  259. devdisr = in_be32(&gur->devdisr);
  260. pordevsr = in_be32(&gur->pordevsr);
  261. porpllsr = in_be32(&gur->porpllsr);
  262. io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
  263. debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
  264. pci_speed = 66666000;
  265. pci_32 = 1;
  266. pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
  267. pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
  268. if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
  269. SET_STD_PCI_INFO(pci_info, 1);
  270. set_next_law(pci_info.mem_phys,
  271. law_size_bits(pci_info.mem_size), pci_info.law);
  272. set_next_law(pci_info.io_phys,
  273. law_size_bits(pci_info.io_size), pci_info.law);
  274. pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
  275. printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
  276. (pci_32) ? 32 : 64,
  277. (pci_speed == 33333000) ? "33" :
  278. (pci_speed == 66666000) ? "66" : "unknown",
  279. pci_clk_sel ? "sync" : "async",
  280. pci_agent ? "agent" : "host",
  281. pci_arb ? "arbiter" : "external-arbiter",
  282. pci_info.regs);
  283. #ifndef CONFIG_PCI_PNP
  284. pci1_hose.config_table = pci_mpc8568mds_config_table;
  285. #endif
  286. first_free_busno = fsl_pci_init_port(&pci_info,
  287. &pci1_hose, first_free_busno);
  288. } else {
  289. printf("PCI: disabled\n");
  290. }
  291. puts("\n");
  292. #else
  293. setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
  294. #endif
  295. fsl_pcie_init_board(first_free_busno);
  296. }
  297. #endif /* CONFIG_PCI */
  298. #if defined(CONFIG_OF_BOARD_SETUP)
  299. int ft_board_setup(void *blob, bd_t *bd)
  300. {
  301. ft_cpu_setup(blob, bd);
  302. FT_FSL_PCI_SETUP;
  303. return 0;
  304. }
  305. #endif