mpc8548cds.c 8.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2004, 2007, 2009-2011 Freescale Semiconductor, Inc.
  4. *
  5. * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
  6. */
  7. #include <common.h>
  8. #include <init.h>
  9. #include <pci.h>
  10. #include <vsprintf.h>
  11. #include <asm/processor.h>
  12. #include <asm/mmu.h>
  13. #include <asm/immap_85xx.h>
  14. #include <asm/fsl_pci.h>
  15. #include <fsl_ddr_sdram.h>
  16. #include <asm/fsl_serdes.h>
  17. #include <miiphy.h>
  18. #include <linux/libfdt.h>
  19. #include <fdt_support.h>
  20. #include <tsec.h>
  21. #include <fsl_mdio.h>
  22. #include <netdev.h>
  23. #include "../common/cadmus.h"
  24. #include "../common/eeprom.h"
  25. #include "../common/via.h"
  26. void local_bus_init(void);
  27. int checkboard (void)
  28. {
  29. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  30. volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
  31. /* PCI slot in USER bits CSR[6:7] by convention. */
  32. uint pci_slot = get_pci_slot ();
  33. uint cpu_board_rev = get_cpu_board_revision ();
  34. puts("Board: MPC8548CDS");
  35. printf(" Carrier Rev: 0x%02x, PCI Slot %d\n",
  36. get_board_version(), pci_slot);
  37. printf(" Daughtercard Rev: %d.%d (0x%04x)\n",
  38. MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
  39. MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
  40. /*
  41. * Initialize local bus.
  42. */
  43. local_bus_init ();
  44. /*
  45. * Hack TSEC 3 and 4 IO voltages.
  46. */
  47. gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
  48. ecm->eedr = 0xffffffff; /* clear ecm errors */
  49. ecm->eeer = 0xffffffff; /* enable ecm errors */
  50. return 0;
  51. }
  52. /*
  53. * Initialize Local Bus
  54. */
  55. void
  56. local_bus_init(void)
  57. {
  58. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  59. volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  60. uint clkdiv;
  61. sys_info_t sysinfo;
  62. get_sys_info(&sysinfo);
  63. clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
  64. gur->lbiuiplldcr1 = 0x00078080;
  65. if (clkdiv == 16) {
  66. gur->lbiuiplldcr0 = 0x7c0f1bf0;
  67. } else if (clkdiv == 8) {
  68. gur->lbiuiplldcr0 = 0x6c0f1bf0;
  69. } else if (clkdiv == 4) {
  70. gur->lbiuiplldcr0 = 0x5c0f1bf0;
  71. }
  72. lbc->lcrr |= 0x00030000;
  73. asm("sync;isync;msync");
  74. lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
  75. lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
  76. }
  77. /*
  78. * Initialize SDRAM memory on the Local Bus.
  79. */
  80. void lbc_sdram_init(void)
  81. {
  82. #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
  83. uint idx;
  84. volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
  85. uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
  86. uint lsdmr_common;
  87. puts("LBC SDRAM: ");
  88. print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
  89. "\n");
  90. /*
  91. * Setup SDRAM Base and Option Registers
  92. */
  93. set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
  94. set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
  95. lbc->lbcr = CONFIG_SYS_LBC_LBCR;
  96. asm("msync");
  97. lbc->lsrt = CONFIG_SYS_LBC_LSRT;
  98. lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
  99. asm("msync");
  100. /*
  101. * MPC8548 uses "new" 15-16 style addressing.
  102. */
  103. lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
  104. lsdmr_common |= LSDMR_BSMA1516;
  105. /*
  106. * Issue PRECHARGE ALL command.
  107. */
  108. lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
  109. asm("sync;msync");
  110. *sdram_addr = 0xff;
  111. ppcDcbf((unsigned long) sdram_addr);
  112. udelay(100);
  113. /*
  114. * Issue 8 AUTO REFRESH commands.
  115. */
  116. for (idx = 0; idx < 8; idx++) {
  117. lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
  118. asm("sync;msync");
  119. *sdram_addr = 0xff;
  120. ppcDcbf((unsigned long) sdram_addr);
  121. udelay(100);
  122. }
  123. /*
  124. * Issue 8 MODE-set command.
  125. */
  126. lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
  127. asm("sync;msync");
  128. *sdram_addr = 0xff;
  129. ppcDcbf((unsigned long) sdram_addr);
  130. udelay(100);
  131. /*
  132. * Issue NORMAL OP command.
  133. */
  134. lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
  135. asm("sync;msync");
  136. *sdram_addr = 0xff;
  137. ppcDcbf((unsigned long) sdram_addr);
  138. udelay(200); /* Overkill. Must wait > 200 bus cycles */
  139. #endif /* enable SDRAM init */
  140. }
  141. #if (defined(CONFIG_PCI) || defined(CONFIG_PCI1)) && !defined(CONFIG_DM_PCI)
  142. /* For some reason the Tundra PCI bridge shows up on itself as a
  143. * different device. Work around that by refusing to configure it.
  144. */
  145. void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
  146. static struct pci_config_table pci_mpc85xxcds_config_table[] = {
  147. {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
  148. {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
  149. {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
  150. mpc85xx_config_via_usbide, {0,0,0}},
  151. {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
  152. mpc85xx_config_via_usb, {0,0,0}},
  153. {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
  154. mpc85xx_config_via_usb2, {0,0,0}},
  155. {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
  156. mpc85xx_config_via_power, {0,0,0}},
  157. {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
  158. mpc85xx_config_via_ac97, {0,0,0}},
  159. {},
  160. };
  161. static struct pci_controller pci1_hose;
  162. #endif /* CONFIG_PCI */
  163. #if !defined(CONFIG_DM_PCI)
  164. void pci_init_board(void)
  165. {
  166. volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  167. struct fsl_pci_info pci_info;
  168. u32 devdisr, pordevsr, io_sel;
  169. u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
  170. int first_free_busno = 0;
  171. char buf[32];
  172. devdisr = in_be32(&gur->devdisr);
  173. pordevsr = in_be32(&gur->pordevsr);
  174. porpllsr = in_be32(&gur->porpllsr);
  175. io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
  176. debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
  177. #ifdef CONFIG_PCI1
  178. pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
  179. pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
  180. pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
  181. pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
  182. if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
  183. SET_STD_PCI_INFO(pci_info, 1);
  184. set_next_law(pci_info.mem_phys,
  185. law_size_bits(pci_info.mem_size), pci_info.law);
  186. set_next_law(pci_info.io_phys,
  187. law_size_bits(pci_info.io_size), pci_info.law);
  188. pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
  189. printf("PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
  190. (pci_32) ? 32 : 64,
  191. strmhz(buf, pci_speed),
  192. pci_clk_sel ? "sync" : "async",
  193. pci_agent ? "agent" : "host",
  194. pci_arb ? "arbiter" : "external-arbiter",
  195. pci_info.regs);
  196. pci1_hose.config_table = pci_mpc85xxcds_config_table;
  197. first_free_busno = fsl_pci_init_port(&pci_info,
  198. &pci1_hose, first_free_busno);
  199. #ifdef CONFIG_PCIX_CHECK
  200. if (!(pordevsr & MPC85xx_PORDEVSR_PCI1)) {
  201. /* PCI-X init */
  202. if (CONFIG_SYS_CLK_FREQ < 66000000)
  203. printf("PCI-X will only work at 66 MHz\n");
  204. reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
  205. | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
  206. pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
  207. }
  208. #endif
  209. } else {
  210. printf("PCI1: disabled\n");
  211. }
  212. puts("\n");
  213. #else
  214. setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
  215. #endif
  216. #ifdef CONFIG_PCI2
  217. {
  218. uint pci2_clk_sel = porpllsr & 0x4000; /* PORPLLSR[17] */
  219. uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
  220. if (pci_dual) {
  221. printf("PCI2: 32 bit, 66 MHz, %s\n",
  222. pci2_clk_sel ? "sync" : "async");
  223. } else {
  224. printf("PCI2: disabled\n");
  225. }
  226. }
  227. #else
  228. setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */
  229. #endif /* CONFIG_PCI2 */
  230. fsl_pcie_init_board(first_free_busno);
  231. }
  232. #endif
  233. void configure_rgmii(void)
  234. {
  235. unsigned short temp;
  236. /* Change the resistors for the PHY */
  237. /* This is needed to get the RGMII working for the 1.3+
  238. * CDS cards */
  239. if (get_board_version() == 0x13) {
  240. miiphy_write(DEFAULT_MII_NAME,
  241. TSEC1_PHY_ADDR, 29, 18);
  242. miiphy_read(DEFAULT_MII_NAME,
  243. TSEC1_PHY_ADDR, 30, &temp);
  244. temp = (temp & 0xf03f);
  245. temp |= 2 << 9; /* 36 ohm */
  246. temp |= 2 << 6; /* 39 ohm */
  247. miiphy_write(DEFAULT_MII_NAME,
  248. TSEC1_PHY_ADDR, 30, temp);
  249. miiphy_write(DEFAULT_MII_NAME,
  250. TSEC1_PHY_ADDR, 29, 3);
  251. miiphy_write(DEFAULT_MII_NAME,
  252. TSEC1_PHY_ADDR, 30, 0x8000);
  253. }
  254. return;
  255. }
  256. int board_eth_init(bd_t *bis)
  257. {
  258. #ifdef CONFIG_TSEC_ENET
  259. struct fsl_pq_mdio_info mdio_info;
  260. struct tsec_info_struct tsec_info[4];
  261. int num = 0;
  262. #ifdef CONFIG_TSEC1
  263. SET_STD_TSEC_INFO(tsec_info[num], 1);
  264. num++;
  265. #endif
  266. #ifdef CONFIG_TSEC2
  267. SET_STD_TSEC_INFO(tsec_info[num], 2);
  268. num++;
  269. #endif
  270. #ifdef CONFIG_TSEC3
  271. /* initialize TSEC3 only if Carrier is 1.3 or above on CDS */
  272. if (get_board_version() >= 0x13) {
  273. SET_STD_TSEC_INFO(tsec_info[num], 3);
  274. tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
  275. num++;
  276. }
  277. #endif
  278. #ifdef CONFIG_TSEC4
  279. /* initialize TSEC4 only if Carrier is 1.3 or above on CDS */
  280. if (get_board_version() >= 0x13) {
  281. SET_STD_TSEC_INFO(tsec_info[num], 4);
  282. tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
  283. num++;
  284. }
  285. #endif
  286. if (!num) {
  287. printf("No TSECs initialized\n");
  288. return 0;
  289. }
  290. mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
  291. mdio_info.name = DEFAULT_MII_NAME;
  292. fsl_pq_mdio_init(bis, &mdio_info);
  293. tsec_eth_init(bis, tsec_info, num);
  294. configure_rgmii();
  295. #endif
  296. return pci_eth_init(bis);
  297. }
  298. #if defined(CONFIG_OF_BOARD_SETUP) && !defined(CONFIG_DM_PCI)
  299. void ft_pci_setup(void *blob, bd_t *bd)
  300. {
  301. FT_FSL_PCI_SETUP;
  302. }
  303. #endif