pci.c 3.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
  4. */
  5. #include <init.h>
  6. #include <asm/mmu.h>
  7. #include <asm/io.h>
  8. #include <common.h>
  9. #include <env.h>
  10. #include <mpc83xx.h>
  11. #include <pci.h>
  12. #include <i2c.h>
  13. #include <fdt_support.h>
  14. #include <asm/fsl_i2c.h>
  15. #include <asm/fsl_mpc83xx_serdes.h>
  16. static struct pci_region pci_regions[] = {
  17. {
  18. bus_start: CONFIG_SYS_PCI_MEM_BASE,
  19. phys_start: CONFIG_SYS_PCI_MEM_PHYS,
  20. size: CONFIG_SYS_PCI_MEM_SIZE,
  21. flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
  22. },
  23. {
  24. bus_start: CONFIG_SYS_PCI_MMIO_BASE,
  25. phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
  26. size: CONFIG_SYS_PCI_MMIO_SIZE,
  27. flags: PCI_REGION_MEM
  28. },
  29. {
  30. bus_start: CONFIG_SYS_PCI_IO_BASE,
  31. phys_start: CONFIG_SYS_PCI_IO_PHYS,
  32. size: CONFIG_SYS_PCI_IO_SIZE,
  33. flags: PCI_REGION_IO
  34. }
  35. };
  36. static struct pci_region pcie_regions_0[] = {
  37. {
  38. .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
  39. .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
  40. .size = CONFIG_SYS_PCIE1_MEM_SIZE,
  41. .flags = PCI_REGION_MEM,
  42. },
  43. {
  44. .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
  45. .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
  46. .size = CONFIG_SYS_PCIE1_IO_SIZE,
  47. .flags = PCI_REGION_IO,
  48. },
  49. };
  50. static struct pci_region pcie_regions_1[] = {
  51. {
  52. .bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
  53. .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
  54. .size = CONFIG_SYS_PCIE2_MEM_SIZE,
  55. .flags = PCI_REGION_MEM,
  56. },
  57. {
  58. .bus_start = CONFIG_SYS_PCIE2_IO_BASE,
  59. .phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
  60. .size = CONFIG_SYS_PCIE2_IO_SIZE,
  61. .flags = PCI_REGION_IO,
  62. },
  63. };
  64. static int is_pex_x2(void)
  65. {
  66. const char *pex_x2 = env_get("pex_x2");
  67. if (pex_x2 && !strcmp(pex_x2, "yes"))
  68. return 1;
  69. return 0;
  70. }
  71. void pci_init_board(void)
  72. {
  73. volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
  74. volatile sysconf83xx_t *sysconf = &immr->sysconf;
  75. volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
  76. volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
  77. volatile law83xx_t *pcie_law = sysconf->pcielaw;
  78. struct pci_region *reg[] = { pci_regions };
  79. struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
  80. u32 spridr = in_be32(&immr->sysconf.spridr);
  81. int pex2 = is_pex_x2();
  82. if (board_pci_host_broken())
  83. goto skip_pci;
  84. /* Enable all 5 PCI_CLK_OUTPUTS */
  85. clk->occr |= 0xf8000000;
  86. udelay(2000);
  87. /* Configure PCI Local Access Windows */
  88. pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
  89. pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
  90. pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
  91. pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
  92. udelay(2000);
  93. mpc83xx_pci_init(1, reg);
  94. skip_pci:
  95. /* There is no PEX in MPC8379 parts. */
  96. if (PARTID_NO_E(spridr) == SPR_8379)
  97. return;
  98. if (pex2)
  99. fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX_X2,
  100. FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
  101. else
  102. fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
  103. FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
  104. /* Configure the clock for PCIE controller */
  105. clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
  106. SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
  107. /* Deassert the resets in the control register */
  108. out_be32(&sysconf->pecr1, 0xE0008000);
  109. if (!pex2)
  110. out_be32(&sysconf->pecr2, 0xE0008000);
  111. udelay(2000);
  112. /* Configure PCI Express Local Access Windows */
  113. out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
  114. out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
  115. out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
  116. out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
  117. mpc83xx_pcie_init(pex2 ? 1 : 2, pcie_reg);
  118. }
  119. void ft_pcie_fixup(void *blob, bd_t *bd)
  120. {
  121. const char *status = "disabled (PCIE1 is x2)";
  122. if (!is_pex_x2())
  123. return;
  124. do_fixup_by_path(blob, "pci2", "status", status,
  125. strlen(status) + 1, 1);
  126. }