mpc8323erdb.c 5.8 KB

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  1. /*
  2. * Copyright (C) 2007 Freescale Semiconductor, Inc.
  3. *
  4. * Michael Barkowski <michael.barkowski@freescale.com>
  5. * Based on mpc832xmds file by Dave Liu <daveliu@freescale.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published
  9. * by the Free Software Foundation.
  10. */
  11. #include <common.h>
  12. #include <env.h>
  13. #include <init.h>
  14. #include <ioports.h>
  15. #include <mpc83xx.h>
  16. #include <i2c.h>
  17. #include <miiphy.h>
  18. #include <command.h>
  19. #include <linux/libfdt.h>
  20. #include <u-boot/crc.h>
  21. #if defined(CONFIG_PCI)
  22. #include <pci.h>
  23. #endif
  24. #include <asm/mmu.h>
  25. DECLARE_GLOBAL_DATA_PTR;
  26. const qe_iop_conf_t qe_iop_conf_tab[] = {
  27. /* UCC3 */
  28. {1, 0, 1, 0, 1}, /* TxD0 */
  29. {1, 1, 1, 0, 1}, /* TxD1 */
  30. {1, 2, 1, 0, 1}, /* TxD2 */
  31. {1, 3, 1, 0, 1}, /* TxD3 */
  32. {1, 9, 1, 0, 1}, /* TxER */
  33. {1, 12, 1, 0, 1}, /* TxEN */
  34. {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
  35. {1, 4, 2, 0, 1}, /* RxD0 */
  36. {1, 5, 2, 0, 1}, /* RxD1 */
  37. {1, 6, 2, 0, 1}, /* RxD2 */
  38. {1, 7, 2, 0, 1}, /* RxD3 */
  39. {1, 8, 2, 0, 1}, /* RxER */
  40. {1, 10, 2, 0, 1}, /* RxDV */
  41. {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
  42. {1, 11, 2, 0, 1}, /* COL */
  43. {1, 13, 2, 0, 1}, /* CRS */
  44. /* UCC2 */
  45. {0, 18, 1, 0, 1}, /* TxD0 */
  46. {0, 19, 1, 0, 1}, /* TxD1 */
  47. {0, 20, 1, 0, 1}, /* TxD2 */
  48. {0, 21, 1, 0, 1}, /* TxD3 */
  49. {0, 27, 1, 0, 1}, /* TxER */
  50. {0, 30, 1, 0, 1}, /* TxEN */
  51. {3, 23, 2, 0, 1}, /* TxCLK->CLK3 */
  52. {0, 22, 2, 0, 1}, /* RxD0 */
  53. {0, 23, 2, 0, 1}, /* RxD1 */
  54. {0, 24, 2, 0, 1}, /* RxD2 */
  55. {0, 25, 2, 0, 1}, /* RxD3 */
  56. {0, 26, 1, 0, 1}, /* RxER */
  57. {0, 28, 2, 0, 1}, /* Rx_DV */
  58. {3, 21, 2, 0, 1}, /* RxCLK->CLK16 */
  59. {0, 29, 2, 0, 1}, /* COL */
  60. {0, 31, 2, 0, 1}, /* CRS */
  61. {3, 4, 3, 0, 2}, /* MDIO */
  62. {3, 5, 1, 0, 2}, /* MDC */
  63. {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
  64. };
  65. int fixed_sdram(void);
  66. int dram_init(void)
  67. {
  68. volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  69. u32 msize = 0;
  70. if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
  71. return -ENXIO;
  72. /* DDR SDRAM - Main SODIMM */
  73. im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
  74. msize = fixed_sdram();
  75. /* set total bus SDRAM size(bytes) -- DDR */
  76. gd->ram_size = msize * 1024 * 1024;
  77. return 0;
  78. }
  79. /*************************************************************************
  80. * fixed sdram init -- doesn't use serial presence detect.
  81. ************************************************************************/
  82. int fixed_sdram(void)
  83. {
  84. volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  85. u32 msize = 0;
  86. u32 ddr_size;
  87. u32 ddr_size_log2;
  88. msize = CONFIG_SYS_DDR_SIZE;
  89. for (ddr_size = msize << 20, ddr_size_log2 = 0;
  90. (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
  91. if (ddr_size & 1) {
  92. return -1;
  93. }
  94. }
  95. im->sysconf.ddrlaw[0].ar =
  96. LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
  97. im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
  98. im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
  99. im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
  100. im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  101. im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  102. im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  103. im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  104. im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
  105. im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
  106. im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
  107. im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
  108. im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  109. __asm__ __volatile__ ("sync");
  110. udelay(200);
  111. im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
  112. __asm__ __volatile__ ("sync");
  113. return msize;
  114. }
  115. int checkboard(void)
  116. {
  117. puts("Board: Freescale MPC8323ERDB\n");
  118. return 0;
  119. }
  120. static struct pci_region pci_regions[] = {
  121. {
  122. bus_start: CONFIG_SYS_PCI1_MEM_BASE,
  123. phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
  124. size: CONFIG_SYS_PCI1_MEM_SIZE,
  125. flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
  126. },
  127. {
  128. bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
  129. phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
  130. size: CONFIG_SYS_PCI1_MMIO_SIZE,
  131. flags: PCI_REGION_MEM
  132. },
  133. {
  134. bus_start: CONFIG_SYS_PCI1_IO_BASE,
  135. phys_start: CONFIG_SYS_PCI1_IO_PHYS,
  136. size: CONFIG_SYS_PCI1_IO_SIZE,
  137. flags: PCI_REGION_IO
  138. }
  139. };
  140. void pci_init_board(void)
  141. {
  142. volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
  143. volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
  144. volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
  145. struct pci_region *reg[] = { pci_regions };
  146. /* Enable all 3 PCI_CLK_OUTPUTs. */
  147. clk->occr |= 0xe0000000;
  148. /* Configure PCI Local Access Windows */
  149. pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
  150. pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
  151. pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
  152. pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
  153. mpc83xx_pci_init(1, reg);
  154. }
  155. #if defined(CONFIG_OF_BOARD_SETUP)
  156. int ft_board_setup(void *blob, bd_t *bd)
  157. {
  158. ft_cpu_setup(blob, bd);
  159. #ifdef CONFIG_PCI
  160. ft_pci_setup(blob, bd);
  161. #endif
  162. return 0;
  163. }
  164. #endif
  165. #if defined(CONFIG_SYS_I2C_MAC_OFFSET)
  166. int mac_read_from_eeprom(void)
  167. {
  168. uchar buf[28];
  169. char str[18];
  170. int i = 0;
  171. unsigned int crc = 0;
  172. unsigned char enetvar[32];
  173. /* Read MAC addresses from EEPROM */
  174. if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_MAC_OFFSET, buf, 28)) {
  175. printf("\nEEPROM @ 0x%02x read FAILED!!!\n",
  176. CONFIG_SYS_I2C_EEPROM_ADDR);
  177. } else {
  178. uint32_t crc_buf;
  179. memcpy(&crc_buf, &buf[24], sizeof(uint32_t));
  180. if (crc32(crc, buf, 24) == crc_buf) {
  181. printf("Reading MAC from EEPROM\n");
  182. for (i = 0; i < 4; i++) {
  183. if (memcmp(&buf[i * 6], "\0\0\0\0\0\0", 6)) {
  184. sprintf(str,
  185. "%02X:%02X:%02X:%02X:%02X:%02X",
  186. buf[i * 6], buf[i * 6 + 1],
  187. buf[i * 6 + 2], buf[i * 6 + 3],
  188. buf[i * 6 + 4], buf[i * 6 + 5]);
  189. sprintf((char *)enetvar,
  190. i ? "eth%daddr" : "ethaddr", i);
  191. env_set((char *)enetvar, str);
  192. }
  193. }
  194. }
  195. }
  196. return 0;
  197. }
  198. #endif /* CONFIG_I2C_MAC_OFFSET */