mpc8308rdb.c 4.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010 Freescale Semiconductor, Inc.
  4. * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
  5. */
  6. #include <common.h>
  7. #include <hwconfig.h>
  8. #include <i2c.h>
  9. #include <init.h>
  10. #include <spi.h>
  11. #include <linux/libfdt.h>
  12. #include <fdt_support.h>
  13. #include <pci.h>
  14. #include <mpc83xx.h>
  15. #include <vsc7385.h>
  16. #include <netdev.h>
  17. #include <fsl_esdhc.h>
  18. #include <asm/io.h>
  19. #include <asm/fsl_serdes.h>
  20. #include <asm/fsl_mpc83xx_serdes.h>
  21. /*
  22. * The following are used to control the SPI chip selects for the SPI command.
  23. */
  24. #ifdef CONFIG_MPC8XXX_SPI
  25. #define SPI_CS_MASK 0x00400000
  26. int spi_cs_is_valid(unsigned int bus, unsigned int cs)
  27. {
  28. return bus == 0 && cs == 0;
  29. }
  30. void spi_cs_activate(struct spi_slave *slave)
  31. {
  32. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  33. /* active low */
  34. clrbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
  35. }
  36. void spi_cs_deactivate(struct spi_slave *slave)
  37. {
  38. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  39. /* inactive high */
  40. setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
  41. }
  42. #endif /* CONFIG_MPC8XXX_SPI */
  43. #ifdef CONFIG_FSL_ESDHC
  44. int board_mmc_init(bd_t *bd)
  45. {
  46. return fsl_esdhc_mmc_init(bd);
  47. }
  48. #endif
  49. static u8 read_board_info(void)
  50. {
  51. u8 val8;
  52. i2c_set_bus_num(0);
  53. if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
  54. return val8;
  55. else
  56. return 0;
  57. }
  58. int checkboard(void)
  59. {
  60. static const char * const rev_str[] = {
  61. "1.0",
  62. "<reserved>",
  63. "<reserved>",
  64. "<reserved>",
  65. "<unknown>",
  66. };
  67. u8 info;
  68. int i;
  69. info = read_board_info();
  70. i = (!info) ? 4 : info & 0x03;
  71. printf("Board: Freescale MPC8308RDB Rev %s\n", rev_str[i]);
  72. return 0;
  73. }
  74. static struct pci_region pcie_regions_0[] = {
  75. {
  76. .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
  77. .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
  78. .size = CONFIG_SYS_PCIE1_MEM_SIZE,
  79. .flags = PCI_REGION_MEM,
  80. },
  81. {
  82. .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
  83. .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
  84. .size = CONFIG_SYS_PCIE1_IO_SIZE,
  85. .flags = PCI_REGION_IO,
  86. },
  87. };
  88. void pci_init_board(void)
  89. {
  90. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  91. sysconf83xx_t *sysconf = &immr->sysconf;
  92. law83xx_t *pcie_law = sysconf->pcielaw;
  93. struct pci_region *pcie_reg[] = { pcie_regions_0 };
  94. fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
  95. FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
  96. /* Deassert the resets in the control register */
  97. out_be32(&sysconf->pecr1, 0xE0008000);
  98. udelay(2000);
  99. /* Configure PCI Express Local Access Windows */
  100. out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
  101. out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
  102. mpc83xx_pcie_init(1, pcie_reg);
  103. }
  104. /*
  105. * Miscellaneous late-boot configurations
  106. *
  107. * If a VSC7385 microcode image is present, then upload it.
  108. */
  109. int misc_init_r(void)
  110. {
  111. #ifdef CONFIG_MPC8XXX_SPI
  112. immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
  113. sysconf83xx_t *sysconf = &immr->sysconf;
  114. /*
  115. * Set proper bits in SICRH to allow SPI on header J8
  116. *
  117. * NOTE: this breaks the TSEC2 interface, attached to the Vitesse
  118. * switch. The pinmux configuration does not have a fine enough
  119. * granularity to support both simultaneously.
  120. */
  121. clrsetbits_be32(&sysconf->sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO);
  122. puts("WARNING: SPI enabled, TSEC2 support is broken\n");
  123. /* Set header J8 SPI chip select output, disabled */
  124. setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK);
  125. setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
  126. #endif
  127. #ifdef CONFIG_VSC7385_IMAGE
  128. if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
  129. CONFIG_VSC7385_IMAGE_SIZE)) {
  130. puts("Failure uploading VSC7385 microcode.\n");
  131. return 1;
  132. }
  133. #endif
  134. return 0;
  135. }
  136. #if defined(CONFIG_OF_BOARD_SETUP)
  137. int ft_board_setup(void *blob, bd_t *bd)
  138. {
  139. ft_cpu_setup(blob, bd);
  140. fsl_fdt_fixup_dr_usb(blob, bd);
  141. fdt_fixup_esdhc(blob, bd);
  142. return 0;
  143. }
  144. #endif
  145. int board_eth_init(bd_t *bis)
  146. {
  147. int rv, num_if = 0;
  148. /* Initialize TSECs first */
  149. rv = cpu_eth_init(bis);
  150. if (rv >= 0)
  151. num_if += rv;
  152. else
  153. printf("ERROR: failed to initialize TSECs.\n");
  154. rv = pci_eth_init(bis);
  155. if (rv >= 0)
  156. num_if += rv;
  157. else
  158. printf("ERROR: failed to initialize PCI Ethernet.\n");
  159. return num_if;
  160. }